A composite video signal processing circuit

Abstract

This utility model discloses a composite video signal processing circuit, relating to the field of image processing. It includes an image sensor, an image processor, auxiliary circuits, a video output circuit, and a software storage module. The auxiliary circuit includes a power supply circuit and a power supply voltage detection circuit. The image sensor uses a JX-F37 chip, and the image processor uses an XC5321A chip; the two are connected via corresponding pins to achieve data transmission and control. The power supply circuit converts the 5V input to 2.8V, 1.8V, 3.3V, and 1.1V voltages to power each module. The power supply voltage detection circuit uses an HE809 chip to monitor the power supply and trigger a reset in case of abnormalities. The video output circuit outputs signals after signal amplification by an MS1681 chip. This circuit has high integration, reduces component usage, lowers costs, and offers strong stability, adapting to various application scenarios.

Description

Technical Field

[0001] This utility model relates to the field of image processing, and in particular to a composite video signal processing circuit. Background Technology

[0002] With the rapid expansion of the security monitoring, smart home and vehicle imaging markets, the "video acquisition + CVBS output" solution has been given the requirement of "three lows and one high": low cost, low power consumption, low development threshold and high stability.

[0003] Therefore, there is a need for a hardware platform that integrates "sensor + ISP + DAC + power management" to reduce cost, power consumption and development complexity while ensuring image quality, and to provide a reliable and rapidly mass-producible hardware carrier for subsequent software algorithms. Utility Model Content

[0004] The technical problem this invention aims to solve is the current lack of suitable hardware circuitry for programming video signals used in vehicle status monitoring. Purchasing commercially available hardware circuitry is costly, difficult to maintain and modify, and suffers from poor hardware compatibility. The beneficial effect of this application is to provide a cost-effective and easy-to-maintain hardware circuit. This application merely provides a low-cost hardware circuit capable of being programmed and does not involve any control methods.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A composite video signal processing circuit, the key features of which include an image sensor, an image processor, auxiliary circuits, a video output circuit, and a software storage module;

[0007] The auxiliary circuit includes a power supply circuit and a power supply voltage detection circuit;

[0008] The image sensor acquires external images and inputs them to the image processor. The image processor processes the image data and outputs it to the video output circuit, where it is amplified and then output. The software storage module is connected to the graphics processor and controls the control part of the graphics processor.

[0009] The power supply circuit receives external voltage, steps it down, and then provides power input to each component; the power supply voltage detection circuit is connected to the image processor.

[0010] Preferably, the image sensor U1 uses a JX-F37 chip. The AVDD pin of this chip is connected to a 2.8V voltage, the DOVDD pin is connected to a 1.8V voltage, the DVDD pin is connected to the MVDD pin, the RSTB pin is connected to a 1.8V power supply and kept at a high level, the SDA and SCL pins are connected to the image processor, and the data output ports D0-D9, PCLK, HREF and VSYNC pins are connected to the image processor.

[0011] Preferably, the image processor U5 uses an XC5321A chip, with pins divided into a data receiving section, a power supply section, a DAC section, and a control section. In the data receiving section, Y0-Y9 are respectively connected to D0-D9, PCLK, HREF, and VSYNC pins are respectively connected to the corresponding pins of the image sensor, CCLK is connected to the EXCLK pin of the image sensor, SNR_RESET is connected to a 1.8V power supply and kept at a high level, and I2C_SCK and I2C_SDA pins are respectively connected to the SCL and SDA pins.

[0012] In the power supply section, the CVDD pin is connected to 1.1V, VDDIO1 is connected to 1.8V, VDDIO2 is connected to 3.3V, the VDDIO3 pin is grounded, the DAC_AVDD pin is connected to 3.3V, and the ground pin is grounded.

[0013] In the DAC section, the DAC_IOUT pin is connected to the video output circuit, the DAC_COMP pin is connected to 3.3V voltage, and the DAC_RESET pin is grounded.

[0014] In the control section, the SPI_CSN, SPI_SCK, SPI_MOSI, and SPI_MISO pins are connected to the software storage module; the XI and XO pins are connected to the two ends of the crystal oscillator X1; the ICR_OFF, ICR_ON, SETTING_SEL, and GPIO0 pins are connected to external inputs through pull-up resistors; and the RESETB pin is connected to the power supply voltage detection circuit.

[0015] Preferably, the power supply circuit includes 2.8V, 1.8V, 1.1V, and 3.3V power supply circuits;

[0016] The 2.8V power supply circuit includes chip U2, which uses an XC6221B282MR voltage regulator chip. Both the EN and VIN terminals of U2 are connected to a 5V power supply, and the output terminal outputs a 2.8V voltage.

[0017] The 1.8V power supply circuit includes chip U4, which uses XC6221B182MR voltage regulator chip. Both the EN and VIN terminals of U4 are connected to a 5V power supply, and the output terminal outputs a 1.8V voltage.

[0018] The 3.3V power supply circuit includes chip U8, which uses XC6221B332MR voltage regulator chip. Both the EN and VIN terminals of U8 are connected to a 5V power supply, and the output terminal outputs a 3.3V voltage.

[0019] The 1.1V power supply circuit includes U6, which uses an MT3410L chip. The VIN and SN pins of U6 are connected to a 5V power supply, and the SW pin is connected to one end of inductor L1. The other end of L1 is connected to resistor R14, the positive terminal of capacitor C27, C24, C25, C26, and C23, respectively. The other ends of capacitors C24, C25, C26, and C23 and the negative terminal of C27 are grounded. The other end of R14 is connected to the FB pin and resistor R15, respectively. The other end of R15 is grounded.

[0020] Preferably, the software storage module includes U7, which uses an M25Q41 chip. The CS pin of U7 is connected to the SPI_CSN pin of U5, the SO pin is connected to the SPI_MISO pin of U5, the SCK pin is connected to the SPI_SCK pin of U5, the SI pin is connected to the SPI_MOSI pin of U5, the WP pin is connected to one end of resistor R13, the other end of R13 is connected to a 3.3V power supply, the VCC pin and the HOLD pin are connected to a 3.3V power supply, and the VSS pin is grounded.

[0021] Preferably, the power supply voltage detection circuit includes U9, which uses the HE809 chip. The VCC pin of U9 is connected to a 3.3V power supply, the RESET pin is connected to resistor R20 and the RESETB pin of U5 respectively, the other end of R20 is connected to a 3.3V power supply, and the GND pin of U9 is grounded.

[0022] Preferably, the input terminal of the video output module is connected to the DAC_OUT pin of U5, the input terminal of the video output module is connected to the IN pin of U3 through an RC circuit, the VCC and PS pins of U3 are connected to a 3.3V power supply, the OUT pin of U3 is connected to interface 1 of external interface J1 through R1; interface 2 of J1 is grounded, and interface 3 is connected to a 5V power supply; U3 uses an MS1681 chip.

[0023] The beneficial effects of adopting the above technical solution are as follows:

[0024] This invention employs a highly integrated design, reducing the number of peripheral discrete components and lowering hardware assembly costs.

[0025] Each module power pin of this invention adopts an independent voltage regulation design, and is filtered and regulated by capacitors to ensure stable signal transmission, reduce noise interference, and guarantee image quality.

[0026] In this invention, the circuit modules are clearly divided and the interfaces of each module are clearly defined. The image processor has reserved external input pins, which can be connected to external control signals through pull-up resistors, and can flexibly adapt to extended functions such as infrared switching and parameter configuration. While the structure is simple, it improves the adaptability to multiple scenarios. Attached Figure Description

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0028] Figure 1 This is the wiring diagram of the image sensor in this utility model;

[0029] Figure 2 This is the wiring diagram of the image processor in this utility model;

[0030] Figure 3 This is a circuit diagram of the 2.8V and 1.8V power supply circuits in this utility model;

[0031] Figure 4 This is a circuit diagram of the 3.3V and 1.1V power supply circuits in this utility model;

[0032] Figure 5 This is a circuit diagram of the software storage module in this utility model;

[0033] Figure 6 This is a circuit diagram of the power supply voltage detection module in this utility model;

[0034] Figure 7 This is a circuit diagram of the video output module in this utility model;

[0035] Figure 8 This is an external wiring diagram of some pins in the image processor of this utility model. Detailed Implementation

[0036] The technical solutions of this utility model will be clearly and completely described below with reference to the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this utility model.

[0037] A composite video signal processing circuit includes an image sensor, an image processor, an auxiliary circuit, a video output circuit, and a software storage module;

[0038] The auxiliary circuit includes a power supply circuit and a power supply voltage detection circuit;

[0039] The image sensor acquires external images and inputs them to the image processor. The image processor processes the image data and outputs it to the video output circuit, where it is amplified and then output. The software storage module is connected to the graphics processor and controls the control part of the graphics processor.

[0040] The power supply circuit receives external voltage, steps it down, and then provides power input to each component.

[0041] like Figure 1 The image sensor U1 uses the JX-F37 chip. The AVDD pin of this chip is connected to a 2.8V voltage, the DOVDD pin is connected to a 1.8V voltage, and the DVDD pin is connected to the MVDD pin. The RSTB pin is connected to a 1.8V power supply and kept at a high level. The SDA and SCL pins are connected to the image processor. The data output ports D0-D9, PCLK, HREF, and VSYNC pins are connected to the image processor.

[0042] like Figure 2 Image sensor U1 acquires external image information through its internal photoelectric sensor pixel array and connects to U5 via SDA and SCL pins to receive control information. After preprocessing by U1, the image information is output to U5 through the D0-D9 data output ports. At the same time, the pixel clock and line and frame boundaries of the image are output through the PCLK, HREF and VSYNC pins to ensure the stability and efficiency of subsequent image processing.

[0043] The image processor U5 uses the XC5321A chip, with pins divided into data reception, power supply, DAC, and control sections. In the data reception section, Y0-Y9 are connected to D0-D9 respectively. The PCLK, HREF, and VSYNC pins are connected to the corresponding pins of the image sensor. CCLK is connected to the EXCLK pin of the image sensor. SNR_RESET is connected to the 1.8V power supply and kept at a high level. The I2C_SCK and I2C_SDA pins are connected to the SCL and SDA pins respectively.

[0044] The data receiving section of the image processor U5 is connected to U1 to acquire the image information output by U1 and synchronize the clock and reset signal of U1 to achieve synchronous reset.

[0045] In the power supply section, the CVDD pin is connected to 1.1V, VDDIO1 is connected to 1.8V, VDDIO2 is connected to 3.3V, the VDDIO3 pin is grounded, the DAC_AVDD pin is connected to 3.3V, and the ground pin is grounded.

[0046] In the DAC section, the DAC_IOUT pin is connected to the video output circuit, the DAC_COMP pin is connected to the 3.3V voltage, and the DAC_RESET pin is grounded; in the DAC section, DAC_OUT is responsible for outputting the processed image signal, DAC_COMP provides the reference voltage, and DAC_RESET is the reset pin;

[0047] In the control section, the SPI_CSN, SPI_SCK, SPI_MOSI, and SPI_MISO pins are connected to the software storage module; the XI and XO pins are connected to the two ends of the crystal oscillator X1; as shown... Figure 8 The ICR_OFF, ICR_ON, SETTING_SEL, and GPIO0 pins are connected to external inputs via pull-up resistors; the RESETB pin is connected to the power supply voltage detection circuit.

[0048] In the control section, OSC_XI and OSC_XO are introduced for the crystal oscillator clock, and the SPI_CSN, SPI_SCK, SPI_MOSI, and SPI_MISO pins interact with the software-accessed storage module.

[0049] The RESETB pin is responsible for resetting the system in a timely manner when a power supply abnormality occurs, ensuring the stability of circuit operation.

[0050] The power supply circuit includes 2.8V, 1.8V, 1.1V, and 3.3V power supply circuits;

[0051] like Figure 3 The 2.8V power supply circuit includes chip U2, which uses the XC6221B282MR voltage regulator chip. Both the EN and VIN terminals of U2 are connected to a 5V power supply, and the output terminal outputs a 2.8V voltage.

[0052] The 1.8V power supply circuit includes chip U4, which uses the XC6221B182MR voltage regulator chip. Both the EN and VIN terminals of U4 are connected to a 5V power supply, and the output terminal outputs a 1.8V voltage.

[0053] like Figure 4 The 3.3V power supply circuit includes chip U8, which uses XC6221B332MR voltage regulator chip. Both the EN and VIN terminals of U8 are connected to a 5V power supply, and the output terminal outputs a 3.3V voltage.

[0054] The 1.1V power supply circuit includes U6, which uses the MT3410L chip. The VIN and SN pins of U6 are connected to the 5V power supply. The SW pin is connected to one end of the inductor L1. The other end of L1 is connected to the positive terminal of resistor R14, capacitor C27, C24, C25, C26, and C23, respectively. The other ends of capacitors C24, C25, C26, and C23 and the negative terminal of C27 are grounded. The other end of R14 is connected to the FB pin and resistor R15, respectively. The other end of R15 is grounded.

[0055] The output voltage of the SW pin is regulated and filtered using a capacitor array.

[0056] like Figure 5 The software storage module includes U7, which uses the M25Q41 chip. The CS pin of U1 is connected to the SPI_CSN pin of U5, the SO pin is connected to the SPI_MISO pin of U5, the SCK pin is connected to the SPI_SCK pin of U5, the SI pin is connected to the SPI_MOSI pin of U5, the WP pin is connected to one end of resistor R13, the other end of R13 is connected to a 3.3V power supply, the VCC pin and the HOLD pin are connected to a 3.3V power supply, and the VSS pin is grounded.

[0057] like Figure 6 The power supply voltage detection circuit includes U9, which uses the HE809 chip. The VCC pin of U9 is connected to a 3.3V power supply, and the RESET pin is connected to resistor R20 and the RESETB pin of U5. The other end of R20 is connected to the 3.3V power supply, and the GND pin of U9 is grounded. When an abnormal input voltage occurs, a reset signal is output.

[0058] like Figure 7 The input terminal of the video output module is connected to the DAC_OUT pin of U5. The input terminal of the video output module is connected to the IN pin of U3 via an RC circuit. The VCC and PS pins of U3 are connected to a 3.3V power supply. The OUT pin of U3 is connected to interface 1 of external interface J1 via R1. Interface 2 of J1 is grounded, and interface 3 is connected to a 5V power supply. This module uses chip U3 to shape, amplify, and output the image signal.

[0059] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A composite video signal processing circuit, characterized by comprising: It includes an image sensor, an image processor, auxiliary circuitry, a video output circuit, and a software storage module; The auxiliary circuit includes a power supply circuit and a power supply voltage detection circuit; The image sensor acquires external images and inputs them to the image processor. The image processor processes the image data and outputs it to the video output circuit, where it is amplified and then output. The software storage module connects to the graphics processor and controls the control section of the graphics processor; The power supply circuit receives external voltage, steps it down, and then provides power input to each component; the power supply voltage detection circuit is connected to the image processor.

2. A composite video signal processing circuit according to claim 1, characterized in that, The image sensor U1 uses a JX-F37 chip. The AVDD pin of this chip is connected to a 2.8V voltage, the DOVDD pin is connected to a 1.8V voltage, and the DVDD pin is connected to the MVDD pin. The RSTB pin is connected to a 1.8V power supply and kept at a high level. The SDA and SCL pins are connected to the image processor. The data output ports D0-D9, PCLK, HREF, and VSYNC pins are connected to the image processor.

3. A composite video signal processing circuit according to claim 1, wherein The image processor U5 uses the XC5321A chip, and its pins are divided into a data receiving section, a power supply section, a DAC section, and a control section. In the data receiving section, Y0-Y9 are connected to D0-D9 respectively, PCLK, HREF, and VSYNC pins are connected to the corresponding pins of the image sensor, CCLK is connected to the EXCLK pin of the image sensor, SNR_RESET is connected to the 1.8V power supply and kept at a high level, and I2C_SCK and I2C_SDA pins are connected to the SCL and SDA pins respectively. In the power supply section, the CVDD pin is connected to 1.1V, VDDIO1 is connected to 1.8V, VDDIO2 is connected to 3.3V, the VDDIO3 pin is grounded, the DAC_AVDD pin is connected to 3.3V, and the ground pin is grounded. In the DAC section, the DAC_IOUT pin is connected to the video output circuit, the DAC_COMP pin is connected to 3.3V voltage, and the DAC_RESET pin is grounded. In the control section, the SPI_CSN, SPI_SCK, SPI_MOSI, and SPI_MISO pins are connected to the software storage module; the XI and XO pins are connected to the two ends of the crystal oscillator X1; the ICR_OFF, ICR_ON, SETTING_SEL, and GPIO0 pins are connected to external inputs through pull-up resistors; and the RESETB pin is connected to the power supply voltage detection circuit.

4. The composite video signal processing circuit according to claim 1, wherein The power supply circuit includes 2.8V, 1.8V, 1.1V and 3.3V power supply circuits; The 2.8V power supply circuit includes chip U2, which uses an XC6221B282MR voltage regulator chip. Both the EN and VIN terminals of U2 are connected to a 5V power supply, and the output terminal outputs a 2.8V voltage. The 1.8V power supply circuit includes chip U4, which uses XC6221B182MR voltage regulator chip. Both the EN and VIN terminals of U4 are connected to a 5V power supply, and the output terminal outputs a 1.8V voltage. The 3.3V power supply circuit includes chip U8, which uses XC6221B332MR voltage regulator chip. Both the EN and VIN terminals of U8 are connected to a 5V power supply, and the output terminal outputs a 3.3V voltage. The 1.1V power supply circuit includes U6, which uses an MT3410L chip. The VIN and SN pins of U6 are connected to a 5V power supply, and the SW pin is connected to one end of inductor L1. The other end of L1 is connected to resistor R14, the positive terminal of capacitor C27, C24, C25, C26, and C23, respectively. The other ends of capacitors C24, C25, C26, and C23 and the negative terminal of C27 are grounded. The other end of R14 is connected to the FB pin and resistor R15, respectively. The other end of R15 is grounded.

5. The composite video signal processing circuit according to claim 1, characterized in that, The software storage module includes U7, which uses an M25Q41 chip. The CS pin of U7 is connected to the SPI_CSN pin of U5, the SO pin is connected to the SPI_MISO pin of U5, the SCK pin is connected to the SPI_SCK pin of U5, the SI pin is connected to the SPI_MOSI pin of U5, the WP pin is connected to one end of resistor R13, the other end of R13 is connected to a 3.3V power supply, the VCC pin and the HOLD pin are connected to a 3.3V power supply, and the VSS pin is grounded.

6. The composite video signal processing circuit according to claim 1, characterized in that, The power supply voltage detection circuit includes U9, which uses the HE809 chip. The VCC pin of U9 is connected to a 3.3V power supply, the RESET pin is connected to resistor R20 and the RESETB pin of U5 respectively, the other end of R20 is connected to a 3.3V power supply, and the GND pin of U9 is grounded.

7. The composite video signal processing circuit according to claim 1, characterized in that, The input terminal of the video output circuit is connected to the DAC_OUT pin of U5. The input terminal of the video output circuit is connected to the IN pin of U3 through an RC circuit. The VCC and PS pins of U3 are connected to a 3.3V power supply. The OUT pin of U3 is connected to interface 1 of external interface J1 through R1. Interface 2 of J1 is grounded, and interface 3 is connected to a 5V power supply. U3 uses an MS1681 chip.

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