semiconductor devices

Abstract

This invention provides a semiconductor device including a device layer, a front interconnect structure disposed above the device layer and including a front power line, and a back interconnect structure disposed below the device layer and including a back power line. The device layer includes a memory cell region comprising multiple memory cells, a logic region disposed next to a first edge of the memory cell region, and an edge region disposed along a second edge of the memory cell region. The second edge is perpendicular to the first edge. The edge region includes a through-hole conductive feature electrically connected to the front power line and the back power line. The through-hole conductive feature includes a back via electrically connected to the back power line, an epitaxial feature disposed on the back via, a source / drain contact disposed on the epitaxial feature, and a top via disposed on the source / drain contact and electrically connected to the front power line.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in each generation of ICs having smaller and more complex circuits than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per unit chip area) generally increases, while geometry (i.e., the smallest component or line created through manufacturing processes) decreases. This shrinkage process typically provides benefits through increased production efficiency and reduced associated costs. This shrinkage also increases the complexity of IC handling and manufacturing.

[0003] In deep sub-micron integrated circuit technology, static random access memory (SRAM) devices have become popular storage units for high-speed communications, image processing, and system-on-chip (SoC) products. With the demands of new technology generations, the number of embedded SRAM devices in microprocessors and SoCs is increasing. As silicon technology shrinks from one generation to the next, the manufacture of traditional SRAM components and / or their manufacturing processes may face limitations. For example, aggressive reduction in IC size leads to dense spacing of source / drain features and gate structures, as well as dense spacing of source / drain contacts and gate vias thereon. In some SRAM components, a multilayer interconnect structure is formed above the source / drain contacts and gate vias of the transistors in the memory cell. This multilayer interconnect structure provides metal lines for interconnecting power and signal lines within and between the memory cells of the SRAM component. As component sizes shrink and transistor spacing becomes denser, the dimensions of some metal lines (e.g., those used for power routing) decrease. This can lead to increased parasitic resistance, increased parasitic capacitance, higher process risks, and / or poor connectivity, thereby reducing the speed of memory components. All these issues present performance, yield, and cost challenges. Therefore, while existing SRAM components are generally sufficient for their intended purpose, they are unsatisfactory in all aspects. Utility Model Content

[0004] In one exemplary aspect, the present invention relates to a semiconductor device comprising a device layer, a front interconnect structure disposed above the device layer and including a front power line, and a back interconnect structure disposed below the device layer and including a back power line. The device layer includes a memory cell region comprising a plurality of memory cells, a logic region disposed adjacent to a first edge of the memory cell region, and an edge region disposed along a second edge of the memory cell region. The second edge is perpendicular to the first edge. The edge region includes a through-hole conductive feature electrically connected to the front power line and the back power line. The through-hole conductive feature includes a back via electrically connected to the back power line, an epitaxial feature disposed on the back via, a source / drain contact disposed on the epitaxial feature, and a top via disposed on the source / drain contact and electrically connected to the front power line.

[0005] In another exemplary aspect, the present invention relates to a semiconductor device, the semiconductor device comprising a device layer, a front interconnect structure disposed above the device layer and including a first front power line and a second front power line, and a back interconnect structure disposed below the device layer and including a first back power line and a second back power line. The device layer includes a memory cell region comprising a plurality of functional memory cells, a power tap region disposed beside and along a first edge of the memory cell region, a logic region disposed between the logic region and the memory cell region beside the power tap region, and an edge region not containing functional memory cells and disposed along a second edge of the memory cell region perpendicular to the first edge. The edge region includes a first through-conducting feature electrically connected to the first front power line and the first back power line. The power tap region includes a second through-conducting feature electrically connected to the second front power line and the second back power line.

[0006] In another embodiment, the present invention relates to a semiconductor device, the semiconductor device including a device layer, a front power line disposed above the device layer, and a back power line disposed below the device layer. The device layer includes a memory cell region comprising a plurality of memory cells, wherein the plurality of memory cells includes a first active region extending along a first direction; a logic region disposed adjacent to the memory cell region and extending along a second direction perpendicular to the first direction; and an edge region disposed adjacent to the memory cell region and extending along the first direction. The edge region includes a second active region extending along the first direction. The edge region includes a through-conductive feature electrically connected to the front power line and the back power line. The second active region is disposed between the through-conductive feature and the first active region.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] The present invention can be best understood by reading the accompanying drawings in the following detailed description. It is emphasized that, according to standard practice in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 The diagram illustrates a semiconductor assembly according to some embodiments of the present invention.

[0010] Figure 2 The diagram illustrates a circuit diagram of a static random access memory (SRAM) cell according to some embodiments of the present invention.

[0011] Figure 3A The illustration shows a perspective view of a multi-gate transistor according to some embodiments of the present invention.

[0012] Figure 3B The illustration shows cross-sectional views of the layers of a semiconductor assembly according to some embodiments of the present invention.

[0013] Figure 4 The illustrations depict some embodiments according to the present invention. Figure 2 An exemplary layout of SRAM cells in the image.

[0014] Figure 5 , Figure 6 and Figure 7 The illustrations are some embodiments according to the present invention, showing different layers such as Figure 1An exemplary layout of a portion of the semiconductor component in region A is shown.

[0015] Figure 8 The illustrations are some embodiments based on the content of this utility model, such as Figure 5 , 6 7. A schematic cross-sectional view of a portion of a semiconductor assembly along the BB line.

[0016] Figure 9A and Figure 9B The figures are illustrated as some embodiments according to the present utility model, along... Figure 1 The CC and DD lines in the image, such as Figure 1 and Figures 5 to 7 A cross-sectional view of a portion of a semiconductor component.

[0017] Figure 10 , Figure 12 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 21 , Figure 22 , Figure 24 , Figure 25 and Figure 26 The illustrations are some embodiments based on the content of this utility model, such as Figure 1 The layout of a portion of the alternative semiconductor components in central region A.

[0018] Figure 11 The illustrations are some embodiments based on the content of this utility model, such as Figure 10 A schematic cross-sectional view of a portion of a semiconductor assembly along the BB line is shown.

[0019] Figure 13 The illustrations are some embodiments based on the content of this utility model, such as Figure 12 A schematic cross-sectional view of a portion of a semiconductor assembly along the BB line is shown.

[0020] Figure 20A The illustrations are some embodiments based on the content of this utility model, as follows: Figure 19 A schematic cross-sectional view of a portion of a semiconductor assembly along the EE line is shown.

[0021] Figure 20B The illustrations are some embodiments based on the content of this utility model, such as Figure 1 and Figure 19 As shown along Figure 1 The DD line is a cross-sectional view of a portion of a semiconductor component.

[0022] Figure 23A and Figure 23B The following are some embodiments based on the content of this utility model, such as Figure 22 A schematic cross-sectional view of a portion of a semiconductor assembly along the EE and FF lines is shown. Detailed Implementation

[0023] The following description of the present invention provides many different embodiments or examples for implementing different features of the present invention. To simplify the description, specific examples of components and configurations are described below. These are, of course, merely exemplary and not intended to be limiting. For example, in the following description, a first feature formed over or on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0024] Furthermore, reference numerals and / or letters may be repeated in various embodiments of this invention. Such repetition is for simplicity and clarity and does not inherently indicate a relationship between various implementations and / or configurations. Moreover, in this invention, forming, connecting to, and / or coupling to one feature on another feature may include implementations where these features are in direct contact, or implementations where additional features are formed between these features, such that these features may not be in direct contact. Furthermore, in this invention, spatially relative terms such as “down,” “up,” “horizontal,” “vertical,” “above,” “over,” “below,” “under,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate the description of the relationship between one feature and another. Spatially relative terms are intended to cover different orientations of the device including these features. Additionally, when using words such as “approximately” or “around” to describe a number or a range of numbers, unless otherwise specified, the term is intended to include numbers within plus or minus 10% of the described number. For example, the term "approximately 5 nanometers" encompasses a size range from 4.5 nanometers to 5.5 nanometers.

[0025] Static Random Access Memory (SRAM) is a type of semiconductor memory that retains data statically as long as a power supply is available. Unlike Dynamic Random Access Memory (DRAM), SRAM is faster, more reliable, and does not require constant reorganization. A memory component (such as an SRAM macro) consists of memory cells located in a memory cell region and logic cells located in a logic cell region. Memory cells, also called bit cells, are configured to store memory bits. Memory cells can be arranged in columns and rows to form arrays. Logic cells can be standard cells (STD cells), such as inverters (INV), AND, OR, NAND, NOR, flip-flops, scanners, etc. Logic cell regions are adjacent to memory cell regions and are configured to implement various logical functions. A memory component may include one or more edge regions adjacent to the memory cell regions to isolate the memory cell regions from the environment or other parts of the memory component and to contribute to uniformity in the manufacturing process.

[0026] Multilayer interconnect (MLI) structures provide metal rails (metal lines) for interconnecting the transistor gates and source / drain regions of memory cells, such as signal lines for routing bit lines and character lines to cell components, and power rails (e.g., metal lines for power supply voltage and ground) for supplying power to the cell components. Contacts and respective contact vias electrically connect the cell components to the signal lines and power rails. For example, some source / drain regions in an SRAM cell are coupled to the power supply voltage Vdd (also known as Vcc or positive power supply voltage) and / or ground Vss via source / drain contacts, source / drain contact vias, and respective metal lines in the power rails. Source / drain regions may be referred to as source or drain individually or collectively, depending on the context. Multilayer interconnect structures also provide metal lines for interconnecting power lines and signal lines between memory cells and logic cells.

[0027] As memory module 10 continues to shrink, so too do the power rails. Due to the limited available layout area and the fact that the metal lines in the power rails are typically formed to a smaller size, this inevitably leads to an increase in voltage drop across the power rails and increased power consumption, which has become a critical issue for further improving the performance of memory module 10. Therefore, while existing semiconductor manufacturing methods are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects in the case of memory module 10.

[0028] This invention generally relates to semiconductor components, such as memory components comprising a device layer. The device layer may include memory cell regions, peripheral regions, memory edge regions, and power tap regions. Memory cells may include static random access memory (SRAM) cells. Peripheral regions may be disposed at a first edge adjacent to the memory cell regions and configured to implement various logic functions. Memory edge regions may include dummy active regions and are disposed at second and third edges adjacent to the memory cell regions, the second and third edges being perpendicular to the first edge. The memory component may also include front power lines and rear power lines disposed above and below the device layer, respectively. This invention provides a memory component having various through-conducting features disposed in the memory edge regions and electrically connected to the front power lines and / or rear power lines, thereby reducing the total resistance of power supply features (e.g., through-conducting features, front power lines, rear power lines). Therefore, voltage drop and power consumption on the power supply features can be reduced. By having through-conducting features, the memory component described herein may include an increased number of memory cells without affecting the performance of the memory cells. In some embodiments, certain regions of the memory component (e.g., power tap regions) can be eliminated, thereby reducing the size of the memory component.

[0029] Now refer to Figure 1 . Figure 1 This is a simplified block diagram of the device layer (DL) of memory component 10A. Various alternatives to memory component 10A, such as memory components 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, and 10L, will be described below. For simplicity, in... Figure 1 In Figure 3, various memory components (e.g., memory components 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, and 10L) are labeled as memory component 10. For clarity and brevity, similar features in memory components 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, and 10L are identified by the same reference numerals, and similar aspects and advantages may not be repeated in the following description. To avoid confusion, the X, Y, and Z directions in the figures are perpendicular to each other and are used consistently throughout this invention.

[0030] In some embodiments, the memory component 10A includes a component layer (DL), a front-side multilayer interconnect structure (FMLI) disposed above the device layer, and a back-side multilayer interconnect structure (BMLI) disposed below the device layer. The device layer may include a circuit macro (hereinafter referred to as macro) 12. In some embodiments, macro 12 is a static random access memory (SRAM) macro, such as a single-port SRAM macro, a dual-port SRAM macro, or other types of SRAM macro. However, the present invention also contemplates embodiments where macro 12 is other types of memory, such as dynamic random access memory (DRAM), non-volatile random access memory (NVRAM), flash memory, or other suitable memory. To better understand the innovative concept of the present invention, Figure 1 This has been simplified for clarity. In other embodiments of macro 12, additional features may be added, and some features described below may be replaced, modified, or eliminated.

[0031] In some embodiments, macro 12 includes a memory cell region 15 and a peripheral region 20 adjacent to a first edge 16 of the memory cell region 15. The first edge 16 may be along the Y direction. The memory cell region 15 includes memory cells (e.g., SRAM cells), also referred to as bit cells or functional memory cells, and is configured to store memory bits. The memory cell region 15 includes at least one memory cell. Typically, the memory cell region 15 may include a plurality of memory cells arranged in columns and rows of an array.

[0032] Peripheral area 20 (also referred to as I / O peripheral area 20) includes peripheral units (also referred to as logic units) configured to implement various logical functions. The logical functions of the logic units include, for example, write and / or read decoding, wordline selecting, bitline selecting, data driving, and memory self-testing. The logical functions of the logic units described above are given for illustrative purposes. Various logical functions of the logic units are included within the scope contemplated by this invention. Peripheral area 20 includes at least one logic unit. Typically, peripheral area 20 may include a plurality of logic units to provide read and / or write operations to memory units in memory unit area 15. Logic units may be standard units, such as inverters (INV), AND, OR, NAND, NOR, flip-flops, scanners, etc.

[0033] The transistors in memory cell region 15 and peripheral region 20 can be implemented using various P-type field-effect transistors (PFETs) and N-type field-effect transistors (NFETs), such as planar transistors or non-planar transistors, including various FinFETs, gate-all-around (GAA) transistors, or combinations thereof. A gate-all-around transistor refers to a transistor having a gate surrounding a transistor channel, such as a vertically stacked gate-all-around horizontal nanowire or nanosheet metal-oxide-semiconductor field-effect transistor (MOSFET) assembly. The following description will continue to use one or more gate-all-around examples to illustrate various embodiments of the present invention. However, it should be understood that this application is not intended to be limited to a particular type of component, except as specifically claimed. For example, aspects of the present invention can also be applied to implementations based on FinFETs or planar field-effect transistors.

[0034] In the depicted embodiment, macro 12 includes power tap regions 25 (e.g., power tap regions 25a and 25b, individually or collectively referred to as power tap regions 25, depending on the context) on a first edge 16 and a second edge 17 of memory cell region 15, wherein the first edge 16 and the second edge 17 extend along the Y direction. Power tap regions 25 may extend longitudinally along the Y direction. Power tap region 25a is located between memory cell region 15 and peripheral region 20 and serves as a transition from memory cell region 15 to peripheral region 20. In some other embodiments, macro 12 does not include power tap regions 25a and / or power tap regions 25b. In some embodiments, each power tap region 25 includes an array of feedthrough vias (FTVs, described below).

[0035] In some embodiments, macro 12 includes memory edge regions 30 (e.g., memory edge regions 30a and 30b, referred to individually or collectively as memory edge regions 30, depending on the context) at the third edge 18 and fourth edge 19 of memory cell region 15. The third edge 18 and fourth edge 19 extend along the X direction. Memory edge regions 30 may be adjacent to power tap regions 25. Memory edge regions 30 may include dummy active regions and conductive features, which will be described below.

[0036] In some embodiments, macro 12 includes memory fill regions 35 located on edges 31 and 32 of memory edge regions 30, and boundary regions 40 and standard cell fills 45 located at the corners of macro 12. The memory fill regions 35, boundary regions 40, and standard cell fills 45 may each include dummy cells, dummy active regions, and / or wellstrap cells of different sizes. Dummy cells and / or dummy active regions can promote uniformity in the manufacturing and / or performance of macro 12. Wellstrap cells can promote the potential stability of N-type and P-type wells in macro 12. Dummy cells are physically and / or structurally similar to SRAM cells or logic cells, but are non-functional (e.g., do not store data). Wellstrap cells generally refer to non-functional cells configured to electrically connect voltage to N-type wells, P-type wells, or both. For example, an N-type wellstrap is configured to electrically couple an N-type well of at least one P-type transistor corresponding to an SRAM cell to a voltage source, while a P-type wellstrap is configured to electrically couple a P-type well of at least one N-type transistor corresponding to an SRAM cell to a voltage source.

[0037] Figure 2 This is a circuit diagram of an exemplary SRAM cell 60 according to various aspects of the present invention, which can be implemented as a memory cell of an SRAM array. In some embodiments, the SRAM cell 60 is located in the memory cell region 15 of macro 12 ( Figure 1 This is implemented as follows. In the illustrated embodiment, SRAM cell 60 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, SRAM cell 60 can be other types of memory cells, such as dual-port memory cells or memory cells with more than six transistors. To clearly understand the innovative concept of this utility model, Figure 2 This has been simplified. Additional features can be added to the single-port SRAM cell 60, and in other embodiments of the single-port SRAM cell 60, some of the features described below can be replaced, modified, or eliminated.

[0038] An exemplary SRAM cell 60 includes six transistors: a pass-gate transistor PG-1, a channel gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the channel gate transistors PG-1 and PG-2 provide access to a storage portion of the SRAM cell 60, which includes a pair of cross-coupled inverters, inverter 82 and inverter 84. Inverter 82 includes pull-up transistor PU-1 and pull-down transistor PD-1, and inverter 84 includes pull-up transistor PU-2 and pull-down transistor PD-2. In some embodiments, pull-up transistors PU-1 and PU-2 are configured as P-type fin field-effect transistors or P-type gate full-loop transistors, and pull-down transistors PD-1 and PD-2 are configured as N-type fin field-effect transistors or N-type gate full-loop transistors.

[0039] The gate of pull-up transistor PU-1 is located between its source (electrically coupled to the power supply voltage (Vdd)) and the first common drain (CD1), while the gate of pull-down transistor PD-1 is located between its source (electrically coupled to the power supply voltage (Vss), which may be electrically grounded) and the first common drain. The gate of pull-up transistor PU-2 is located between its source (electrically coupled to the power supply voltage (Vdd)) and the second common drain (CD2), while the gate of pull-down transistor PD-2 is located between its source (electrically coupled to the power supply voltage (Vss)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) storing true form data, and the second common drain (CD2) is a storage node (SNB) storing complementary form data. The gates of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to a second common drain (CD2), while the gates of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to a first common drain (CD1). The gate of channel gate transistor PG-1 is located between its source (electrically coupled to bit line BL) and drain, and its drain is electrically coupled to the first common drain (CD1). The gate of channel gate transistor PG-2 is located between its source (electrically coupled to complementary bit line BLB) and drain, and its drain is electrically coupled to the second common drain (CD2). The gates of channel gate transistors PG-1 and PG-2 are electrically coupled to the character line WL. In some embodiments, channel gate transistors PG-1 and PG-2 provide access to storage nodes SN and SNB during read and / or write operations. For example, channel gate transistors PG-1 and PG-2 couple storage nodes SN and SNB to bit lines BL and BLB, respectively, in response to applying voltage to the gates of channel gate transistors PG-1 and PG-2 via character line WL.

[0040] Figure 3A The diagram is a perspective view of a multi-gate transistor 100, which can serve as any transistor in the memory component 10, such as an SRAM cell 60. Figure 2 Any transistor, including pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, pull-down transistor PD-2, transfer gate transistor PG-1, and transfer gate transistor PG-2. In some embodiments, the multi-gate transistor 100 is a fin field-effect transistor (FinFET) that includes a channel region composed of a fin-like structure. In some embodiments, the multi-gate transistor 100 is a gate all-around (GAA) transistor that includes a channel region composed of vertically stacked horizontally guided nanostructures (e.g., nanowires or nanosheets).

[0041] In the illustrated embodiment, a multi-gate transistor 100 is formed on a substrate 102. The substrate 102 may include elemental (single-element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 102 may be a single-layer material with a uniform composition. Alternatively, the substrate 102 may include multiple material layers with similar or different compositions suitable for IC component fabrication. In one example, the substrate 102 may be a silicon-on-insulator (SOI) substrate with a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 102 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain (S / D) regions, may be formed in or on the substrate 102. The doped regions can be doped with N-type dopants (such as phosphorus or arsenic) and / or P-type dopants (such as boron) according to design requirements. The doped regions can be formed directly on substrate 102, in a P-type well structure, in an N-type well structure, in a double-well structure, or using a raised structure. The doped regions can be formed through dopant atom implantation, in-situ doped epitaxial growth, and / or other suitable techniques.

[0042] A three-dimensional active region 104 is formed on the substrate 102. The active region for a transistor refers to the region under the gate structure of the transistor where the source region, drain region, and channel region are formed.

[0043] Because active regions are sometimes located within and defined by silicon oxide isolation features (such as shallow trench isolation, STI), active regions may be referred to as oxide-defined regions or "ODs". Active region 104 includes a source region 106a, a drain region 106b, a channel region sandwiched between the source region 106a and the drain region 106b (located below the gate structure 110), and a fin base 112 disposed on the source region 106a, the drain region 106b, and the channel region. The source region 106a and the drain region 106b may also be individually or collectively referred to as source / drain (S / D) regions 106. In some embodiments, the source / drain region 106 is formed by an epitaxial growth feature, also referred to as source / drain feature 106 or source / drain epitaxial feature 106. The fin base 112 protrudes from the substrate 102. In a fin field-effect transistor, the channel region below the gate structure 110 can be a fin-like structure extending continuously upward from the fin base 112. In a gate full-ring transistor, the channel region below the gate structure 110 can be a vertically stacked, horizontally oriented nanostructure suspended above the fin base 112. The suspended nanostructure is connected to the opposing source region 106a and drain region 106b.

[0044] An SRAM cell includes multiple active regions. In some embodiments, the active regions are formed (e.g., Figure 3A The three-dimensional active region 104 shown includes the top of a patterned substrate in a patterning process. For example, the active region 104 can be patterned using one or more photolithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-aligned processes, allowing for the fabrication of patterns with smaller pitches than achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Using a self-aligned process, spacers are formed alongside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the active region 104.

[0045] In some embodiments, isolation structure 114 is deposited on the sidewall of fin base 112. Isolation structure 114 electrically isolates active region 104 from other active regions. In some embodiments, isolation structure 114 is shallow trench isolation (STI), field oxide (FOX), or other suitable electrical isolation features.

[0046] Still refer to Figure 3AIn some embodiments, the gate structure 110 includes a gate dielectric layer 116 and a gate 118 formed above the gate dielectric layer 116. In a fin field-effect transistor, the gate structure 110 is positioned on the sidewalls and top surface of the fin. In a gate full-ring transistor, the gate structure 110 encloses each channel layer (such as a nanowire or nanosheet). Thus, the gate structure 110 defines a portion of the active region 104 beneath it as a channel region. In some embodiments, the gate dielectric layer 116 is a dielectric material with a high dielectric constant (high k). High dielectric materials have a higher dielectric constant (k) than silicon dioxide. Examples of high dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high dielectric materials, or combinations thereof. In some embodiments, the gate 118 is composed of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials.

[0047] In some embodiments, gate spacer 120 is deposited on the sidewall of gate structure 110. In some embodiments, gate spacer 120 is composed of silicon nitride, silicon oxynitride, silicon carbide, other suitable materials, or combinations thereof.

[0048] In some embodiments, a portion of the active region 104 not covered by the gate structure 110 and the gate spacer 120 serves as the source / drain region 106. In some embodiments, the source / drain region 106 of a P-type transistor (e.g., pull-up transistors PU-1, PU-2) is formed by implanting P-type impurities (such as boron, indium, or the like) into a portion of the active region 104 not covered by the gate structure 110 and the gate spacer 120. In some embodiments, the source / drain region 106 of an N-type transistor (e.g., pass-gate transistors PG-1, PG-2, pull-down transistors PD-1, PD-2) is formed by implanting N-type impurities (such as phosphorus, arsenic, antimony, or the like) into a portion of the active region 104 not covered by the gate structure 110 and the gate spacer 120.

[0049] In some embodiments, the source / drain region 106 is formed by etching a portion of the active region 104 not covered by the gate structure 110 and the gate spacer 120 to form a trench, and growing epitaxial features in the trench. The epitaxial features may be formed of Si, Ge, SiP, SiC, SiPC, SiGe, SiAs, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, C, or combinations thereof. Therefore, in some exemplary embodiments, the source / drain region 106 may be formed of silicon germanium (SiGe), while the remaining active region 104 may be formed of silicon. In some embodiments, during the epitaxial growth of the source / drain region 106 of the P-type transistor (e.g., pull-up transistors PU-1, PU-2), P-type impurities are in-situ doped into the source / drain region 106. Furthermore, during the epitaxial growth of the source / drain regions 106 of the N-type transistors (e.g., channel gate transistors PG-1, PG-2 and pull-down transistors PD-1, PD-2), N-type impurities are in situ doped into the source / drain regions 106.

[0050] Figure 3B The illustration shows partial schematic cross-sectional views of various layers (layers) that can be fabricated above and below a semiconductor substrate (or wafer) to form part of a memory assembly (such as...). Figure 1 Memory component 10). For example... Figure 3B As shown, the various layers include the device layer DL, the front multilayer interconnect structure FMLI disposed above the device layer, and the back multilayer interconnect structure BMLI disposed below the device layer.

[0051] The device layer includes devices (such as transistors, resistors, capacitors, and / or inductors) and / or device components (such as doped wells, gate structures, and / or source / drain features). In the embodiment shown in FIG3, the device layer includes a substrate 102 as described above, doped regions 122 disposed in the substrate 102 (e.g., N-type wells 122N and / or P-type wells 122P), an isolation structure 114, and a transistor 100. In the illustrated embodiment, the transistor 100 includes a suspended channel layer (nanostructure) 124 disposed between source / drain features 106 to connect with a gate structure 110, wherein the gate structure 110 encloses and / or surrounds the suspended channel layer 124. Each gate structure 110 has a metal gate stack formed from a gate 118 disposed above a gate dielectric layer 116. Gate spacers 120 are disposed along the sidewalls of the metal gate stack.

[0052] The front-side multilayer interconnect (FMLI) and back-side multilayer interconnect (BMLI) electrically couple device layers to various devices and / or components, enabling these devices and / or components to operate according to the design requirements of the memory module. Each of the front-side and back-side multilayer interconnects may include one or more interconnect layers. In the illustrated embodiment, the front-side multilayer interconnect includes a contact interconnect layer (CO layer), a zero-thorough-hole interconnect layer (V0 layer), a zero-thorough-metal interconnect layer (M0 layer), a first-thorough-hole interconnect layer (V1 layer), a first-thorough-metal interconnect layer (M1 layer), a second-thorough-hole interconnect layer (V2 layer), a second-thorough-metal interconnect layer (M2 layer), a third-thorough-hole interconnect layer (V3 layer), and a third-thorough-metal interconnect layer (M3 layer). Each CO layer, V0 layer, M0 layer, V1 layer, M1 layer, V2 layer, M2 layer, V3 layer, and M3 layer may be referred to as a metal layer. The metal line formed on the M0 layer may be referred to as an M0 metal line. Similarly, the vias or metal lines formed in layers V1, M1, V2, M2, V3, and M3 can be referred to as V1 vias, M1 metal lines, V2 vias, M2 metal lines, V3 vias, and M3 metal lines, respectively. The front-side multilayer interconnect layer considered in this invention has more or fewer interconnect layers and / or layers; for example, the total number of interconnect layers (layers) in the front-side multilayer interconnect layer is N, where N is an integer ranging from 1 to 10. Each layer of the front-side multilayer interconnect layer includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric layers and etch stop layers (ESL)). The dielectric layers of the front-side multilayer interconnect layer are collectively referred to as dielectric structure 126. In some embodiments, the conductive features of the front-side multilayer interconnect layer in the same layer (e.g., layer M0) are formed simultaneously. In some embodiments, the conductive features of the front-side multilayer interconnect layer in the same layer have top surfaces that are substantially planar with each other and / or bottom surfaces that are substantially planar with each other.

[0053] exist Figure 3BIn the illustrated embodiment, the CO layer includes a source / drain contact MD disposed in the dielectric structure 126. The source / drain contact MD can be formed on and in direct contact with the silicide layer, which is directly disposed on the source / drain feature 106. The VO layer includes a gate via VG disposed on the gate structure 110 and a source / drain contact via VD disposed on the source / drain contact MD, wherein the gate via VG connects the gate structure 110 to the M0 metal line, and the source / drain via VD connects the source / drain contact MD to the M0 metal line. In some embodiments, the VO layer may further include a mating contact disposed in the dielectric structure 126. The V1 layer includes a V1 via disposed in the dielectric structure 126, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 layer includes the M1 metal line disposed in the dielectric structure 126. The V2 layer includes a V2 via disposed in the dielectric structure 126, wherein the V2 via connects the M1 metal line to the M2 metal line. The M2 layer includes an M2 metal line disposed in the dielectric structure 126. The V3 layer includes a V3 via disposed in the dielectric structure 126, wherein the V3 via connects the M2 metal line to the M3 metal line.

[0054] In the described embodiment, the back-side multilayer interconnect structure BMLI includes a zeroth back-side via layer (BV0 layer), a zeroth back-side metal layer (BM0 layer), a first back-side via layer (BV1 layer), and a first back-side metal layer (BM1 layer). Each of the BV0, BV0, BV1, and BM1 layers can be referred to as a metal layer. The metal line formed in the BM0 layer can be referred to as a BM0 metal line. Similarly, the vias or metal lines formed in the BV0, BV1, and BM1 layers can be referred to as BV0 vias, BV1 vias, and BM1 metal lines, respectively. This invention takes into account that the back-side multilayer interconnect structure BMLI has more or fewer interconnect layers and / or layers, for example, the total number of M interconnect layers (layers) in the back-side multilayer interconnect structure, where M is an integer in the range of 1 to 10. Each layer of the back-side multilayer interconnect structure includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and etch stop layers (ESL)). The dielectric layers of the back-side multilayer interconnect structure are collectively referred to as back-side dielectric structure 126'. In some embodiments, conductive features formed in the same layer (e.g., a BMO layer) of the back-side multilayer interconnect structure are formed simultaneously. In some embodiments, conductive features formed in the same layer of the back-side multilayer interconnect structure have top surfaces and / or bottom surfaces that are substantially planar with each other.

[0055] exist Figure 3BIn the illustrated embodiment, the BVO layer includes BVO vias formed beneath the device layer. For example, a BVO via may include one or more back-side source / drain vias formed directly beneath the source / drain features 106 of the device layer and coupled to those features 106 via a silane layer. A BVO via may include one or more back-side gate vias formed directly beneath and in direct contact with the gate structure 110 of the device layer. The BMO layer includes BMO metal lines formed beneath the BVO layer. Back-side gate vias (not shown) connect the gate structure 110 to the BMO metal lines, while back-side source / drain vias connect the source / drain features to the BMO metal lines. The BV1 layer includes BV1 vias disposed in the back-side dielectric structure 126', whereby the BV1 vias connect the BMO metal lines to the BM1 metal lines. The BM1 layer includes BM1 metal lines formed beneath the BV1 layer.

[0056] Figure 3B For clarity and to better understand the innovative concept of this utility model, simplification is provided. Additional features may be added to the various layers of the memory component, and in other embodiments of the memory component, some described features may be replaced, modified, or eliminated. Figure 3B This is just an example and may not reflect the actual cross-sectional view of the memory component 10, which will be described in further detail below.

[0057] Figure 4 The diagram is as follows Figure 2 An exemplary layout 200 of the SRAM cell 60. Figure 4 The boundary of the SRAM cell 60 is illustrated using a dashed rectangle 202. Rectangle 202 is longer in the Y direction than in the X direction.

[0058] SRAM cell 60 includes active regions 104 (e.g., active regions 104A, 104B, 104C, and 104D) extending in the X-direction to connect with gate structures 110 (e.g., gate structures 110A, 110B, 110C, and 110D) extending in the Y-direction. Active regions 104B and 104C are disposed above an N-type well (or N-type well) 122N. Active regions 104A and 104D are disposed above a P-type well (or P-type well) 122P located on either side of the N-type well 122N in the Y-direction. Gate structures 110 are combined with channel regions (e.g., 215A, 215B, ..., 215F) of the respective active regions 104 to form transistors. In this regard, gate structure 110A is combined with channel region 215A of active region 104A to form an N-type transistor as a transmission gate transistor PG-1; gate structure 110B is combined with channel region 215B of active region 104A to form an N-type transistor as a pull-down transistor PD-1, and is combined with channel region 215C of active region 104B to form a P-type transistor as a pull-up transistor PU-1; gate structure 110C is combined with channel region 215E of active region 104D to form an N-type transistor as a pull-down transistor PD-2, and is combined with channel region 215D of active region 104C to form a P-type transistor as a pull-up transistor PU-2; gate structure 110D is combined with channel region 215F of active region 104D to form an N-type transistor as a transmission gate transistor PG-2.

[0059] Different active regions 104 in different transistors of SRAM cell 60 can have the same or different widths (e.g., dimensions measured along the Y direction) to optimize component performance. More specifically, active regions 104A and 104D can each have a first width W1 extending along the Y direction, and active regions 104B and 104C can each have a second width W2 extending along the Y direction. The second width W2 can be equal to or less than the first width W1. For example, the ratio of the first width W1 to the second width W2 (W1 / W2) can be in the range of approximately 1 to approximately 4. This can balance the speed between N-type and P-type transistors to optimize SRAM performance.

[0060] Continue to refer to Figure 4The SRAM cell 60 further includes a source / drain contact (the source / drain regions are located on both sides of their respective channel regions) disposed above the source / drain regions of the active region 104, a mating contact (Butt_CO) 209 disposed above and connected to the active region 104B and the gate structure 110C, another mating contact 209 disposed above and connected to the active region 104C and the gate structure 110B, a source / drain contact via VD disposed above and connected to the source / drain contact, and two gate vias VG disposed above and connected to the gate structures 110A and 110D, respectively. Figure 4 Further illustrated as circuit nodes Vss node, Vdd node, bitline node, and bitline bar node (or BLB node), corresponding to respectively Figure 2 The circuit nodes Vss, Vdd, BL, and BLB are used in the circuit. The bit line bar is also called the complementary bit line or inverse bit line. For example... Figure 4 As shown, in layout 200, source / drain contact vias VD and gate vias VG can be positioned on the boundary of SRAM cell 60 (e.g., on the dashed line of rectangle 202) because source / drain contact vias VD and gate vias VG can be shared by adjacent SRAM cells to electrically couple their respective signal lines.

[0061] Still refer to Figure 4The SRAM cell 60 further includes a plurality of gate-cut dielectric features extending along the X direction, including dielectric features 252A, 252B, 252C, and 252D (collectively referred to as dielectric feature 252). In the illustrated embodiment, dielectric feature 252A is disposed between active regions 104C and 104D and adjacent to gate structures 110B and 110D. Dielectric feature 252A divides the originally continuous gate structure into two independent blocks corresponding to gate structures 110B and 110D. Similarly, dielectric feature 252B is disposed between active regions 104A and 104B and adjacent to gate structures 110A and 110C. Dielectric feature 252B divides the originally continuous gate structure into two independent blocks corresponding to gate structures 110A and 110C. Dielectric feature 252C is disposed between active region 104A and the active region in the SRAM cell adjacent to the left of SRAM cell 60, and separates gate structure 110B from the gate structure in the adjacent SRAM cell. Similarly, dielectric feature 252D is disposed between active region 104D and the active region in the SRAM cell adjacent to the right of SRAM cell 60, and separates gate structure 110C from the gate structure in the adjacent SRAM cell. Each dielectric feature 252 is formed by filling a corresponding diced metal gate (CMG) trench at the location of the dielectric feature. Dielectric feature 252 is also referred to as a CMG feature. In the illustrated embodiment, each dielectric feature 252A, 252B is disposed above the interface between N-type well 122N and the corresponding P-type well 122P, while dielectric features 252C, 252D are disposed above the corresponding P-type well 122P.

[0062] CMG (Cut Metal Gate) technology refers to a manufacturing process in which, after a metal gate (e.g., a high dielectric constant metal gate, HKMG) replaces a dummy gate structure (e.g., a polysilicon gate), the metal gate is diced (e.g., by an etching process) to separate it into two or more gate blocks. Each gate block serves as the metal gate of a single transistor. Subsequently, an isolation material is filled into trenches between adjacent metal gate portions. In this invention, these trenches are referred to as diced metal gate trenches or CMG trenches. The dielectric material filling the CMG trenches for isolation is called a CMG feature. To ensure complete dicing of the metal gate, the CMG feature typically extends into adjacent areas, such as a dielectric layer filling the space between the metal gates. CMG features typically have an elongated shape in a top view. For example, as shown... Figure 4 As shown, each CMG feature 252 has a strip shape extending along the X direction.

[0063] Figures 5 to 7 The drawing is as follows Figure 1An exemplary layout of the memory component 10A portion in region A, wherein Figure 5 The layout is shown for the DL layer, CO layer, and V0 layer. Figure 6 The layout is shown for the DL layer, BV0 layer, and BMO layer. Figure 7 The layout is shown as layers V0, M0, V1, and M1. Figure 8 Draw as along Figures 5 to 7 A cross-sectional view of region A of memory component 10A in the BB line.

[0064] Reference Figure 6 For simplicity, the layout within the boundary region 40, standard cell fill 45, and peripheral region 20 is not shown. Dashed lines 16, 18, and 31 illustrate the first edge 16 and the third edge 18 of the memory cell region 15, and the edge 31 of the memory edge region 30, respectively. As shown, the memory assembly 10A includes an N-type well 122N and a P-type well 122P, and a plurality of active regions 104 disposed above the N-type well 122N and the P-type well 122P. The active region 104 disposed above the P-type well 122P may be an N-type active region (e.g., including source / drain features with N-type dopant). The active region 104 disposed above the N-type well 122N may be a P-type active region (e.g., including source / drain features with P-type dopant). The active regions 104 are arranged along the Y direction and extend along the X direction. As described above, in the memory cell region 15, the active regions 104 may have the same or different widths along the Y direction as described above. For example, in memory cell region 15, active regions 104 above N-type wells 122N each have a width W2, while active regions 104 above P-type wells 122P each have a width W1. Gate structures 110 are disposed above the active regions 104 and extend along the Y direction. In the illustrated embodiment, the gate structures 110 are uniformly distributed along the X direction, with a uniform distance between adjacent gate structures 110. The uniform distance (which may be the minimum center-to-center distance between two adjacent gate structures 110 along the X direction) is represented as gate pitch or polysilicon pitch PP. Gate structures 110 intersect with active regions 104 to form transistors, such as transistor 100 as described above. Transistors formed at the intersection of active regions 104 and gate structures 110 within memory cell region 15 are used to form SRAM cells. Contacts (e.g., source / drain contacts MD) are disposed above and electrically connected to the source / drain regions of active regions 104. A V0 via (e.g., a source / drain contact via VD) can be disposed above the source / drain contact MD. To better understand the concept of this invention, Figure 5 It has been simplified to improve clarity. For example, Figure 5The diagram shows the active region 104, gate structure 110, source / drain contact MD, and source / drain contact via VD, while some other features (e.g., gate via VG, mating contact, gate cut dielectric features) are omitted.

[0065] In memory cell region 15, dashed line 128 indicates that the boundary of the SRAM cell is a rectangular box. In the illustrated embodiment, transistors in memory cell region 15 form a plurality of SRAM cells 60 as described above (e.g., SRAM cells 60a, 60b, 60c, 60d, collectively referred to as SRAM cells 60). The SRAM cells 60 are arranged in the X and Y directions to form an SRAM cell array. Each SRAM cell 60 in array form can use, for example... Figure 4 The layout 200 of the SRAM cells 60 is shown. In some embodiments, two adjacent SRAM cells 60 in the X direction are line symmetric with respect to their common boundary, and two adjacent SRAM cells 60 in the Y direction are line symmetric with respect to their common boundary. That is, SRAM cell 60b is a duplicate cell of SRAM cell 60a, but flipped over the Y-axis; SRAM cell 60c is a duplicate cell of SRAM cell 60a, but flipped over the X-axis; and SRAM cell 60d is a duplicate cell of SRAM cell 60b, but flipped over the X-axis. SRAM cells 60 may be repeated in an array in a similar manner. Some active regions 104 extend through multiple SRAM cells in the form of rows. For example, active regions 104A and 104D extend through at least SRAM cells 60b and SRAM cells 60a.

[0066] In some embodiments, the memory edge region 30 includes a continuous active region 104E and discontinuous active regions (e.g., active regions 104F, 104G, and 104I). In the depicted embodiments, active regions 104E and 104I are located above a P-type well 122P and are N-type active regions with N-type source / drain characteristics 106, while active regions 104F and 104G are located above an N-type well 122N and are P-type active regions with P-type source / drain characteristics 106. The width W3 of active regions 104E and 104I along the Y direction may be approximately the same as the width W1. In some embodiments, active regions 104F and 104G each have a width W4 along the Y direction, which may be equal to or greater than the width W1. In some embodiments, the ratio of width W4 to width W2 is in the range of approximately 3 to approximately 9. If the width W4 is too small, the resistance of the through-conductivity feature formed by the active regions 104F and 104G may be too large, and therefore the benefit of the described structure may be too small. If the width W4 is too large, the distance S1' between the active regions 104G (or 104F) and 104E may be too small, and therefore the isolation between the active regions 104G / 104F and 104E may be too small. The distance S1' can be equal to or greater than the distance S1 between the active regions 104D and 104E. The memory edge region 30 may further include more discontinuous active regions aligned in the X direction with and to the left of the active regions 104F and 104G, and located above the N-type well 122N.

[0067] Reference Figure 5 and Figure 8In some embodiments, the memory edge region 30 includes source / drain contacts MDs disposed over discontinuous active regions 104, such as active regions 104F and 104G (also referred to for clarity and simplicity as "source / drain contacts over dummy oxide boundaries"). The source / drain contacts over dummy oxide boundaries (MDs over dummy oxide boundaries) may each be disposed over only one source / drain feature 106. In the illustrated embodiment, the source / drain contacts over dummy oxide boundaries are disposed over each source / drain feature 106 of active regions 104F and 104G. In some other embodiments, the source / drain contacts over dummy oxide boundaries are disposed over some source / drain features 106 of active regions 104F and 104G. In other words, some source / drain features 106 of active regions 104F and 104G do not have source / drain contacts (MD over dummy OD) disposed above the dummy oxide boundary regions above them. In the illustrated embodiment, memory edge region 30 further includes source / drain contact vias VD (also referred to as VD 138 for clarity and simplicity) disposed above the source / drain contacts (MD over dummy OD) above each dummy oxide boundary region.

[0068] In some embodiments, the memory filling region 35 includes an active region 104H disposed above a P-shaped well 122P. The active region 104H may have a width W5 along the Y direction, which is smaller than the width W1 and larger than the width W2.

[0069] In some embodiments, the power tap region 25 includes an active region 104J aligned in the X direction with the active region 104 on the P-type well 122P in the memory cell region 15. The power tap region 25 also includes a feedthrough via 130 between adjacent active regions 104J. From a top view, the feedthrough via 130 may be surrounded by a dielectric layer 132. The dielectric layer 132 isolates the feedthrough via 130 from the surrounding gate structure 110. The dielectric layer 132 may include silicon dioxide, a silicon dioxide-containing material, or a dielectric layer with a low dielectric constant, such as tetraethoxysilane (TEOS) oxide, undoped silicate glass (USG), doped silicon dioxide such as borophospho-silicate glass (BPSG), fluorinated glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In various examples, the dielectric layer 132 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In an embodiment, feedthrough vias 130 are arranged along the Y direction. The feedthrough vias 130 extend through the device layer DL and can provide front-to-back electrical routes between the front-side multilayer interconnect structure FMLI and the back-side multilayer interconnect structure BMLI, and each may include one or more conductive features connected together (e.g., a back-side contact 134 and a front-side contact 136 disposed above the back-side contact 134). The back-side contact 134 may contact a BMO metal line, while the front-side contact 136 may contact a MO metal line. Each BMO metal line and MO metal line may be electrically connected to a power supply voltage (Vdd or Vss). In some embodiments, the back contact 134 comprises tungsten (W), while the front contact 136 comprises aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), or tungsten (W). One or more conductive features of the feedthrough via (FTV) 130 can be formed by performing patterning and photolithography processes to create trenches through a portion of the dielectric layer 132, and then filling the trenches with metallic features. In the depicted embodiment, the power tap region 25 has a span of five polysilicon pitch (PP) along the X direction between the first edge 16 of the memory cell region 15 and the corresponding edge of the peripheral region 20.

[0070] Reference Figure 6 and Figure 8The memory component 10A may further include a back via BV0 disposed below the source / drain features 106 of the active regions 104F and 104G in the memory edge region 30 and the source / drain features 106 of the active region 104 (e.g., 104D) in the memory cell region 15. The back via BV0 is electrically connected to the corresponding source / drain features 106 below it and the BM0 metal lines (e.g., BM0-1, BM0-2, BM0-3, BM0-4). For clarity and simplicity, the back via BV0 disposed directly below the discontinuous active regions 104 (e.g., active regions 104F and 104G) in the memory edge region 30 is also referred to as a back via BV0 142. A back-side via BV0 142 may be disposed beneath each source / drain feature 106 of the discontinuous active region 104 in the memory edge region 30, and together form a discontinuous rail, which may be referred to as a back-side via rail (BV0 rail). In the illustrated embodiment, metal line BMO-1 is a Vdd power line (e.g., a metal line electrically connected to the Vdd potential, also referred to as a positive power supply line), while metal lines BMO-2, BMO-3, and BMO-4 are Vss power lines (e.g., metal lines electrically connected to the Vss potential, also referred to as ground lines). Therefore, the BV0 rail is electrically connected to the back-side Vdd power line (e.g., metal line BMO-1), while the back-side vias BV0, except for the back-side via BV0 142, are electrically connected to the back-side Vss power lines. The feedthrough via FTV 130 can be electrically connected to a rear-side Vdd power line (e.g., metal line BM0-1) or a rear-side Vss power line (e.g., metal lines BM0-2, BM0-3, and BM0-4). The BM0 metal line may have a width W6 along the Y direction. The width W6 may be greater than the width W4. In some embodiments, the width W6 is approximately the sum of the widths W1 and W3 and the distance S1. The BM0 metal line may extend from below the memory edge region 30 and the memory cell region 15 to below the standard cell fill 45, the boundary region 40, and the peripheral region 20.

[0071] Reference Figure 7 and Figure 8The source / drain contact via VD is connected to the M0 metal lines (e.g., metal lines M0-1, M0-2, M0-3) above it. The M0 metal lines can extend from above the memory edge region 30 and memory cell region 15 to above the standard cell fill 45, boundary region 40, and peripheral region 20. The M0 metal lines can be connected to the M1 metal lines (e.g., metal line M1-1) via V1 vias. For example, metal lines M0-1, M0-2, and M0-3 are connected to the M1-1 metal line via V1 vias. In some embodiments, metal lines M0-1, M0-2, and M0-3 are Vdd power lines. Therefore, the source / drain features 106 of the active regions 104F and 104G in the memory edge region 30 are electrically connected to the Vdd power lines via source / drain contacts MD (e.g., source / drain contacts MD above the dummy oxide boundary region) and source / drain contact vias VD (e.g., source / drain contact vias VD 138). Arrows indicate exemplary electrical paths 144 from metal line M0-1 to other Vdd power lines M0-2 and M0-3. It should be understood that the connections between metal lines M0-1, M0-2, and M0-3 (e.g., vias V1 and metal line M1-1) are for illustrative purposes only and should not be construed as limiting the scope of this invention. Electrical path 144 may be formed by other connections. Feedthrough via FTV 130 may be electrically connected to the front-side Vdd power lines (e.g., metal lines M1-1, M0-1, M0-2, and M0-3) or the front-side Vss power lines.

[0072] Reference Figure 8 In some embodiments, the memory component 10A includes through-through conductive features 150 located in the memory edge region 30. Each through-through conductive feature 150 may be formed in a discontinuous active region (e.g., active regions 104F and 104G) in the memory edge region 30 and may include a source / drain contact via VD, a source / drain contact MD, a source / drain feature 106, and a back-side via BV0 142. The memory edge region 30 may include a plurality of through-through conductive features 150 arranged in the X direction. The discontinuous active regions may be separated from each other by an isolation structure 114 and dielectric fin-cut features 151. The source / drain contact via VD and the source / drain contact MD may be surrounded by a dielectric structure 126, and the back-side via BV0 142 may be surrounded by a back-side dielectric structure 126'.

[0073] Figure 9A and 9B They are drawn as along Figure 1 A schematic side view of a portion of the memory assembly 10A with the CC and DD lines. For simplicity, the structure in the device layer DL of the memory cell region 15 is not shown. Figure 9Aand 9B The number of metal wires and metal through holes, as well as the connections between them, are for illustrative purposes only and should not be construed as limiting the scope of this utility model. Figure 9A The metal wires in the can include those with Figure 9B The metal wires in the reference are the same and / or different metal wires. Figure 9A The feedthrough via FTV 130 in power tap regions 25a and 25b can be electrically connected to the M0 metal line, and then electrically connected to other metal lines in the front-side multilayer interconnect structure FMLI. In an embodiment, the feedthrough via FTV 130 is electrically connected to the BMO metal line. The feedthrough via FTV 130 can then be electrically connected to other metal lines in the back-side multilayer interconnect structure BMLI. The M0 metal line and the BMO metal line may each include Vdd and / or Vss power lines electrically connected to the feedthrough via FTV 130. (See reference...) Figure 9B The through-conductive feature 150 in the memory edge regions 30a and 30b can be electrically connected to the M0 metal line, and then electrically connected to other metal lines in the front-side multilayer interconnect structure FMLI. In an embodiment, the through-conductive feature 150 is electrically connected to the BMO metal line. The through-conductive feature 150 can then be electrically connected to other metal lines in the back-side multilayer interconnect structure BMLI. By having the through-conductive feature 150, the additional conductive feature (e.g., the through-conductive feature 150) is connected in parallel to the power supply line, reducing the total resistance of the power supply feature (e.g., the metal line electrically connected to a voltage potential (such as Vdd or Vss) and the through-conductive feature 150). Therefore, during operation of the memory component 10A, the voltage drop and / or power consumption on the power supply feature is reduced. The voltage drop can be reduced by more than about 50 mV. By having the additional conductive feature for power supply, the memory component 10A can include an increased number of memory cells without affecting the performance of the memory cells.

[0074] Figure 10 Plotted in Figure 1 An exemplary layout of a portion of the alternative memory component 10B in region A within the DL layer, CO layer, and V0 layer. (Refer to...) Figure 10 ,and Figures 5 to 9B The difference in memory component 10A is that memory component 10B includes a source / drain contact rail VDR 152 disposed on and connected to the source / drain contact MD above the dummy oxide boundary region, instead of as... Figure 5A source / drain contact via VD 138 is disposed on the source / drain contact MD above the dummy oxide boundary region. The source / drain contact rail VDR 152 may comprise a material similar to the source / drain contact via VD 138 and may be formed using any suitable method, such as performing patterning and photolithography processes to form a trench through a portion of the dielectric structure 126, and then filling the trench with metallic features.

[0075] Figure 11 A cross-sectional view of a portion of memory component 10B along line BB is shown, as follows. Figure 10 As shown. In these embodiments, the back-side via BV0 142, the source / drain feature 106, the source / drain contact (MDover dummy OD) above the dummy oxide boundary region, and the source / drain contact rail VDR 152 together form a through-hole conductive feature 154. This through-hole conductive feature 154 electrically connects metal lines MO-1 and BMO-1. In some embodiments, this through-hole conductive feature 154 is further electrically connected to other front-side and / or back-side metal lines. By having the source / drain contact rail VDR 152, the total resistance of the power supply feature can be further reduced compared to the total resistance in the memory component 10A.

[0076] Figure 12 The diagram shows the replacement memory component 10C in... Figure 1 An exemplary layout 200 of a portion of region A includes a DL layer, a BVO layer, and a BMO layer. (As shown in the image) Figure 5-9B The difference between memory component 10A and memory component 10C is that memory component 10C does not include, for example, Figure 6 Instead of BV0 142, a back-side via 156 is provided below each discontinuous active region (e.g., active regions 104F and 104G) and connected to its source / drain region. The back-side via 156 may comprise a material similar to that of a BV0 via (e.g., BV0 140) and may be formed using any suitable method.

[0077] Figure 13 The diagram shows a cross-sectional view of a portion of memory component 10C along line BB, as shown. Figure 12 As shown. In these embodiments, the back-side via 156, source / drain feature 106, source / drain contact MD, and VD together form a through-hole conductive feature 158. The through-hole conductive feature 158 electrically connects metal line M0-1 and metal line BMO-1. In some embodiments, the through-hole conductive feature 158 is further electrically connected to other front-side and / or back-side metal lines. By having the back-side via 156, the total resistance of the power supply feature can be further reduced from the memory component 10A.

[0078] Figures 14 to 16 The diagram illustrates the alternative memory component 10D in, for example Figure 1 An exemplary layout of a portion of region A in the image, wherein Figure 14 The layout of the DL layer, CO layer, and V0 layer is shown. Figure 15 The layout of the DL layer, BV0 layer, BM0 layer, BV1 layer, and BM1 layer is shown. Figure 16 The layout is shown in the V0, M0, V1 and M1 layers.

[0079] Reference Figure 14 Memory component 10D and Figure 5 The difference in memory component 10A is that active regions 104F, 104G, and 104H are located on the same P-type well 122P as active regions 104E and 104D. Therefore, active regions 104F and 104G are N-type active regions, and their source / drain characteristics 106 are N-type source / drain characteristics. In some embodiments not depicted, the source / drain contact via VD 138 can be similar to... Figure 10 The VD track 152 in the middle is replaced by the VD track.

[0080] Reference Figure 15 ,and Figure 6 The memory component 10A differs in that the metal line BM0-1' is a Vss power line. Therefore, both metal lines BM0-1' and BM0-2 can be back-side Vss power lines and can be electrically connected via the BV1 via the metal line BM1-1. The connection between metal lines BM0-1' and BM0-2, such as the metal lines BM1 and the BV1 via, is for illustrative purposes only, and its location, size, and number should not be construed as limiting the scope of this invention. In some embodiments not depicted, the back-side via BV0 142 can be similar to... Figure 12 The back-side through-hole 156 is replaced by the back-side through-hole 130. The feedthrough FTV 130 can be electrically connected to the back-side Vdd power line or the back-side Vss power line (e.g., metal wires BM1-1, BM0-1', BM0-2, BM0-3 and BM0-4).

[0081] Reference Figure 16 The source / drain contact via VD 138 is electrically connected to the metal wire M0-1'. Figure 7Unlike memory component 10A, M0-1' is a Vss power line. Metal line M0-1' can be electrically connected to metal line M1-2 via a V1 via. In some embodiments, metal line M1-2 is a front-side Vss power line. In some embodiments, metal line M1-2 is connected to metal lines M0-4 and M0-5 via a V1 via. Metal lines M0-4 and M0-5 can also be referred to as Vss grounding pads. Similar to the through-hole conductive feature 150 in memory component 10A, the through-hole conductive features of memory component 10D in memory edge region 30, from top to bottom, include a source / drain contact via VD 138, a source / drain contact (MD over dummy OD) over the dummy oxide boundary region, a source / drain feature 106, and a back-side via BVO 142. Therefore, the through-conducting feature of memory component 10D is electrically connected to the front power line M0-1' and the rear power line BMO-1'. Arrow 162 illustrates an exemplary conductive path between the source / drain contact VD 138 and the source / drain contact via VD (also referred to as VD 166 for clarity and simplicity) below the Vss pads (e.g., metal lines M0-4 and M0-5). In some embodiments, metal line M0-1' is also electrically connected to other Vss ground pads (e.g., metal lines M0-6 and M0-7) via other M1 metal lines (e.g., metal line M1-3) and V1 vias. Metal lines M1-2 and M1-3 may both be Vss power lines. In some embodiments, memory component 10D includes metal lines above the M1 layer (e.g., M2 metal lines) to electrically connect metal lines M1-2 and other M1 metal lines. The connections between source / drain contacts VD 138 and source / drain contacts VD 166, such as metal wires M1-2, M1-3, and V1 vias, are for illustrative purposes only, and their positions, dimensions, and quantities should not be construed as limiting the scope of this invention. Feedthrough vias FTV130 can be electrically connected to the front-side Vdd power lines (e.g., metal wires M0-2, M0-3) or the front-side Vss power lines (e.g., metal wires M1-2, M1-3, M0-4, M0-5, M0-6, and M0-7).

[0082] Figure 17 The diagram illustrates the alternative memory component 10E in... Figure 1 An exemplary layout of portions of the device layer, CO layer, and V0 layer in region A. Figures 14 to 16The difference in the memory component 10D includes that, instead of the source / drain contact 172 of the memory component 10E for the circuit Vss node (also referred to as "Vss node source / drain contact MD") and the source / drain contact MD above the dummy oxide boundary region OD aligned with the Vss node MD, the extended source / drain contact 172 may extend continuously from discontinuous active regions 104 (e.g., active regions 104F and 104G) to active region 104D. In the example, the extended source / drain contact 172 extends continuously over active regions 104D, 104E, and 104F and is electrically connected to their source / drain features 106. In another example, extended source / drain contacts 172 extend continuously over active regions 104D, 104E, and 104G and are electrically connected to their source / drain features 106. Source / drain contacts VD 138 and / or source / drain contacts VD 166 may be disposed on the extended source / drain contacts 172. In some embodiments, such as Figure 16 As shown, source / drain contact VD 138 is electrically connected to metal line M0-1', and source / drain contact VD 166 is electrically connected to metal lines M0-4 and / or M0-6. In these embodiments, the extended source / drain contact 172 can reduce the total resistance of the Vss power supply characteristic. In some other embodiments, it can eliminate Figure 16 The metal wire M0-1' shown is connected to M0-4 / M0-6 via metal wires M1-2 / M1-3. In other words, the through-conductivity features of the memory component 10E may include source / drain features 106 of discontinuous active regions (e.g., active regions 104F and 104G) and a top-to-bottom back-side via BV0 142, and may be connected to Vss power lines (e.g., metal wires M0-4, M0-6, M1-2, and M1-3) via extended source / drain contacts 172.

[0083] Figure 18 As shown in the diagram Figure 1 The diagram shows an exemplary layout of the alternative memory component 10F in regions A, specifically the DL layer, CO layer, and V0 layer. (Refer to...) Figure 18 ,and Figure 17 Unlike memory component 10E, memory component 10F does not include source / drain contact via VD 138, but instead includes source / drain contact via rail VDR 176. Source / drain contact via rail VDR 176 can be similar to... Figure 10The source / drain contact via 152 is located in the middle. The source / drain contact via 176 electrically connects the source / drain contact (MD over dummy OD) above the dummy oxide boundary region and the extended source / drain contact 172 to the dummy oxide boundary region. Figure 16 The metal wire M0-1' in it.

[0084] Figure 19 The diagram illustrates a 10G alternative memory component in... Figure 1 An exemplary layout of portions of the DL layer, CO layer, and V0 layer in region A. (Refer to...) Figure 19 , and like Figures 5 to 9B The memory component 10A differs from the memory component 10G in that it includes a feedthrough via (FTV) rail 180 in the memory edge region 30, instead of a through-hole conductive feature 150. Another difference from the memory component 10A is that the memory component 10G includes a continuous active region 104K in the memory edge region 30, instead of discontinuous active regions 104F and 104G. In some embodiments, the feedthrough via (FTV) rail 180 is located between active regions 104K and 104E. The feedthrough via (FTV) rail 180 may also be disposed between active regions 104K and 104I. In some other embodiments, the active region 104K is eliminated. The feedthrough via (FTV) rail 180 may extend through the memory edge region 30 along the X-direction and perpendicularly through the device layer DL including the N-type well 122N. Therefore, the feedthrough via (FTV) rail 180 may be referred to as a through-hole conductive feature 180. In some embodiments, the memory component 10G includes a dielectric layer 182 on the sidewall of the feedthrough FTV rail 180. The dielectric layer 182 isolates the feedthrough FTV rail 180 from adjacent conductive features, such as the gate structure 110, source / drain features 106, and source / drain contacts MD. The feedthrough FTV rail 180 and the dielectric layer 182 may each comprise materials similar to those used for the feedthrough FTV 130 and the dielectric layer 132. The feedthrough FTV rail 180 and the dielectric layer 182 can be formed using any suitable method. In some embodiments, the method is similar to the method described above for forming the feedthrough FTV 130 and the dielectric layer 132.

[0085] The active region 104K can have a width of W7 in the Y direction. For example... Figure 5As shown, the width W7 can be smaller than the width W4. The distance S2 between active regions 104K and 104E can be greater than the distance S1. In some embodiments, the distance S2 is in the range of approximately 0.07 micrometers to approximately 0.15 micrometers. The dielectric layer 182 can be separated from the active regions 104E, 104I, or 104K by a distance S3. The distance S3 can be in the range of approximately 0 micrometers to approximately 0.03 micrometers. The feedthrough FTV rail 180 can have a width W8 in the Y direction, ranging from approximately 0.02 micrometers to approximately 0.05 micrometers. In some embodiments, the ratio of W8 to S2 is in the range of approximately 0.3 to approximately 1. In some embodiments, the ratio of W8 to W3 is in the range of approximately 1 to approximately 3. The gate structure 110 can have a width G1 in the X direction. In some embodiments, the ratio of width W8 to width G1 is between approximately 1 and approximately 6. If W8 is too small, the resistance of the FTV rail 180 may be too large, and therefore the advantages of the described structure may be too small. If the width W8 is too large, it may unnecessarily increase the footprint of the memory components by 10G and the associated costs.

[0086] Figure 20A draw Figure 19 A cross-sectional view of a portion of the memory component 10G along the EE line. The feedthrough FTV rail 180 may include one or more conductive features (e.g., conductive rails 184 and 186) connected together. Figure 7 The metal wire M0-1 is positioned above and connected to the conductive rail 186. Figure 6 The metal wire BM0-1 is positioned below and connected to the conductive rail 184.

[0087] Figure 20B The drawing is along Figure 1 A schematic side view of a portion of the 10G memory module on the DD line. For simplicity, the structure within the device layer of memory cell region 15 is not shown. Figure 20B The number of metal wires and metal through-holes, as well as the connections between them, are for illustrative purposes only and should not be construed as limiting the scope of this invention. Figure 9BThe difference between memory component 10A and memory component 10G is that memory component 10G includes a feedthrough FTV rail 184 connecting the M0 and BMO metal lines, instead of a through-hole conductive feature 150. The feedthrough FTV rail 184 can then be electrically connected to other metal lines in the front-side multilayer interconnect structure FMLI and the back-side multilayer interconnect structure BMLI. By replacing the through-hole conductive feature 150 with the feedthrough FTV rail 184, the total resistance of the power supply feature (e.g., the metal lines electrically connected to voltage potentials (such as Vdd or Vss) and the FTV rail 184) is further reduced compared to memory component 10A. Therefore, the voltage drop and / or power consumption on the power supply feature may be further reduced during operation of memory component 10G. The voltage drop may be reduced by more than about 150mV.

[0088] Figure 21 The drawing is as follows Figure 1 An exemplary layout of the replacement memory component 10H within region A in the DL layer, CO layer, and V0 layer. (Refer to...) Figure 21 ,and Figures 14 to 16 The memory component 10D differs in that the memory component 10H includes a feedthrough via (FTV) rail 180 in the memory edge region 30 instead of a through-hole conductive feature, and the memory component 10G includes a continuous active region 104K in the memory edge region 30 instead of discontinuous active regions 104F and 104G. The active regions 104D, 104E, 104K, and 104H of the memory component 10H are located above the same P-type well 122P. The feedthrough via (FTV) rail 180 can extend along the X-direction through the length direction of the memory edge region 30 and perpendicularly through the device layer DL including the same P-type well 122P. Similar to the through-hole conductive feature of the memory component 10D, the feedthrough via (FTV) rail 180 can be as follows: Figure 16 As shown, it is positioned below and electrically connected to the metal wire M0-1', and can be used as follows: Figure 15 The feedthrough FTV rail 180, dielectric layer 182, and continuous active region 104K, as shown, are positioned above and electrically connected to the metal line BM0-1'. Their relative positions and dimensions are similar to those of the memory component 10G described above.

[0089] Figure 22 The drawing is shown in Figure 1 An exemplary layout of a portion of the DL layer, CO layer, and V0 layer of the memory component 10I in region A. See reference... Figure 22 ,and Figure 21The difference in memory component 10H is that memory component 10I does not include the Vss node MD aligned with the Vss node MD and the Vss node MD, source / drain contact VD 166, and source / drain contact MD located above the active region 104K. Instead, it includes an extended source / drain contact 188 located above and electrically connected to the source / drain features 106 of the feedthrough FTV rail 190 and the active regions 104D, 104E, and 104K. In some other embodiments, the active region 104K is eliminated, and the extended source / drain contact 188 does not extend above the active region 104K. In some embodiments, the extended source / drain contact 188 is similar to... Figure 16 The metal wires M0-1', M0-4, and / or M0-6 shown are electrically connected; these are the front-side Vss power lines. Therefore, the extended source / drain contact 188 is the Vss contact. In these embodiments, extending the source / drain contact 188 can reduce the total resistance of the Vss power supply characteristics. In some other embodiments, such as Figure 16 The metal wire M0-1' shown, and the connection between metal wires M0-1' and M0-4 / M0-6 via metal wires M1-2 / M1-3, can be eliminated.

[0090] Figure 23A and Figure 23B Draw them respectively as follows Figure 22 The diagram shows a cross-sectional view of a portion of the memory assembly 10I along the EE and FF lines. In the illustrated embodiment, a feedthrough via (FTV) rail 184 is disposed below and connected to the extended source / drain contact 188. The feedthrough via (FTV) rail 184 and the extended source / drain contact 188 together form a through-type conductive feature 192, which is electrically connected to the metal lines MO-1' and BMO-1'. Figure 21 The differences in the feedthrough FTV rail 180 include that the height of the feedthrough FTV rail 184 along the Z-direction is less than that of the feedthrough FTV rail 180 along the Z-direction, and that the feedthrough FTV rail 184 does not directly contact the metal line M0-1'. As shown, the feedthrough FTV rail 184 can be spaced apart from the metal line M0-1' by the dielectric structure 126 and the extended source / drain contact 188. The feedthrough FTV rail 184 can be positioned above and in direct contact with the metal line M0-1'.

[0091] Figure 24 The drawing is as follows Figure 1 An exemplary layout of a portion of the alternative memory component 10J within region A in the DL layer, CO layer, and V0 layer. (Refer to...) Figure 24 ,and Figure 19 and Figures 20A to 20BThe difference in memory component 10G is that the alignment portions of the power tap region 25a and the memory edge region 30 and memory fill region 35 (e.g., in region G) are eliminated, thus reducing the total width of macro 12 by five poly pitches (PP). Region G is shown as a dashed rectangle and is aligned with the power tap region 25a along the Y direction. Similarly, the corresponding alignment portions of the power tap region 25b and the memory edge region 30 and memory fill region 35 can also be eliminated, thus reducing the total width of macro 12 by five PP. Therefore, the footprint of macro 12 of memory component 10J can be reduced by about 2% to about 30% compared to memory component 10G. In these embodiments, the power supply for the memory cells of memory cell region 15 can be provided by a feedthrough FTV rail 180', which extends through the memory edge region 30 and is similar to but shorter in the X direction than the feedthrough FTV rail 180. By having a feedthrough FTV rail 180' and eliminating the power tap region 25 and alignment portion, the total resistance of the power supply characteristics (e.g., the metal lines electrically connected to the voltage potential (e.g., Vdd or Vss) and the feedthrough FTV rail 180') can be reduced. Therefore, during operation of the memory component 10J, the voltage drop and / or power consumption on the power supply characteristics can be reduced. The voltage drop can be reduced by more than about 80mV.

[0092] Figure 25 The diagram shows a 10K replacement memory component in... Figure 1 An exemplary layout of portions of the DL layer, CO layer, and V0 layer in region A. (See reference...) Figure 25 ,and Figure 21 The difference in the memory component 10H is that the alignment portions of the power tap region 25a and the memory edge region 30 and memory fill region 35 (e.g., in region G) are eliminated, thus reducing the total width of the macro 12 by five polysilicon pitches (PPs). Region G is shown as a dashed rectangle and is aligned with the power tap region 25a along the Y direction. Similarly, the corresponding alignment portions of the power tap region 25b and the memory edge region 30 and memory fill region 35 can also be eliminated, thus reducing the total width of the macro 12 by five polysilicon pitches (PPs). Therefore, the footprint of the macro 12 of the memory component 10K is reduced by approximately 2% to approximately 30% compared to the footprint of the memory component 10H. In these embodiments, the power supply for the memory cells of the memory cell region 15 can be provided by a feedthrough FTV rail 180', which extends through the memory edge region 30 and is similar to but shorter in the X direction than the feedthrough FTV rail 180. As described above for... Figure 24 The voltage drop can be reduced by more than 80mV.

[0093] Figure 26 It schematically illustrates that in Figure 1 In region A, an exemplary layout of a portion of the alternative memory component 10L in the DL layer, CO layer, and V0 layer. (Refer to...) Figure 26 ,and Figures 22 to 23B The difference in the memory component 10I is that the power tap region 25a and the aligned portions of the memory edge region 30 and memory fill region 35 (e.g., in region G) are eliminated, thus reducing the total width of the macro 12 by five polysilicon pitches (PPs). Region G is shown by a dashed rectangle and is aligned with the power tap region 25a along the Y direction. Similarly, the power tap region 25b and the corresponding aligned portions of the memory edge region 30 and memory fill region 35 can also be eliminated, thus reducing the total width of the macro 12 by five polysilicon pitches (PPs). Therefore, the footprint of the macro 12 of the memory component 10L is reduced by approximately 2% to approximately 30% compared to the footprint of the memory component 10I. In such an embodiment, the power supply for the memory cells of the memory cell region 15 can be provided by a feedthrough FTV rail 190', which extends through the memory edge region 30 and is similar to but shorter in the X direction than the feedthrough FTV rail 190. As described above for... Figures 24 to 25 The voltage drop can be reduced by more than approximately 80mV.

[0094] Although not depicted, it is understood that the aforementioned memory components 10A, 10B, ..., and 10F can similarly eliminate the corresponding alignment portions of the power tap region 25, the memory edge region 30, and the memory fill region 35 (e.g., in region G), thus reducing the footprint of the macro 12 of the memory component 10.

[0095] Please understand that the description of the memory component 10 in region A above can be applied similarly to the memory component 10 in region A'. Region A and region A' are relative to... Figure 1 The mirror axis HH in the image is symmetrical, and this mirror axis is the central line of macro 12. Therefore, a portion of region A' includes a portion of memory edge region 30b. The portions of memory component 10 in region A and in region A' can have combinations of the various embodiments described above. In some embodiments, memory edge regions 30a and 30b can include the same or different through-conductivity features described above and can be connected to power lines having the same or different potentials. In the example, memory component 10 can have similar characteristics to... Figures 5 to 8 A portion of region A, and similar to Figures 14 to 16 The portion within region A'. In another example, the portions of memory component 10 in both regions A and A' are similar. Figures 5 to 8In yet another example, the portion of memory component 10 in region A is similar to the embodiments described above, for example, similar to... Figures 5 to 8 The portion of memory component 10 in region A' does not include the aforementioned penetrating conductive features.

[0096] Based on the foregoing discussion, it is evident that the present invention offers advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages are necessarily described herein, and not all embodiments require any particular advantage. For example, the present invention provides a memory component with additional and / or improved through-conductivity features for power supply, which reduces the total resistance of the power supply features, thereby reducing voltage drop and / or power consumption. Furthermore, by eliminating specific regions, the area of ​​a memory macro having a specific number of memory cells can be reduced by approximately 2% to approximately 30%. By having additional and / or improved through-conductivity features for power supply, the memory component disclosed herein can include an increased number of memory cells without affecting the performance of the memory cells.

[0097] In one exemplary aspect, the present invention relates to a semiconductor device comprising a device layer, a front interconnect structure disposed above the device layer and including a front power line, and a back interconnect structure disposed below the device layer and including a back power line. The device layer includes a memory cell region comprising a plurality of memory cells, a logic region disposed adjacent to a first edge of the memory cell region, and an edge region disposed along a second edge of the memory cell region. The second edge is perpendicular to the first edge. The edge region includes a through-hole conductive feature electrically connected to the front power line and the back power line. The through-hole conductive feature includes a back via electrically connected to the back power line, an epitaxial feature disposed on the back via, a source / drain contact disposed on the epitaxial feature, and a top via disposed on the source / drain contact and electrically connected to the front power line.

[0098] In some embodiments, the front power line and the rear power line are positive power supply lines. In some embodiments, the front power line and the rear power line are ground lines. In some embodiments, the epitaxial feature is a first epitaxial feature, and the rear via is a first rear via; the plurality of memory cells include a second epitaxial feature electrically connected to the rear power line via a second rear via and a rear metal line; the source / drain contact extends over and directly contacts the second epitaxial feature. In some embodiments, the edge region is a first edge region, the through-conductive feature is a first through-conductive feature, the front power line is a first front power line, and the rear power line is a first rear power line; the device layer further includes a second edge region disposed along a third edge of the memory cell region, the third edge being opposite to the second edge; the front interconnect structure further includes a second front power line; the rear interconnect structure further includes a second rear power line; the second edge region includes a second through-conductive feature electrically connected to the second front power line and the second rear power line. In some embodiments, the first front power line and the first rear power line are positive power supply lines; the second front power line and the second rear power line are ground lines. In some embodiments, the first front power line, the first rear power line, the second front power line, and the second rear power line are electrically connected to the same potential. In some embodiments, the epitaxial feature is a first epitaxial feature of an active region, the active region further including a second epitaxial feature, and the rear via directly contacts the bottom surface of the second epitaxial feature. In some embodiments, the through-conductive feature is a first through-conductive feature; the device layer further includes a power tap region disposed between the first edge of the logic region and the memory cell region; the power tap region includes a second through-conductive feature electrically connected to the front power line and the rear power line.

[0099] In another exemplary aspect, the present invention relates to a semiconductor device, the semiconductor device comprising a device layer, a front interconnect structure disposed above the device layer and including a first front power line and a second front power line, and a back interconnect structure disposed below the device layer and including a first back power line and a second back power line. The device layer includes a memory cell region comprising a plurality of functional memory cells, a power tap region disposed beside and along a first edge of the memory cell region, a logic region disposed between the logic region and the memory cell region beside the power tap region, and an edge region not containing functional memory cells and disposed along a second edge of the memory cell region perpendicular to the first edge. The edge region includes a first through-conducting feature electrically connected to the first front power line and the first back power line. The power tap region includes a second through-conducting feature electrically connected to the second front power line and the second back power line.

[0100] In some embodiments, the first through-conductive feature includes a back-side via electrically connected to the first back-side power line, an epitaxial feature disposed on the back-side via, a source / drain contact disposed on the epitaxial feature, and a top via disposed on the source / drain contact and electrically connected to the first front-side power line. In some embodiments, the edge region further includes a third through-conductive feature electrically connected to the first front-side power line and the first back-side power line; the first through-conductive feature and the third through-conductive feature are arranged along a direction parallel to the second edge of the memory cell region. In some embodiments, the first through-conductive feature includes: a back-side contact electrically connected to the first back-side power line; and a front-side contact disposed above the back-side contact and electrically connected to the first front-side power line. In some embodiments, the first front-side power line, the first back-side power line, the second front-side power line, and the second back-side power line are positive power supply lines. In some embodiments, the first front-side power line, the first back-side power line, the second front-side power line, and the second back-side power line are ground lines. In some embodiments, the plurality of functional memory cells include an active region having an epitaxial feature; wherein the plurality of functional memory cells include a conductive contact connecting the first through-type conductive feature and the epitaxial feature, and wherein the length direction of the conductive contact is perpendicular to the length direction of the active region.

[0101] In another embodiment, the present invention relates to a semiconductor device, the semiconductor device including a device layer, a front power line disposed above the device layer, and a back power line disposed below the device layer. The device layer includes a memory cell region comprising a plurality of memory cells, wherein the plurality of memory cells includes a first active region extending along a first direction; a logic region disposed adjacent to the memory cell region and extending along a second direction perpendicular to the first direction; and an edge region disposed adjacent to the memory cell region and extending along the first direction. The edge region includes a second active region extending along the first direction. The edge region includes a through-conductive feature electrically connected to the front power line and the back power line. The second active region is disposed between the through-conductive feature and the first active region.

[0102] In some embodiments, the penetrating conductive feature extends along the length direction of the first direction. In some embodiments, the edge region includes a third active region extending along the length direction of the first direction, and the penetrating conductive feature extends through the third active region. In some embodiments, the first active region, the second active region, and the third active region are disposed above the same p-type well.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Device layer, including: The memory cell region includes multiple memory cells. A logical region is located next to the first edge of the memory cell region, and An edge region is provided along the second edge of the memory cell region, wherein the second edge is perpendicular to the first edge; A front interconnect structure is disposed above the device layer and includes front power lines; and A back-side interconnect structure is disposed below the device layer and includes back-side power lines. The edge region includes a penetrating conductive feature electrically connected to the front power line and the rear power line. The through-type conductive feature includes a back-side via electrically connected to the back-side power line, an epitaxial feature disposed on the back-side via, a source / drain contact disposed on the epitaxial feature, and a top via disposed on the source / drain contact and electrically connected to the front-side power line.

2. The semiconductor device according to claim 1, characterized in that, The edge region is a first edge region, the penetrating conductive feature is a first penetrating conductive feature, the front power line is a first front power line, and the back power line is a first back power line. The device layer further includes a second edge region disposed along the third edge of the memory cell region, the third edge being opposite to the second edge. The front interconnect structure further includes a second front power line. The back-side interconnect structure further includes a second back-side power line, and The second edge region includes a second penetrating conductive feature electrically connected to the second front power line and the second back power line.

3. The semiconductor device according to claim 1, characterized in that, The penetrating conductive feature mentioned above is the first penetrating conductive feature. The device layer further includes a power tap region disposed between the first edge of the logic region and the memory cell region, and The power tap area includes a second penetrating conductive feature electrically connected to the front power line and the back power line.

4. A semiconductor device, characterized in that, include: Device layer, including: The memory unit area includes multiple functional memory units. A power tap area is located next to and along the first edge of the memory cell area. A logic region is located adjacent to the power tap region, wherein the power tap region is located between the logic region and the memory cell region. An edge region, which does not contain functional memory cells and is disposed along a second edge of the memory cell region, wherein the second edge is perpendicular to the first edge; A front interconnect structure is disposed above the device layer and includes a first front power line and a second front power line; and The back-side interconnect structure is disposed below the device layer and includes a first back-side power line and a second back-side power line. The edge region includes a first penetrating conductive feature electrically connected to the first front power line and the first back power line, and The power tap area includes a second penetrating conductive feature, which is electrically connected to the second front power line and the second back power line.

5. The semiconductor device according to claim 4, characterized in that, The first penetrating conductive feature includes a back-side through-hole electrically connected to the first back-side power line, an epitaxial feature disposed on the back-side through-hole, a source / drain contact disposed on the epitaxial feature, and a top through-hole disposed on the source / drain contact and electrically connected to the first front-side power line.

6. The semiconductor device according to claim 5, characterized in that, The edge region further includes a third penetrating conductive feature electrically connected to the first front power line and the first rear power line. The first penetrating conductive feature and the third penetrating conductive feature are arranged along a direction parallel to the second edge of the memory cell region.

7. The semiconductor device according to claim 4, characterized in that, The first penetrating conductive feature includes: The back-side contact is electrically connected to the first back-side power line, and A front contact is disposed above the rear contact and electrically connected to the first front power line.

8. A semiconductor device, characterized in that, include: Device layer, including: The memory cell region includes a plurality of memory cells, wherein the plurality of memory cells includes a first active region extending along a first length direction. A logical region is disposed adjacent to the memory cell region and extends along a second direction perpendicular to the first direction. An edge region is disposed next to the memory cell region and extends along the length direction of the first direction, wherein the edge region includes a second active region extending along the length direction of the first direction; The front power line is positioned above the device layer; and The back power line is located below the device layer. The edge region includes a penetrating conductive feature electrically connected to the front power line and the rear power line, and The second active region is disposed between the penetrating conductive feature and the first active region.

9. The semiconductor device according to claim 8, characterized in that, The edge region includes a third active region extending along the length direction of the first direction, and The penetrating conductive feature extends through the third active region.

10. The semiconductor device according to claim 9, characterized in that, The first active region, the second active region, and the third active region are located above the same p-shaped well.

Images