A high-efficiency thermally managed planar gate silicon carbide VDMOS
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2026-08-11
AI Technical Summary
[0002]碳化硅VDMOS器件由于其宽禁带特性和高导热的特性，其热管理的风险更低，但是主流栅极金属为铝材料，栅极金属用合金热导率一般为180–190W/(m·K)，与掺杂碳化硅材料(120–270W/(m·K))相近，因此，栅极金属对碳化硅VDMOS器件的热管理作用有限
[0015]一、本实用新型构建了与N型源区接触的肖特基金属层，实现了N型源区在顶部和横向两个方向的金属接触，可以有效降低器件的源极欧姆接触电阻，降低器件的导通电阻，降低了器件的热源，肖特基金属层在器件内部与漂移层、第一P型源区和第二P型源区直接接触，减少了器件源极金属层到体二极管的导通阻抗，降低了器件的热源；
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Figure CN224627073U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a high-efficiency thermally managed planar gate silicon carbide VDMOS. Background Technology
[0002] Silicon carbide VDMOS devices have lower thermal management risks due to their wide bandgap and high thermal conductivity. However, the mainstream gate metal is aluminum, and the thermal conductivity of the gate metal alloy is generally 180–190 W / (m·K), which is similar to that of doped silicon carbide (120–270 W / (m·K)). Therefore, the gate metal has a limited effect on the thermal management of silicon carbide VDMOS devices. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a high-efficiency thermal management planar gate silicon carbide VDMOS. The design of Schottky metal in lateral contact with the N-type source region reduces the source contact resistance of the device, reduces heat generation, and improves the thermal management capability of the device.
[0004] This invention provides a high-efficiency thermally managed planar gate silicon carbide VDMOS, comprising:
[0005] silicon carbide substrate,
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, a protrusion on the drift layer, and a gate protection zone within the protrusion; a first P-type source region and a second P-type source region are provided on the drift layer, the second P-type source region being located inside the first P-type source region;
[0007] A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, the upper side of the first P-type source region, and the second P-type source region;
[0008] The N-type source region has its lower side connected to the upper side of the second P-type source region, and its outer side connected to the inner side of the Schottky metal layer.
[0009] The lower side of the P-type well region is connected to the upper side of the second P-type source region, the outer side of the P-type well region is connected to the N-type source region, and the inner side of the P-type well region is connected to the outer side of the protrusion.
[0010] An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to a P-type well region, a protrusion, and a gate protection region;
[0011] A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer;
[0012] A source metal layer, wherein the source metal layer is connected to the Schottky metal layer and the N-type source region respectively;
[0013] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0014] The advantages of this utility model are:
[0015] I. This utility model constructs a Schottky metal layer in contact with the N-type source region, realizing metal contact between the N-type source region in both the top and lateral directions. This can effectively reduce the source ohmic contact resistance of the device, reduce the on-resistance of the device, and reduce the heat source of the device. The Schottky metal layer is in direct contact with the drift layer, the first P-type source region, and the second P-type source region inside the device, reducing the on-resistance from the source metal layer to the body diode and reducing the heat source of the device.
[0016] 2. The Schottky metal layer in contact with the N-type source region in this utility model constructs a low thermal resistance path from the device body to the source metal layer. The parasitic diodes of the device can dissipate heat through the low thermal resistance channel of the Schottky metal layer, which increases the metal contact area between the N-type source region and the device surface, reduces the source thermal resistance of the device, and thus improves the thermal management capability of the device.
[0017] Third, this utility model constructs a composite diode structure in the body diode region of the device, with a Schottky metal layer on top and a first P-type source region, a second P-type source region, and a drift region distributed side by side at the bottom of the Schottky metal layer. This reduces the freewheeling loss while ensuring the freewheeling capability of the device body diode. When the drain is subjected to a large voltage, the drift layer will form a space charge region with the first P-type source region and the second P-type source region, which can improve the voltage withstand capability of the parasitic Schottky diode. Attached Figure Description
[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0019] Figure 1 This is a schematic diagram of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model.
[0020] Figure 2 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 1 .
[0021] Figure 3 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 2 .
[0022] Figure 4 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 3 .
[0023] Figure 5This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 4 .
[0024] Figure 6 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 5 .
[0025] Figure 7 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 6 .
[0026] Figure 8 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 7 .
[0027] Figure 9 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 8 .
[0028] Figure 10 This is a cross-sectional view of the process of a high-efficiency thermally managed planar gate silicon carbide VDMOS according to this utility model. Figure 9 . Detailed Implementation
[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0034] like Figure 1 As shown, this application embodiment provides a high-efficiency thermally managed planar gate silicon carbide VDMOS, including:
[0035] Silicon carbide substrate 1,
[0036] A drift layer 2 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 1. A protrusion 21 is provided on the drift layer 2, and a gate protection zone 211 is provided in the protrusion 21. A first P-type source region 22 and a second P-type source region 23 are provided on the drift layer 2, and the second P-type source region 23 is located inside the first P-type source region 22.
[0037] Schottky metal layer 3, the lower side of which is connected to the upper side of drift layer 2, the upper side of first P-type source region 22 and second P-type source region 23;
[0038] N-type source region 4, the lower side of the N-type source region 4 is connected to the upper side of the second P-type source region 23, and the outer side of the N-type source region 4 is connected to the inner side of the Schottky metal layer 3;
[0039] P-type well region 5, the lower side of the P-type well region 5 is connected to the upper side of the second P-type source region 23, the outer side of the P-type well region 5 is connected to the N-type source region 4, and the inner side of the P-type well region 5 is connected to the outer side of the protrusion 21.
[0040] An insulating dielectric layer 6, the lower side of which is connected to a P-type well region 5, a protrusion 21 and a gate protection zone 211 respectively;
[0041] A gate metal layer 7, the lower side of which is connected to the upper side of the insulating dielectric layer 6;
[0042] Source metal layer 8, which is connected to the Schottky metal layer 3 and the N-type source region 4 respectively;
[0043] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.
[0044] In this embodiment, preferably, the Schottky metal layer 3, the N-type source region 4, the P-type well region 5, and the gate protection region 211 have equal thicknesses.
[0045] In this embodiment, preferably, the width of the first P-type source region 22 is smaller than the width of the second P-type source region 23.
[0046] In this embodiment, preferably, the doping concentration of the P-type well region 5 is less than the doping concentration of the drift layer 2.
[0047] In this embodiment, preferably, the doping concentration of the P-type well region 5 is less than the doping concentration of the N-type source region 4; and the doping concentration of the P-type well region 5 is less than the doping concentration of the second P-type source region 23.
[0048] In this embodiment, preferably, the silicon carbide substrate 1 and the drift layer 2 are both N-type, and the gate protection zone 211 is P-type.
[0049] like Figures 1 to 10 As shown, the fabrication method of the above-mentioned planar gate silicon carbide VDMOS includes the following steps:
[0050] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9; epitaxially grow on the upper side of silicon carbide substrate 1 to form drift layer 2;
[0051] Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer 100 to form a via, and implant ions to form a first P-type source region 22 and a second P-type source region 23, respectively.
[0052] Step 3: Remove the barrier layer 100 from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and perform ion implantation to form a P-type well region 5 and a gate protection region 211, respectively.
[0053] Step 4: Remove the barrier layer 100 from Step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form the N-type source region 4.
[0054] Step 5: Remove the barrier layer 100 from step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, etch the drift layer 2 to the upper side of the first P-type source region 22, deposit metal, and form a Schottky metal layer 3.
[0055] Step 6: Remove the barrier layer 100 from step 5, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form the insulating dielectric layer 6.
[0056] Step 7: Remove the barrier layer 100 from step 6, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal, and form the gate metal layer 7.
[0057] Step 8: Remove the barrier layer 100 from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit metal to form the source metal layer 8, remove the barrier layer 100, and complete the fabrication.
[0058] In another embodiment of this invention, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of drift layer 2 is 1-8e17cm. -3 The doping concentration of P-type well region 5 is 1-5e15cm. -3 The doping concentration of both the first P-type source region 22 and the second P-type source region 23 is 5-9e18cm. -3 The insulating dielectric layer 6 can be made of silicon dioxide, and the doping concentration of the N-type source region 4 is 2-8e18cm. -3The Schottky metal layer 3 is made of the same material as the source metal layer 8, which is nano-silver with a thermal conductivity of 429 W / (m·K). When embedded into the device structure, it can improve the thermal conductivity from the inside of the device to the source metal, improve the thermal management capability of the device, improve the thermal conductivity of the device source, and form a stronger contact with the bonding wire during device packaging, thus forming thermal conductivity from the device pad to the device packaging structure.
[0059] The doping concentration of the silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 9, thereby reducing the overall on-resistance of the device. The doping concentration of the drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. Due to the doping concentration of the first P-type source region 22 and the second P-type source region 23, as well as the structural distribution of the Schottky metal layer 3, the doping concentration of the drift layer 2 can be increased while ensuring the breakdown voltage of the device.
[0060] The doping concentration design of the first P-type source region 22 and the second P-type source region 23 has two considerations: First, it is to reduce the contact resistance between the first P-type source region 22 and the second P-type source region 23 and the Schottky metal layer 3, thereby reducing the conduction loss of the parasitic pn junction body diode of the device; Second, it is to reduce the diffusion rate of the space charge region located in the first P-type source region 22 and the second P-type source region 23 to the device gate and source when the drain voltage is high; The doping concentration of the P-type well region 5 is to reduce the gate control charge of the device gate and improve the switching speed of the device;
[0061] The silicon carbide substrate 1 of the device has a thickness of 1 μm, and the drift layer 2 has a thickness of 50-80 μm, which is adjusted within the above range according to different requirements for the device's breakdown voltage characteristics. The thickness of the first P-type source region 22 and the second P-type source region 23 is 300 nm, and the thickness of the Schottky metal layer 3, N-type source region 4, P-type well region 5, and gate protection region 211 is 600 nm. This is to increase the longitudinal contact area between the Schottky metal layer 3 and the N-type source region 4, thereby reducing the ohmic contact resistance between the N-type source region 4 and the source metal layer 8, and reducing the device's voltage drop. The on-resistance is increased, and the contact area between the internal structure of the device and the high thermal conductivity metal is improved, thereby enhancing thermal management efficiency. The thickness of the gate protection zone 211 is equal to the thickness and doping concentration of the P-type well region 5, so that the P-type well region 5 and the gate protection zone 211 can be fabricated in one step, reducing process steps and lowering device manufacturing costs. The Schottky metal layer 3 and the drift layer 2 form a Schottky junction, but the Schottky metal layer 3 and the N-type source region 4 form an ohmic contact. The thickness of the insulating dielectric layer 6 is 50nm, which ensures the switching characteristics of the device and controls the gate charge.
[0062] The width of the first P-type source region 22 is 1 μm, the width of the drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is 500 nm, the width of the second P-type source region is 2 μm, the width of the Schottky metal layer 3 is 2 μm, and the width of the N-type source region 4 is 1 μm. This design is to form an ohmic contact above the second P-type source region 23 by the Schottky metal layer 3, avoiding the formation of an ohmic conductive channel from the N-type source region 4 to the drift layer 2. The drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is to construct a Schottky diode and at the same time form a space charge region when the device is reverse-biased, ensuring the breakdown voltage characteristics of the device.
[0063] The width of the P-type well region 5 is 500 nm, the width of the insulating dielectric layer 6 is 4 μm, the width of the gate metal layer 7 is 3 μm, and the width of the gate protection zone 211 is 1 μm. This is to improve the gate reliability of the device, shield the gate leakage capacitance, and improve the switching speed of the device. The distance from the P-type well region 5 to the gate protection zone 211 is 500 nm. This is to ensure that the conductive path of the device is not affected while improving the gate reliability of the device.
[0064] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A high efficiency thermal management planar gate silicon carbide VDMOS, characterized by: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, a protrusion on the drift layer, and a gate protection zone within the protrusion; a first P-type source region and a second P-type source region are provided on the drift layer, the second P-type source region being located inside the first P-type source region; A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, the upper side of the first P-type source region, and the second P-type source region; The N-type source region has its lower side connected to the upper side of the second P-type source region, and its outer side connected to the inner side of the Schottky metal layer. The lower side of the P-type well region is connected to the upper side of the second P-type source region, the outer side of the P-type well region is connected to the N-type source region, and the inner side of the P-type well region is connected to the outer side of the protrusion. An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to a P-type well region, a protrusion, and a gate protection region; A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer; A source metal layer, wherein the source metal layer is connected to the Schottky metal layer and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. A high efficiency thermal management planar gated silicon carbide VDMOS as claimed in claim 1, wherein: The Schottky metal layer, N-type source region, P-type well region, and gate protection region are all of equal thickness.
3. A high efficiency thermal management planar gated silicon carbide VDMOS as claimed in claim 1, wherein: The width of the first P-type source region is smaller than the width of the second P-type source region.
4. The high-efficiency thermally managed planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than that of the drift layer.
5. The high-efficiency thermally managed planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than that of the N-type source region; the doping concentration of the P-type well region is less than that of the second P-type source region.
6. The high-efficiency thermally managed planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate and the drift layer are both N-type, and the gate protection zone is P-type.