High-uis-resistance low-resistance planar gate silicon carbide vdmos
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2026-08-11
AI Technical Summary
[0002]碳化硅VDMOS器件由于其宽禁带特性，相比SiVDMOS器件天然具备低栅电荷、高开关速度的特点，在高压(1000V以上)大电流(100A以上)应用条件下，单个碳化硅VDMOS器件不能满足应用需求，需要进行多个器件并联应用，在并联应用器件关断的过程中，由于器件分布不可能完全堆成，会出现电流向某一个器件冲击，烧毁器件；因此，对器件的UIS特性要求更高
[0018] I. This utility model constructs a source protection zone that is short-circuited to the source metal layer, thereby ensuring that the parasitic NPN transistors in the N-type source region-P-type well region-source protection zone-first drift layer (shunt region) are in the off state when the device is short-circuited, and will not cause the current to double when the device is short-circuited, thereby improving the device's anti-UIS characteristics.
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Figure CN224627074U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Background Technology
[0002] Due to their wide bandgap characteristics, silicon carbide VDMOS devices inherently possess lower gate charge and higher switching speeds compared to SiVDMOS devices. However, in high-voltage (above 1000V) and high-current (above 100A) applications, a single silicon carbide VDMOS device cannot meet the requirements, necessitating the parallel connection of multiple devices. During the turn-off process of these parallel devices, the device distribution cannot be perfectly aligned, leading to current surges to certain devices and potential burnout. Therefore, higher requirements are placed on the device's UIS (Unified Inlet / Outlet) characteristics. Currently, there are two thermal mechanisms analyzed for short-circuit burnout: one is the significant thermal burnout caused by the high electric field and large current in the JFET region; the other is the thermal burnout caused by the conduction of parasitic NPN transistors inside the device, resulting in current multiplication and significant heat generation. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a low-resistance planar gate silicon carbide VDMOS with high UIS resistance, which reduces the resistance of the JFET region, avoids a large amount of heat generation, improves the UIS resistance and reduces the on-resistance of the device; and ensures that the parasitic NPN transistor inside the device is always turned off, so that there is no current multiplication effect, thereby improving the UIS resistance of the device.
[0004] This invention provides a low-resistance planar gate silicon carbide VDMOS with high UIS resistance, comprising:
[0005] silicon carbide substrate,
[0006] A first drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a groove is provided on the first drift layer;
[0007] A source polar protection zone, wherein the lower side of the source polar protection zone is connected to the upper side of the first drift layer;
[0008] A P-type well region is provided, the lower side of which is connected to the upper side of the source protection zone. An N-type source region and a P-type source region are provided on the P-type well region. The inner side of the P-type source region is connected to the outer side of the N-type source region, and the inner side of the N-type source region is connected to the P-type well region.
[0009] The shunt region is located in the groove at its lower part, and the outer side of the shunt region is connected to the inner side of the source protection zone and the inner side of the P-type trap region.
[0010] A low-resistance region, the lower part of which is disposed in the groove, and the outer side of which is connected to the inner side of the diversion region;
[0011] A gate protection zone, wherein the lower side of the gate protection zone is connected to the upper side of the low resistance region;
[0012] The second drift layer has its lower side connected to the upper side of the shunt region; the outer side of the second drift layer is connected to the inner side of the P-type well region; and the inner side of the second drift layer is connected to the outer side of the gate protection zone.
[0013] An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to a P-type well region, a second drift layer and a gate protection zone;
[0014] A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer;
[0015] A source metal layer is provided, which is connected to the P-type source region and the N-type source region respectively; the source metal layer is short-circuited to the source protection zone.
[0016] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0017] The advantages of this utility model are:
[0018] I. This utility model constructs a source protection zone that is short-circuited to the source metal layer, thereby ensuring that the parasitic NPN transistors in the N-type source region-P-type well region-source protection zone-first drift layer (shunt region) are in the off state when the device is short-circuited, and will not cause the current to double when the device is short-circuited, thereby improving the device's anti-UIS characteristics.
[0019] II. This utility model constructs a low-resistance region and a shunt region directly below the gate metal layer. When the device is short-circuited, a low-resistance JFET region is formed. The space charge region formed by the source protection zone and the P-type well region will not cause the JFET region to become a high-resistance space charge region. This avoids the generation of a large amount of heat in the JFET region by large voltage and current, thereby improving the device's UIS resistance characteristics.
[0020] Third, the low-resistance region and shunt region of this utility model construct a low-resistance conductive channel in the JFET region of the device, which can effectively reduce the on-resistance of the device and achieve low on-resistance.
[0021] Fourth, this utility model constructs a gate protection zone, which can alleviate the electric field at the bottom of the planar gate and effectively shield the gate leakage capacitance, thereby improving the reliability of the device. Attached Figure Description
[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0023] Figure 1This is a schematic diagram of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance.
[0024] Figure 2 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 1 .
[0025] Figure 3 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 2 .
[0026] Figure 4 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 3 .
[0027] Figure 5 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 4 .
[0028] Figure 6 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 5 .
[0029] Figure 7 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 6 .
[0030] Figure 8 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 7 .
[0031] Figure 9 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 8 .
[0032] Figure 10 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 9 .
[0033] Figure 11 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 10 .
[0034] Figure 12 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide VDMOS with high UIS resistance. Figure 10 one. Detailed Implementation
[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0040] like Figure 1 As shown, a low-resistance planar gate silicon carbide VDMOS with high UIS resistance includes:
[0041] Silicon carbide substrate 101,
[0042] A first drift layer 102 is provided, the lower side of the first drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and the first drift layer 102 is provided with a groove (not shown in the figure);
[0043] Source protection zone 103, the lower side of which is connected to the upper side of the first drift layer 102;
[0044] P-type well region 104, the lower side of which is connected to the upper side of the source protection zone 103, N-type source region 1041 and P-type source region 1042 are provided on the P-type well region 104, the inner side of the P-type source region 1042 is connected to the outer side of the N-type source region 1041, and the inner side of the N-type source region 1041 is connected to the P-type well region 104;
[0045] The shunt region 105 is located in the groove at its lower part, and the outer side of the shunt region 105 is connected to the inner side of the source protection zone 103 and the inner side of the P-type trap region 104.
[0046] Low resistance region 106, the lower part of which is disposed in the groove, and the outer side of the low resistance region 106 is connected to the inner side of the diversion region 105;
[0047] Gate protection zone 107, the lower side of which is connected to the upper side of low resistance region 106;
[0048] The second drift layer 108 has its lower side connected to the upper side of the shunt region 105; the outer side of the second drift layer 108 is connected to the inner side of the P-type well region 104; and the inner side of the second drift layer 108 is connected to the outer side of the gate protection zone 107.
[0049] An insulating dielectric layer 109, the lower side of which is connected to a P-type well region 104, a second drift layer 108 and a gate protection zone 107 respectively;
[0050] A gate metal layer 110, the lower side of which is connected to the upper side of the insulating dielectric layer 109;
[0051] A source metal layer 111 is provided, which is connected to the P-type source region 1042 and the N-type source region 1041 respectively; the source metal layer 111 is short-circuited to the source protection zone 103.
[0052] And a drain metal layer 112, which is connected to the lower side of the silicon carbide substrate 101.
[0053] In this embodiment, preferably, the lower side of the low-resistance region 106 is lower than the lower side of the shunt region 105; the upper side of the low-resistance region 106 and the upper side of the shunt region 105 are located on the same plane.
[0054] In this embodiment, preferably, the width of the P-type source region 1042 is greater than the width of the N-type source region 1041; and the thickness of the P-type source region 1042 is equal to the thickness of the N-type source region 1041.
[0055] In this embodiment, preferably, the doping concentration of the low-resistivity region 106 is less than the doping concentration of the shunt region 105.
[0056] In this embodiment, preferably, the doping concentration of the low-resistivity region 106 is less than the doping concentration of the gate protection region 107.
[0057] In this embodiment, preferably, the doping concentrations of the first drift layer 102 and the second drift layer 108 are equal, and the doping concentration of the low-resistivity region 106 is greater than the doping concentration of the first drift layer 102.
[0058] In this embodiment, preferably, the doping concentration of the source protection zone 103 is greater than the doping concentration of the P-type well region 104, the doping concentration of the shunt region 105, and the doping concentration of the first drift layer 102.
[0059] In this embodiment, preferably, the silicon carbide substrate 101, the first drift layer 102, the second drift layer 108, the low-resistivity region 106, and the shunt region 105 are all N-type; the source protection zone 103 and the gate protection zone 107 are both P-type.
[0060] like Figures 1 to 12 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0061] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 112; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift region 100;
[0062] Step 2: Form a barrier layer 200 above the drift region 100, etch the barrier layer 200 to form a via, and implant ions to form a low-resistivity region 106.
[0063] Step 3: Remove the barrier layer 200 from Step 2, reform the barrier layer 200, etch the barrier layer 200 to form a via, and implant ions to form the shunt region 105.
[0064] Step 4: Remove the barrier layer 200 from Step 3, reform the barrier layer 200, etch the barrier layer 200 to form a via, perform ion implantation to form the source protection zone 103, and divide the drift region 100 into a first drift layer 102 and a second drift layer 108.
[0065] Step 5: Remove the barrier layer 200 from step 4, reform the barrier layer 200, etch the barrier layer 200 to form a via, and implant ions to form a P-type well region 104.
[0066] Step 6: Remove the barrier layer 200 from step 5, reform the barrier layer 200, etch the barrier layer 200 to form a via, and implant ions to form a P-type source region 1042.
[0067] Step 7: Remove the barrier layer 200 from step 6, reform the barrier layer 200, etch the barrier layer 200 to form a via, and implant ions to form an N-type source region 1041.
[0068] Step 8: Remove the barrier layer 200 from step 7, reform the barrier layer 200, etch the barrier layer 200 to form a via, and form the gate protection zone 107; the gate protection zone 107 can be formed by depositing a high concentration of P-type silicon carbide material and then using high-temperature thermal diffusion.
[0069] Step 9: Remove the barrier layer 200 from step 8, reform the barrier layer 200, etch the barrier layer 200 to form a via, and deposit to form an insulating dielectric layer 109.
[0070] Step 10: Remove the barrier layer 200 from step 9, reform the barrier layer 200, etch the barrier layer 200 to form a via, deposit metal, and form the gate metal layer 110.
[0071] Step 11: Remove the barrier layer 200 from step 10, reform the barrier layer 200, etch the barrier layer 200 to form a via, deposit metal to form a source metal layer 111, the source metal layer 111 is short-circuited with the source protection zone 103, remove the barrier layer 200, and the fabrication is complete.
[0072] In another embodiment of this invention, the doping concentration of the silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of both the first drift layer 102 and the second drift layer 108 is 6-10e15cm. -3 The doping concentration in the low-resistivity region 106 is 6-10e16cm. -3 The doping concentration of the shunt region 105 is 1-5e17cm. -3 The doping concentration of the gate protection zone 107 is 5-8e18cm. -3 The doping concentration of source polar protection zone 103 is 5-8e18cm. -3 The doping concentration of the P-type well region 104 is 1-5e16cm. -3 The doping concentration of the P-type source region 1042 is 1-5e19cm. -3 The insulating dielectric layer 109 can be made of silicon dioxide, and the doping concentration of the N-type source region 1041 is 2-8e18cm. -3The doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112, reducing the overall on-resistance of the device. The doping concentration of the first drift layer 102 is a trade-off between the reverse breakdown voltage and on-resistance of the device. The doping concentration of the gate protection zone 107 is designed to protect the gate of the device and shield the gate-drain capacitance, reduce the Miller capacitance, and improve the switching speed of the device. The doping concentration of the shunt region 105 is to reduce the bulk resistance of the device and reduce the conduction loss. It is also to reduce the diffusion width of the space charge region formed by the source protection zone 103 and the P-type well region 104 with the JFET region when the drain of the device is subjected to a high voltage short circuit, thereby increasing the low-resistance conductive region of the JFET region, improving the short-circuit freewheeling capability of the device, and avoiding rapid heating of the device due to high electric field strength and high current, which would affect the UIS characteristics of the device. The doping concentration of the low-resistance region 106 is to form a low-resistance channel with the shunt region 105 when the device is short-circuited, improving the device's UIS resistance. The doping concentration of the source protection zone 103 is to transfer a low potential to the P-type well region 104 inside the device, thereby preventing the structure of the N-type source region 1041-P-type well region 104-source protection zone 103-first drift layer 102 from conducting, thus improving the device's UIS resistance. The doping concentration of the P-type source region 1042 is designed with two considerations: first, to reduce the contact resistance between the P-type source 1042 and the source metal layer 111, thereby reducing the conduction loss of the parasitic pn junction diode; second, to ensure that when a high voltage is achieved to the drain in the P-type source region 1041, the diffusion rate of the space charge region is reduced when it diffuses to the device gate and source. The doping concentration of the P-type well region 104 is not only to reduce the gate control charge of the device gate and improve the switching speed of the device, but also to form a buffer zone between the P-type source region 1042 and the N-type source region 1041, thereby reducing the electric field strength near the N-type source region 1041 and improving the reliability of the device near the N-type source region 1041.
[0073] The silicon carbide substrate 101 has a thickness of 1 μm, the first drift layer 102 has a thickness of 50-100 μm, adjusted within this range according to different requirements for device withstand voltage characteristics, the gate protection zone 107 has a thickness of 200 nm and a width of 1.2 μm, the low-resistivity region 106 also has a width of 1.2 μm and a thickness of 1.5 μm, the shunt region 105 has a width of 0.6 μm and a thickness of 1.2 μm, and the source protection zone 103 has a width of 1.2 μm and a thickness of 40 μm. The width of the P-type source region 1042 is 600 nm and the thickness is 400 nm; the width of the N-type source region 1041 is 400 nm and the thickness is 400 nm; the width of the P-type well region 104 is 1.2 μm and the thickness is 800 nm; the thickness of the insulating dielectric layer 109 is 50 nm and the width is 3 μm; the width of the gate metal layer 110 is 2.8 μm and the thickness is 250 nm; the width of the source metal layer 111 is 0.9 μm and the thickness is 300 nm. The top of the gate protection zone 107 is in direct contact with the insulating dielectric layer 109. Its thickness is designed to ensure protection of the device gate while preventing interference with the formation of conductive channels, thus guaranteeing the device's low-resistance characteristics. The top of the low-resistance region 106 is in direct contact with the gate protection zone 107. This is to form the low-resistance JFET region, constructing a low-resistance channel during normal conduction and short circuits. Its thickness is designed to reduce the diffusion of the space charge region formed by the source protection zone 103 into the device, ensuring the formation of the low-resistance channel in the JFET region. The top of the shunt region 105 is at the same height as the top of the low-resistance region 106. This is to ensure the device's gate control capability, avoid the influence of the shunt region 105 on the P-type well region 104, and shield the source protection zone. The space charge diffusion in the protection region 103 and the P-type well region 104, and the bottom of the shunt region 105 being lower than the source protection region 103, are designed to ensure the shielding effect and the formation of a low-resistance JFET. The source protection region 103 is shorted to the source metal layer 111 of the device to prevent the conduction of parasitic NPN transistors inside the device and to ensure the protection of the device source. The width of the P-type source region 1042 is designed to ensure the freewheeling capability of the device's body diode. The width of the N-type source region 1041 only needs to ensure a low-resistance ohmic contact with the source metal layer 111, and its width has little impact on the characteristics of the device. The width of the P-type well region 104 is formed by the gate control structure based on the P-type source region 1042 and the N-type source region 1041.
[0074] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A low-resistance planar gate silicon carbide VDMOS with high UIS resistance, characterized in that: include: silicon carbide substrate, A first drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a groove is provided on the first drift layer; A source polar protection zone, wherein the lower side of the source polar protection zone is connected to the upper side of the first drift layer; A P-type well region is provided, the lower side of which is connected to the upper side of the source protection zone. An N-type source region and a P-type source region are provided on the P-type well region. The inner side of the P-type source region is connected to the outer side of the N-type source region, and the inner side of the N-type source region is connected to the P-type well region. The shunt region is located in the groove at its lower part, and the outer side of the shunt region is connected to the inner side of the source protection zone and the inner side of the P-type trap region. A low-resistance region, the lower part of which is disposed in the groove, and the outer side of which is connected to the inner side of the diversion region; A gate protection zone, wherein the lower side of the gate protection zone is connected to the upper side of the low resistance region; The second drift layer has its lower side connected to the upper side of the shunt region; the outer side of the second drift layer is connected to the inner side of the P-type well region; and the inner side of the second drift layer is connected to the outer side of the gate protection zone. An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to a P-type well region, a second drift layer and a gate protection zone; A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer; A source metal layer, wherein the source metal layer is connected to the P-type source region and the N-type source region respectively; The source metal layer is short-circuited to the source protection zone; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The lower side of the low-resistance region is lower than the lower side of the shunt region; the upper side of the low-resistance region and the upper side of the shunt region are located on the same plane.
3. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The width of the P-type source region is greater than the width of the N-type source region; the thickness of the P-type source region is equal to the thickness of the N-type source region.
4. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The doping concentration in the low-resistivity region is less than the doping concentration in the shunt region.
5. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The doping concentration in the low-resistivity region is less than that in the gate protection region.
6. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The doping concentrations of the first drift layer and the second drift layer are equal, and the doping concentration of the low-resistivity region is greater than that of the first drift layer.
7. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The doping concentration of the source protection zone is greater than the doping concentration of the P-type well region, the doping concentration of the shunt region, and the doping concentration of the first drift layer.
8. The low-resistance planar gate silicon carbide VDMOS with high UIS resistance as described in claim 1, characterized in that: The silicon carbide substrate, the first drift layer, the second drift layer, the low-resistivity region, and the shunt region are all N-type; the source protection zone and the gate protection zone are both P-type.