MOSFET devices

Abstract

This application discloses a MOSFET device, comprising: a substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer having a first surface facing away from the substrate, the epitaxial layer including a buffer layer, a drift layer, a first doped layer, and a second doped layer stacked together, the buffer layer being in contact with the substrate, and multiple sub-drift layers in the drift layer having different thicknesses and different doping concentrations, the thickness of the multiple sub-drift layers being proportional to the doping concentration, and the sub-drift layer closest to the buffer layer having the highest doping concentration; and multiple source regions, the source regions being spaced apart in the epitaxial layer, with the source regions located on the first surface facing away from the substrate. The aforementioned MOSFET device optimizes the electric field distribution within the drift layer, reducing the peak electric field and transforming the electric field from a traditional high-sharp triangular distribution to a flatter, lower-peak-value trapezoidal distribution, thus solving the problem of excessive on-resistance in MOSFET devices under high voltage conditions in related technologies.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOSFET device. Background Technology

[0002] Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) are a class of voltage-controlled high-power switching devices with fast switching speed, high input impedance, high power density, high conversion efficiency, and high operating frequency. They are widely used in various industrial power supplies, motor drives, electric traction, power quality control, renewable energy generation, national defense, and cutting-edge science and technology.

[0003] A critical issue with power MOSFET devices is that as the breakdown voltage increases, the on-resistance increases rapidly, leading to a significant increase in power loss. Specifically, when designing high-voltage MOSFETs, to ensure the device can withstand high reverse voltages, the thickness of the drift layer needs to be increased and its doping concentration reduced. This is because the drift layer is one of the core structures of a MOSFET, its main function being to provide a high-resistance region to support the device's blocking voltage. However, this results in a significant increase in the drift layer resistance when the device is on, thus increasing the on-resistance (Ron). In the on-state, current encounters higher resistance when passing through the drift layer, leading to increased power loss and reduced device efficiency. Furthermore, the higher on-resistance also generates excessive heat in high-current applications, limiting the MOSFET's rated current capability and operating temperature range.

[0004] Therefore, there is an urgent need to develop a new silicon carbide MOSFET structure that can improve voltage withstand capability while reducing on-resistance. Utility Model Content

[0005] This application provides a MOSFET device to solve the problem of excessive on-resistance of MOSFET devices under high voltage conditions in related technologies.

[0006] According to one aspect of this application, a MOSFET device is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer having a first surface facing away from the substrate, the epitaxial layer including a buffer layer, a drift layer, a first doped layer and a second doped layer stacked together, the buffer layer being in contact with the substrate, the drift layer including multiple sub-drift layers, the multiple sub-drift layers having different thicknesses and different doping concentrations, and the thickness of the multiple sub-drift layers being proportional to the doping concentration, the drift layer closest to the sub-buffer layer having the highest doping concentration, the substrate and the epitaxial layer both being of the first doping type; and a plurality of source regions spaced apart in the epitaxial layer, the source regions located on the surface facing away from the substrate being located on the first surface.

[0007] Optionally, the thickness of the multiple sub-drift layers increases along a first direction, and the doping concentration of the multiple sub-drift layers increases along a first direction, where the first direction is the direction from the second doped layer to the buffer layer.

[0008] Optionally, the thickness of the multiple sub-drift layers increases by a factor of 2 to 10 along the first direction.

[0009] Optionally, the doping concentration of the multilayer sub-drift layer increases by a factor of 2 to 10 along the first direction.

[0010] Optionally, the doping concentration of the buffer layer is greater than the doping concentration of the drift layer, the doping concentration of the drift layer is greater than the doping concentration of the first doped layer, the doping concentration of the second doped layer is greater than the doping concentration of the first doped layer, and both the substrate and the epitaxial layer are of the first doping type.

[0011] Optionally, the doping concentration of the buffer layer is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The thickness of the buffer layer is 1 μm to 2 μm; the doping concentration of the first doped layer is 1 × 10⁻⁶. 15 cm -3 ~1×10 16 cm -3 The thickness of the first doped layer is 1 μm to 2 μm; the doping concentration of the second doped layer is 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The thickness of the second doped layer is 1 μm to 2 μm.

[0012] Optionally, the thickness of the source region is less than or equal to the thickness of the second doped layer.

[0013] Optionally, the thickness of the source region is 0.7 μm to 1 μm.

[0014] Optionally, the source region structure includes a first heavily doped region, a second heavily doped region, and a body region. The first heavily doped region is in contact with the second heavily doped region and is located within the body region. The second heavily doped region is located on the side of the first heavily doped region closer to the first region. The first region is a portion of the epitaxial layer located between adjacent source regions. The body region is located on the side of the first heavily doped region and the second heavily doped region closer to the substrate, and on the side of the second heavily doped region closer to the first region, respectively. The first heavily doped region and the body region have a second doping type, and the second heavily doped region has the first doping type.

[0015] Optionally, it further includes a gate oxide and a gate, wherein the gate oxide is located on the side of the epitaxial layer opposite to the substrate in a portion of the source region and between adjacent source regions, and the gate is located on the side of the gate oxide opposite to the substrate.

[0016] This application provides a MOSFET device by configuring the drift layer as multiple sub-drift layers with varying thicknesses and doping concentrations. The thickness of each sub-drift layer is proportional to its doping concentration, thus achieving a variable doping concentration design for the drift layer. This optimizes the electric field distribution within the drift layer, reducing the peak electric field. The electric field distribution changes from a traditional high-sharp triangular distribution to a flatter, lower-peak-value trapezoidal distribution, resulting in a more uniform charge distribution and effectively reducing the peak electric field intensity below the material's critical value, significantly improving the device's blocking voltage capability. Simultaneously, the variable doping concentration design maintains low on-resistance. By placing the sub-layer with the highest doping concentration at the bottom of the drift layer, a low-resistance path is formed, maintaining low-loss characteristics even under high voltage conditions. Therefore, this application improves the performance and reliability of silicon carbide MOSFET devices through the aforementioned variable doping concentration design of the drift layer. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This is a cross-sectional structural schematic diagram of a MOSFET device according to an embodiment of this application;

[0019] Figure 2 This is a cross-sectional structural schematic diagram of another MOSFET device provided according to an embodiment of this application.

[0020] The above figures include the following reference numerals:

[0021] 10. Substrate; 20. Epitaxial layer; 201. First surface; 202. First region; 21. Buffer layer; 22. Drift layer; 221. First sub-drift layer; 222. Second sub-drift layer; 223. Third sub-drift layer; 224. Fourth sub-drift layer; 300. nth sub-drift layer; 23. First doped layer; 24. Second doped layer; 30. Source region; 31. Body region; 32. First heavily doped region; 33. Second heavily doped region; 41. Gate oxide; 42. Gate electrode; 51. Source electrode; 52. Drain electrode. Detailed Implementation

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] As described in the background section, a critical issue with existing power MOSFET devices is that as the device's voltage withstand capability increases, its on-resistance increases rapidly, leading to a significant increase in power loss. There is an urgent need to develop a new silicon carbide MOSFET structure that can reduce on-resistance while improving voltage withstand capability.

[0026] To address the aforementioned technical problems, according to embodiments of this application, a MOSFET device is provided, such as... Figure 1and Figure 2 As shown, the MOSFET device includes: a substrate 10; an epitaxial layer 20 located on one side of the substrate 10, the epitaxial layer 20 having a first surface 201 facing away from the substrate, the epitaxial layer 20 including a buffer layer 21, a drift layer 22, a first doped layer 23 and a second doped layer 24 stacked together, the buffer layer 21 being in contact with the substrate 10, the drift layer 22 including multiple sub-drift layers with different thicknesses and different doping concentrations, and the thickness of the multiple sub-drift layers being proportional to the doping concentration, the sub-drift layer closest to the buffer layer 21 having the highest doping concentration, both the substrate 10 and the epitaxial layer 20 being of the first doping type; and a plurality of source regions 30 spaced apart in the epitaxial layer 20, the source regions 30 being located on the surface facing away from the substrate 10 within the first surface 201. The aforementioned MOSFET device incorporates multiple sub-drift layers with varying thicknesses and doping concentrations. The thickness of each sub-drift layer is directly proportional to its doping concentration, allowing for a variable doping concentration design. This optimizes the electric field distribution within the drift layer, resulting in a silicon carbide MOSFET structure with optimized blocking voltage and conduction characteristics, thus improving the performance of the silicon carbide MOSFET device.

[0027] Specifically, such as Figure 1 As shown, the drift layer includes a first sub-drift layer 221, a second sub-drift layer 222, ..., an nth sub-drift layer 300, where n is an integer greater than 1. The thicknesses of the first sub-drift layer 221, the second sub-drift layer 222 to the nth sub-drift layer 300 are different, and the doping concentration of each sub-drift layer is different. The sub-drift layer closest to the buffer layer 21 in the multilayer sub-drift layer is the first sub-drift layer 221, which has the highest doping concentration.

[0028] By employing the embodiments described above in this application, the drift layer in the MOSFET device is configured as a multi-layer sub-drift layer with varying thicknesses and doping concentrations. The thickness of each sub-drift layer is directly proportional to its doping concentration, thus achieving a variable doping concentration design for the drift layer. This optimizes the electric field distribution within the drift layer. By reducing the peak electric field, the electric field distribution transforms from a traditional high-sharp triangular distribution to a flatter, lower-peak-value trapezoidal distribution. This not only achieves a more uniform charge distribution but also effectively reduces the peak electric field intensity below the material's critical value, significantly improving the device's blocking voltage withstand capability. Simultaneously, the variable doping concentration design maintains a low on-resistance. By placing the sub-layer with the highest doping concentration at the bottom of the drift layer, a low-resistance path is formed, maintaining low-loss characteristics even under high voltage conditions. Therefore, this application improves the performance and reliability of silicon carbide MOSFET devices through the aforementioned variable doping concentration design of the drift layer.

[0029] Specifically, the materials of the drift layer include semiconductor materials such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, and aluminum nitride. Those skilled in the art can make reasonable selections according to actual needs, without applying for or specifying any limitations.

[0030] In some alternative implementations, the process of forming the drift layer includes, but is not limited to, deposition and epitaxial growth processes. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, making it easy to achieve the target doping distribution. This is not only applicable to silicon-based power devices, but can also avoid the difficulties of implantation doping in silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate, and has low cost. The deposition process includes, but is not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD). Physical Vapor Deposition (PVD) includes, but is not limited to, magnetron sputtering, reactive sputtering, DC sputtering, AC sputtering, vacuum coating, and arc evaporation. Chemical Vapor Deposition (CVD) includes, but is not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal-Organic Chemical Vapor Deposition (MOCVD), and Laser-Induced Chemical Vapor Deposition (LCVD). Those skilled in the art can choose the appropriate process according to actual needs, and no specific limitations are imposed without application.

[0031] Furthermore, impurities may exist in the substrate, and there is a significant difference in lattice constant between the substrate and the drift layer. Direct contact between the substrate and the drift layer can lead to interface distortion and stress accumulation, and also allow impurities from the substrate to enter the drift layer, thus affecting its performance. Placing a buffer layer between the substrate and the drift layer, and adjusting its material and concentration, can reduce lattice mismatch, lower interfacial stress, and maintain the purity of the drift layer and the stability of the device. Additionally, the thickness of the buffer layer can be designed to regulate the stress state between the substrate and the drift layer, and this helps improve the quality of the grown drift layer, thereby enhancing the electrical performance and reliability of the device. The concentration of the buffer layer is crucial for the relationship between the drift layer and the substrate.

[0032] Specifically, the substrate material includes semiconductor materials such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, and aluminum nitride. Those skilled in the art can make reasonable selections for specific substrate materials according to actual needs, and no specific restrictions are imposed without application.

[0033] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the thickness of the multilayer sub-drift layer increases along the first direction A, and the doping concentration of the multilayer sub-drift layer increases along the first direction A, where the first direction A is the direction from the second doped layer 24 to the buffer layer 21.

[0034] Specifically, when a MOSFET device is turned on, current flows from the source to the drain. The thicker the sub-drift layer, the greater the resistance of the current within that sub-drift layer. As the thickness of multiple sub-drift layers increases along a first direction, the resistance of each sub-drift layer also increases along the first direction, forming a resistance gradient. This makes the current path smoother, reducing current collisions and scattering within the drift layers, thereby lowering the on-resistance. Furthermore, the thickness of the multiple sub-drift layers also alters the electric field distribution, promoting a more uniform electric field distribution within the drift layers and improving the device's blocking performance.

[0035] Furthermore, when the MOSFET device is turned on, the higher the doping concentration of the sub-drift layer, the more charge carriers there are in the sub-drift layer. The higher the concentration of charge carriers, the stronger the electric field. As the doping concentration of the multilayer sub-drift layers increases along the first direction, the electric field strength of each sub-drift layer also increases along the first direction, forming a gradient of electric field strength. This makes the electric field distribution within the drift layer more uniform, optimizes the electric field distribution, and improves the device's blocking performance.

[0036] In some alternative embodiments, the thickness of the multilayer sub-drift layer increases by a factor of 2 to 10 along the first direction, or the doping concentration of the multilayer sub-drift layer increases by a factor of 2 to 10 along the first direction.

[0037] In the above optional embodiments, by increasing the thickness or doping concentration of the multilayer sub-drift layer by a factor that satisfies the above range along the first direction, the electric field is no longer highly concentrated near the surface, but is more uniformly distributed over the entire drift layer thickness, making the electric field distribution inside the drift layer flatter and close to a trapezoidal distribution. This effectively reduces the peak electric field at the PN junction interface, which can significantly improve the breakdown voltage, reduce the specific on-resistance, improve switching performance, and enhance reliability.

[0038] In some alternative implementations, the doping concentration of the buffer layer is greater than that of the drift layer, the doping concentration of the drift layer is greater than that of the first doped layer, the doping concentration of the second doped layer is greater than that of the first doped layer, and both the substrate and the epitaxial layer are of the first doping type.

[0039] Specifically, the second doped layer contacts the source region and also the channel. The second doped layer has a higher doping concentration, which increases the number of charge carriers near the channel. These charge carriers move directionally under the influence of an electric field, and the increased number of charge carriers leads to an increase in the current flowing through the channel, contributing to a more uniform current distribution within the channel. Furthermore, the increased doping concentration of the second doped layer reduces the resistivity of the channel, thereby lowering the on-resistance of the device.

[0040] In addition, the doping concentration of the buffer layer is greater than that of the drift layer but less than that of the substrate. This means that the buffer layer acts as a buffer between the drift layer and the substrate, optimizing the electric field between the substrate and the drift layer and further improving the device's blocking performance.

[0041] In some specific implementations, the doping concentration of the buffer layer is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The thickness of the buffer layer is 1 μm to 2 μm; the doping concentration of the first doped layer is 1 × 10⁻⁶. 15 cm -3 ~1×10 16 cm -3 The thickness of the first doped layer is 1 μm to 2 μm; the doping concentration of the second doped layer is 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The thickness of the second doped layer is 1 μm to 2 μm.

[0042] Specifically, the doping concentration relationships among the drift layer, the first doped layer, and the second doped layer satisfy the following: the doping concentration of the drift layer is greater than that of the first doped layer, and the doping concentration of the first doped layer is less than that of the second doped layer. The doping concentration relationships among the drift layer, the buffer layer, and the substrate satisfy the following: the doping concentration of the drift layer is less than that of the first doped layer, and the doping concentration of the buffer layer is less than that of the substrate. The doping concentration of the buffer layer is 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The thickness of the substrate is 330μm to 370μm.

[0043] In some alternative implementations, the thickness of the source region is less than or equal to the thickness of the second doped layer, for example, such as Figure 1 As shown, the thickness of the second doped layer is greater than the thickness of the source region, meaning the source region is located within the second doped layer, thus the channel of the source region is located within the second doped layer; another example is... Figure 2 As shown, the thickness of the source region is equal to the thickness of the second doped layer. In this case, the bottom surface of the source region structure contacts the first doped layer, ensuring that the side surface of the source region structure contacts the second doped layer. In both embodiments described above, the second doped layer is ensured to contact the channel of the source region. The second doped layer helps to make the current distribution in the channel more uniform and reduces the on-resistance of the device.

[0044] In some specific implementations, the thickness of the source region is 0.7 μm to 1 μm.

[0045] Specifically, when the thickness of the source region can be 0.7 μm, the thickness of the second doped layer can be 1 μm, 1.5 μm, or 2 μm; when the thickness of the source region can be 1 μm, the thickness of the second doped layer can be 1 μm, 1.5 μm, or 2 μm. In particular, when the source region structure is 1 μm and the second doped layer is 1 μm, the bottom surface of the source region structure is in contact with the first doped layer, and the side surface of the source region structure is in contact with the second doped layer.

[0046] In some alternative implementations, such as Figures 1 to 2 As shown, the source region 30 includes a body region 31, a first heavily doped region 32, and a second heavily doped region 33. The first heavily doped region 32 is in contact with the second heavily doped region 33 and is located in the body region 31. The second heavily doped region 33 is located on the side of the first heavily doped region 32 near the first region 202. The first region 202 is a portion of the epitaxial layer 20 located between adjacent source regions 30. The body region 31 is located on the side of the first heavily doped region 32 and the second heavily doped region 33 near the substrate 10, and on the side of the second heavily doped region 33 near the first region 202. The first heavily doped region 32 and the body region 31 have a second doping type, and the second heavily doped region 33 has a first doping type.

[0047] Furthermore, the depth of the first doped region is 0.3 μm to 0.5 μm, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 ~2×10 20 cm -3 The depth of the second doped region is 0.3 μm to 0.5 μm, and the doping concentration is 10. 20 cm -3 ~2×10 20 cm -3 .

[0048] Specifically, the depth of the first doped region can be 0.3 μm, and the doping concentration is 1 × 10⁻⁶. 20 cm -3The depth of the second doped region can be 0.3 μm, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 The depth of the first doped region can be 0.4 μm, and the doping concentration is 1.5 × 10⁻⁶. 20 cm -3 The depth of the second doped region can be 0.4 μm, and the doping concentration is 1.5 × 10⁻⁶. 20 cm -3 The depth of the first doped region can be 0.5 μm, and the doping concentration is 2 × 10⁻⁶. 20 cm -3 The depth of the second doped region can be 0.5 μm, and the doping concentration is 2 × 10⁻⁶. 20 cm -3 Furthermore, the doping concentrations of the first doped region and the second doped region can be different, and the depths of the first doped region and the second doped region can be different; this application does not impose specific limitations on these.

[0049] In some alternative implementations, the depth of the first doped region is greater than the depth of the second doped region.

[0050] For example, the depth of the first doped region is 0.4 μm, the depth of the second doped region is 0.3 μm, and the depth of the bulk region is 0.7 μm to 1 μm.

[0051] Specifically, the body region serves as the channel of the source region. When a voltage is applied to the device gate, an electric field is generated in the channel, which attracts the flow of charge carriers. When the voltage applied to the gate is large, current can flow in the channel. When the voltage applied to the gate is small, the conductivity of the channel weakens. That is, the voltage of the gate can effectively control the conductivity of the channel.

[0052] In some alternative embodiments, the processes for forming the first heavily doped region, the second heavily doped region, and the bulk region in the source region include, but are not limited to, ion implantation and diffusion processes. Ion implantation involves injecting a high-energy ion beam into a semiconductor material; it is a process where ions collide with semiconductor atoms and embed the ions into the semiconductor crystal. Ion implantation allows for precise control of concentration and depth, and ion doping can be achieved at relatively low temperatures. However, ion implantation equipment is expensive and costly. Diffusion, on the other hand, involves allowing impurity atoms to diffuse freely along the thermal gradient of the crystal under thermal equilibrium conditions within the semiconductor through high temperatures or chemical reactions to achieve doping. Diffusion does not require expensive equipment but requires strict temperature and time control. It cannot precisely control the distribution and concentration of impurity atoms. Those skilled in the art can choose the appropriate method based on actual needs, and no specific limitations are imposed.

[0053] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the MOSFET device also includes a gate oxide 41 and a gate 42. The gate oxide 41 is located on the side of the partial source region 30 and the epitaxial layer 20 located between adjacent source regions away from the substrate 10, respectively. The gate 42 is located on the side of the gate oxide 41 away from the substrate.

[0054] Specifically, the gate oxide is in contact with the body region, and the conductivity of the body region is controlled by applying a voltage to the gate. The gate oxide material includes, but is not limited to, any one or more of silicon oxide, aluminum oxide (Al₂O₃), titanium oxide (TiO₂), germanium oxide (GeO₂), gallium oxide (Ga₂O₃), and indium tin oxide (In₂O₅Sn), and this application does not impose a specific limitation. The gate material includes, but is not limited to, metals, polycrystalline silicon, or metal silicides. The metal material may include, but is not limited to, aluminum, copper, tantalum, and tungsten or alloys; the polycrystalline silicon material may include polycrystalline silicon and doped polycrystalline silicon; metal silicides are formed by doping polycrystalline silicon with metals having high melting points, such as tungsten, titanium, cobalt, or nickel, which have good conductivity and high-temperature resistance. This application does not impose a specific limitation on the above gate materials.

[0055] In other alternative implementations, such as Figure 1 and Figure 2 As shown, the MOSFET device also includes a source 51 and a drain 52, wherein the source 51 is located on the side of the source region 30 away from the substrate, and the drain is located on the side of the substrate 10 away from the epitaxial layer 20.

[0056] Specifically, the materials for the source electrode 51 and the drain electrode 52 include, but are not limited to, alloys of one or more of the following metals: silver, copper, aluminum, gold, titanium, nickel, platinum, and palladium. Those skilled in the art may make reasonable selections according to actual needs, without applying for or specifying any particular material.

[0057] In a MOSFET device, the source electrode and the source region contact serve as the drain electrode, while the drain electrode and the substrate contact also serve as the drain electrode, influencing the current input and output of the MOSFET device. An ohmic contact can be formed between the drain substrate and the substrate to reduce the on-state current of the MOSFET device. For example, the drain material can be a TiNiAg alloy, which forms an ohmic contact with the substrate.

[0058] The MOSFET devices described above in the embodiments of this application will now be described in conjunction with specific examples.

[0059] Example 1

[0060] This application provides a MOSFET device, such as... Figure 2As shown, the system includes a substrate 10, an epitaxial layer 20, and a plurality of source regions 30. The epitaxial layer 20 is located on one side of the substrate 10 and has a first surface 201 facing away from the substrate 10, wherein:

[0061] Both substrate 10 and epitaxial layer 20 are of the first doping type;

[0062] Epitaxial layer 20 includes a buffer layer 21, a drift layer 22, a first doped layer 23 and a second doped layer 24 stacked together, with the buffer layer 21 in contact with the substrate 10;

[0063] The drift layer 22 includes four sub-drift layers, namely the first sub-drift layer 221, the second sub-drift layer 222, the third sub-drift layer 223, and the fourth sub-drift layer 224;

[0064] The source regions 30 are spaced apart in the epitaxial layer 20, and the source regions 30 are located on the surface opposite to the substrate 10 in the first surface 201.

[0065] The doping concentration of substrate 10 is 2 × 10⁻⁶. 19 cm -3 The thickness is 350 μm; the doping concentration of buffer layer 21 is 7 × 10⁻⁶. 19 cm -3 The thickness is 1.5 μm; the drift layer 22 has four sub-drift layers, and the doping concentration of the first sub-drift layer 221 is 1.25 × 10⁻⁶. 18 cm -3 The thickness is 8 μm; the doping concentration of the second sub-drift layer 222 is 2.5 × 10⁻⁶. 17 cm -3 The thickness is 4 μm; the doping concentration of the third sub-drift layer 223 is 5 × 10⁻⁶. 16 cm -3 The thickness is 2 μm; the doping concentration of the fourth sub-drift layer 224 is 1 × 10⁻⁶. 16 cm -3 The thickness is 1 μm; the doping concentration of the first doped layer 23 is 5 × 10⁻⁶. 15 cm -3 The thickness is 1.5 μm; the doping concentration of the second doped layer 24 is 1 × 10⁻⁶. 17 cm -3 The thickness is 1.5μm.

[0066] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0067] This invention provides a MOSFET device in which the drift layer is configured as a multi-layered sub-drift layer with varying thicknesses and doping concentrations. The thickness of each sub-drift layer is proportional to its doping concentration, thus achieving a variable doping concentration design for the drift layer. This optimizes the electric field distribution within the drift layer, reducing the peak electric field. The electric field distribution transforms from a traditional high-sharp triangular distribution to a flatter, lower-peak-value trapezoidal distribution, resulting in a more uniform charge distribution and effectively reducing the peak electric field intensity below the material's critical value, significantly improving the device's blocking voltage capability. Simultaneously, the variable doping concentration design maintains low on-resistance. By placing the sub-layer with the highest doping concentration at the bottom of the drift layer, a low-resistance path is formed, maintaining low-loss characteristics even under high voltage conditions. Therefore, this application improves the performance and reliability of silicon carbide MOSFET devices through the aforementioned variable doping concentration design of the drift layer.

[0068] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0069] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOSFET device, characterized in that, include: Substrate; An epitaxial layer is located on one side of the substrate and has a first surface facing away from the substrate. The epitaxial layer includes a buffer layer, a drift layer, a first doped layer, and a second doped layer stacked together. The buffer layer is in contact with the substrate. The drift layer includes multiple sub-drift layers with different thicknesses and different doping concentrations. The thickness of the multiple sub-drift layers is proportional to the doping concentration. The sub-drift layer closest to the buffer layer has the highest doping concentration. Both the substrate and the epitaxial layer are of the first doping type. Multiple source regions are spaced apart in the epitaxial layer, and the source regions are located on the surface opposite to the substrate in the first surface.

2. The MOSFET device according to claim 1, characterized in that, The thickness of the multiple sub-drift layers increases along a first direction, and the doping concentration of the multiple sub-drift layers increases along a first direction, where the first direction is the direction from the second doped layer to the buffer layer.

3. The MOSFET device according to claim 2, characterized in that, The thickness of the sub-drift layers in the multilayer increases by a factor of 2 to 10 along the first direction.

4. The MOSFET device according to claim 2, characterized in that, The doping concentration of the sub-drift layers in the multilayer increases by a factor of 2 to 10 along the first direction.

5. The MOSFET device according to claim 1, characterized in that, The doping concentration of the buffer layer is greater than that of the drift layer, the doping concentration of the drift layer is greater than that of the first doped layer, the doping concentration of the second doped layer is greater than that of the first doped layer, and both the substrate and the epitaxial layer are of the first doping type.

6. The MOSFET device according to claim 5, characterized in that, The doping concentration of the buffer layer is 5×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The thickness of the buffer layer is 1μm to 2μm; The doping concentration of the first doped layer is 1×10 15 cm -3 ~1×10 16 cm -3 The thickness of the first doped layer is 1 μm to 2 μm; The doping concentration of the second doped layer is 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the second doped layer is 1 μm to 2 μm.

7. The MOSFET device according to claim 1, characterized in that, The thickness of the source region is less than or equal to the thickness of the second doped layer.

8. The MOSFET device according to claim 1, characterized in that, The thickness of the source region is 0.7 μm to 1 μm.

9. The MOSFET device according to claim 1, characterized in that, The source region structure includes a first heavily doped region, a second heavily doped region, and a body region. The first heavily doped region is in contact with the second heavily doped region and is located within the body region. The second heavily doped region is located on the side of the first heavily doped region closer to the first region. The first region is a portion of the epitaxial layer located between adjacent source regions. The body region is located on the side of the first heavily doped region and the second heavily doped region closer to the substrate, and on the side of the second heavily doped region closer to the first region, respectively. The first heavily doped region and the body region have a second doping type, and the second heavily doped region has the first doping type.

10. The MOSFET device according to claim 1, characterized in that, It also includes a gate oxide and a gate, wherein the gate oxide is located on the side of the epitaxial layer opposite to the substrate in a portion of the source region and between adjacent source regions, and the gate is located on the side of the gate oxide opposite to the substrate.

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