A breakdown-proof structure of a GaN-HEMT chip

Abstract

This invention provides a breakdown-resistant structure for GaN-HEMT chips, belonging to the field of semiconductor device technology. It includes a substrate, an epitaxial layer, a source, a drain, a gate, and a guard ring. The guard ring is disposed around the source and drain in the edge region of the epitaxial layer and is electrically connected to the epitaxial layer via a resistive contact structure. The epitaxial layer includes a buffer layer and an active layer. The guard ring adopts an inner and outer double-ring design connected by a connecting bridge. The guard ring is disposed around the source and drain in the edge region of the epitaxial layer and is electrically connected to the epitaxial layer via a resistive contact structure. The resistive contact structure includes multiple contact resistor units, which are uniformly distributed along the circumference of the guard ring. Through reasonable geometric parameters and material selection, it provides a current conduction path under high voltage stress, avoids electric field concentration, and solves the technical problem of easy breakdown and damage in existing GaN-HEMT chips.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor device technology, and specifically relates to a breakdown protection structure for a GaN-HEMT chip. Background Technology

[0002] In existing technologies, gallium nitride (GaN) high electron mobility transistors (HEMTs) are widely used in high-frequency, high-power applications, playing a crucial role, particularly in RF power amplifiers, switching power supplies, and power electronic devices. Traditional GaN-HEMT chip designs primarily focus on the device's conduction and switching characteristics. However, in practical applications, they frequently face high voltage stress. Existing device structures are prone to electric field concentration at the chip edges when subjected to transient overvoltages or electrostatic discharges, leading to localized breakdown damage. Current protection methods mainly include external protection circuits and passivation layers on the chip surface. However, these methods cannot fundamentally solve the problem of electric field distribution within the chip. In other words, existing technologies suffer from insufficient breakdown resistance of GaN-HEMT chips under high voltage stress. Utility Model Content

[0003] In view of this, the present invention provides a breakdown protection structure for GaN-HEMT chips, capable of... This utility model is implemented as follows: This invention provides a breakdown protection structure for a GaN-HEMT chip, comprising a substrate, an epitaxial layer, a source, a drain, a gate, and a guard ring. The epitaxial layer is located on the upper surface of the substrate, the source and drain are located at opposite ends of the epitaxial layer, and the gate is located on the epitaxial layer between the source and drain. The guard ring is disposed around the source and drain in the edge region of the epitaxial layer and is electrically connected to the epitaxial layer through a resistive contact structure.

[0004] The technical effects of the anti-breakdown structure for GaN-HEMT chips provided by this utility model are as follows: The protective ring is set around the source and drain in the edge region of the epitaxial layer and is electrically connected to the epitaxial layer through a resistive contact structure. It can provide a current conduction path under high voltage stress, avoid the electric field from concentrating in the critical area of ​​the device, and thus prevent the chip from being damaged by breakdown.

[0005] Based on the above technical solution, the breakdown protection structure of the GaN-HEMT chip of this utility model can be further improved as follows: The resistor connection structure includes multiple resistor units, which are evenly distributed along the circumference of the protective ring. The resistance value of each resistor unit ranges from 100Ω to 10kΩ.

[0006] The beneficial effects of adopting the above-mentioned improved scheme are as follows: the contact resistor units are evenly distributed along the circumference of the protective ring, and the resistance value of each unit is controlled within a reasonable range, ensuring that the leakage current can be limited under overvoltage conditions, while ensuring the uniformity of current distribution and avoiding local overheating.

[0007] Furthermore, the distance between the guard ring and the source is twice the distance between the guard ring and the drain, and the width of the guard ring is 10μm to 50μm.

[0008] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the distance between the guard ring and the source and drain is equal to twice the distance, which ensures the symmetry of the electric field distribution; and the reasonable design of the guard ring width ensures sufficient current carrying capacity and good heat dissipation performance.

[0009] Furthermore, the epitaxial layer includes a buffer layer and an active layer. The buffer layer is located on the upper surface of the substrate, and the active layer is located on the upper surface of the buffer layer. The gate is isolated from the active layer by an insulating layer.

[0010] The beneficial effects of adopting the above-mentioned improved scheme are as follows: the layered structure design of the epitaxial layer can achieve effective confinement and transport of charge carriers, and the setting of the insulating layer ensures good isolation between the gate and the active layer, thereby improving the control performance and reliability of the device.

[0011] Furthermore, the protective ring includes an inner ring segment and an outer ring segment. The inner ring segment is arranged around the active region of the active layer, and the outer ring segment is arranged around the inner ring segment. The inner ring segment and the outer ring segment are connected by a connecting bridge.

[0012] The beneficial effects of adopting the above-mentioned improved scheme are as follows: the double-ring structure design of the protective ring enhances the protection effect, the inner ring section mainly undertakes the near-field protection function, the outer ring section provides far-field protection, and the connecting bridge ensures the electrical connection between the two rings.

[0013] Furthermore, the angular intervals when the connecting bridge rotates around the protective ring are 45° to 90°, and the width of the connecting bridge is 5μm to 15μm.

[0014] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the angle spacing and width design of the connecting bridge optimize the current distribution path, avoid the phenomenon of current concentration, and improve the overall current carrying capacity and thermal stability of the protective ring.

[0015] Furthermore, the substrate is made of silicon carbide or sapphire material, with a thickness of 200 μm to 500 μm and a surface roughness of less than 1 nm.

[0016] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the selection of substrate material and surface quality control ensure good growth quality of epitaxial layer, and the appropriate thickness design takes into account both mechanical strength and thermal conductivity.

[0017] Furthermore, the buffer layer comprises multiple gallium nitride sublayers with decreasing thicknesses, the bottom sublayer having a thickness of 500 nm to 1000 nm.

[0018] The beneficial effects of adopting the above-mentioned improved scheme are as follows: the multi-layer structure design of the buffer layer effectively alleviates the lattice mismatch stress between the substrate and the active layer, and the decreasing thickness design realizes the layer-by-layer release of stress.

[0019] Furthermore, the active layer is composed of a heterostructure of aluminum gallium nitride and gallium nitride, with a total thickness of 20 nm to 100 nm.

[0020] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the heterostructure of the active layer forms a two-dimensional electron gas channel with high mobility, and the reasonable total thickness design ensures the high-frequency performance and power handling capability of the device.

[0021] Furthermore, the insulating layer is made of silicon oxide or silicon nitride material, with an insulating layer thickness of 10nm to 50nm and a gate length of 0.1μm to 2μm.

[0022] The beneficial effects of adopting the above-mentioned improvement scheme are as follows: the optimized design of the insulating layer material and thickness ensures good control performance of the gate, and the design of the gate length balances the frequency response and power density requirements of the device. Compared with the prior art, the beneficial effects of the anti-breakdown structure of GaN-HEMT chip provided by this utility model are as follows: By setting a protective ring structure in the edge area of ​​the chip and connecting it to the epitaxial layer by means of resistance, this utility model effectively disperses the electric field intensity under high voltage stress, provides a safe current conduction path, significantly improves the chip's withstand voltage and reliability, and solves the technical problem of easy breakdown of GaN-HEMT chips in the prior art. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a breakdown protection structure for a GaN-HEMT chip; Figure 2 for Figure 1 Enlarged view of A in the middle; The attached diagram lists the components represented by each number as follows: 1. Substrate; 21. Buffer layer; 22. Active layer; 31. Source; 32. Drain; 33. Gate; 34. Insulating layer; 41. Guard ring; 42. Resistor contact structure; 421. Contact resistor unit; 431. Inner ring segment; 432. Outer ring segment; 433. Connecting bridge. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0026] like Figure 1 , Figure 2 As shown, this invention provides a breakdown protection structure for a GaN-HEMT chip, including a substrate 1, an epitaxial layer, a source 31, a drain 32, a gate 33, and a guard ring 41. The epitaxial layer is located on the upper surface of the substrate 1 and includes a buffer layer 21 and an active layer 22. The buffer layer 21 is directly grown on the upper surface of the substrate 1, and the active layer 22 is located on the upper surface of the buffer layer 21. The source 31 and drain 32 are located at the two ends of the active layer 22, respectively. The gate 33 is located above the active layer 22 between the source 31 and drain 32 and is isolated from the active layer 22 by an insulating layer 34. The guard ring 41 is disposed around the source 31 and drain 32 in the edge region of the epitaxial layer and is electrically connected to the epitaxial layer through a resistor abutment structure 42. The resistor contact structure 42 includes multiple contact resistor units 421, which are uniformly distributed circumferentially along the guard ring 41. The angular interval between adjacent contact resistor units 421 is 30° to 60°, and the resistance value of each contact resistor unit 421 is controlled within the range of 100Ω to 10kΩ. The guard ring 41 is twice the distance from the source 31 as twice the distance from the drain 32, ensuring the symmetry of the electric field distribution. The width of the guard ring 41 is designed to be 10μm to 50μm, and the depth is 50% to 80% of the total thickness of the epitaxial layer. The guard ring 41 includes an inner ring segment 431 and an outer ring segment 432. The inner ring segment 431 is arranged around the active region of the active layer 22, 20μm to 50μm from the edge of the active region of the device. The outer ring segment 432 is arranged around the inner ring segment 431, with a spacing of 15μm to 30μm from the inner ring segment 431. The inner ring segment 431 and the outer ring segment 432 are connected by a connecting bridge 433. The connecting bridge 433 rotates 45° to 90° at different angles around the protective ring 41. The width of the connecting bridge 433 is 5μm to 15μm, and its length is equal to the interval between the inner and outer ring segments.

[0027] The manufacturing process of this solution includes substrate 1 pretreatment, epitaxial layer growth, device fabrication, and guard ring 41 fabrication. First, substrate 1 is cleaned and surface-treated. Then, a buffer layer 21 and an active layer 22 are sequentially grown on substrate 1 using metal-organic chemical vapor deposition (MOCVD). Next, source 31, drain 32, and gate 33 are patterned using photolithography and etching processes. Following this, ohmic contacts are formed through metallization. Finally, guard ring 41 is fabricated using deep etching, and a resistive contact structure 42 is formed through ion implantation or diffusion. During normal operation, guard ring 41 does not participate in current conduction. When subjected to high-voltage surges, guard ring 41 provides a current conduction path through resistive contact structure 42, protecting the device from breakdown damage.

[0028] The main technical advantages of this solution compared to existing technologies are a significant improvement in the chip's breakdown resistance. The protective ring 41 effectively disperses the edge electric field intensity, the double-ring structure forms a gradient protection mechanism, and the resistor-connected structure 42 ensures controlled current discharge, avoiding disordered current surges. The inner ring 431 mainly undertakes near-field electric field modulation, the outer ring 432 provides far-field protection, and the connecting bridge 433 ensures the uniformity of current distribution. The overall structure increases the breakdown voltage by more than 30% without affecting the normal performance of the device, significantly improving the device's reliability and lifespan.

[0029] In the improved embodiment based on paragraph 1, substrate 1 is made of hexagonal silicon carbide material with a thickness of 200 μm to 500 μm. The surface is chemically mechanically polished, and the surface roughness is controlled to be below 1 nm. Buffer layer 21 includes multiple gallium nitride sublayers, comprising a bottom sublayer, a middle sublayer, and a top sublayer, with the sublayer thickness decreasing sequentially: the bottom sublayer has a thickness of 500 nm to 1000 nm, the middle sublayer has a thickness of 300 nm to 600 nm, and the top sublayer has a thickness of 100 nm to 300 nm. Active layer 22 is a heterostructure composed of an aluminum gallium nitride layer and a gallium nitride layer. The aluminum gallium nitride layer is located above the gallium nitride layer, with the aluminum gallium nitride layer having a thickness of 15 nm to 30 nm and the gallium nitride layer having a thickness of 1 μm to 3 μm. A two-dimensional electron gas channel is formed at the heterojunction interface. The insulating layer 34 is made of alumina material deposited by atomic layer deposition. The thickness of the insulating layer 34 is 10nm to 50nm. The gate 33 has a length of 0.1μm to 2μm and adopts a T-shaped structure design. The top width is 2 to 5 times the length of the gate 33.

[0030] In the improved manufacturing process, substrate 1 pretreatment employs a combination of RCA cleaning and high-temperature hydrogen annealing. Epitaxial layer growth utilizes low-pressure metal-organic chemical vapor deposition (MOCVD), with growth temperature controlled between 1000℃ and 1200℃ and growth pressure controlled between 50 Torr and 200 Torr. During device fabrication, source 31 and drain 32 utilize a Ti / Al / Ni / Au multilayer metal system, which undergoes rapid thermal annealing to form ohmic contacts with a contact resistance less than 10^(-6) Ω·cm^2. Gate 33 employs a Ni / Au bilayer metal system, and submicron gate patterns are achieved using electron beam lithography. The protective ring 41 is fabricated using inductively coupled plasma etching (ICP-C), with precise control over etching depth and a surface smoothness better than 5nm.

[0031] The improvement over the basic design lies in the use of optimized material combinations and process parameters. The hexagonal silicon carbide substrate 1 exhibits better thermal conductivity and lattice matching, the multilayer buffer structure more effectively alleviates stress, and the T-type gate 33 design reduces gate resistance and parasitic capacitance. Compared to existing technologies, the improved design further enhances the device's frequency response and power density while maintaining excellent breakdown performance. It also demonstrates better stability and reliability in high-temperature, high-frequency applications, providing an ideal technical solution for next-generation high-performance power devices.

[0032] This embodiment is based on the scheme described in paragraph 1 of the specific implementation method. It uses a 4-inch hexagonal silicon carbide substrate 1 with a thickness of 350 μm and a surface roughness of 0.5 nm. The buffer layer 21 has a total thickness of 2 μm, including a bottom sublayer with a thickness of 800 nm, a middle sublayer with a thickness of 600 nm, and a top sublayer with a thickness of 600 nm. The aluminum composition of each sublayer is 15%, 10%, and 5%, respectively. The active layer 22 includes a 2 μm thick gallium nitride layer and a 25 nm thick aluminum gallium nitride layer, with an aluminum composition of 25%. The two-dimensional electron gas concentration at the heterojunction interface is 1.2 × 10^13 cm^(-2), and the mobility is 1800 cm^2 / V·s. The source 31 and drain 32 use a Ti 20nm / Al 200nm / Ni 40nm / Au 100nm metal system, with a source-drain spacing of 10 μm and a width of 100 μm for both source 31 and drain 32. The gate 33 employs a Ni 50nm / Au 200nm dual-layer metal structure, with a gate length of 0.5μm and a gate width of 100μm. The insulating layer 34 is atomically deposited aluminum oxide with a thickness of 25nm. The guard ring 41 is designed as a double-ring structure, with the inner ring segment 431 35μm away from the active region of the device, and the outer ring segment 432 25μm away from the inner ring segment 431. Both rings are 30μm wide and 3μm deep. Eight connecting bridges 433 are provided, spaced at 45° intervals, with a width of 10μm. The resistor abutment structure 42 includes 32 abutment resistor units 421, each with a resistance of 2kΩ, formed by boron ion implantation. The entire chip area is 2mm × 2mm, manufactured using standard semiconductor processes, including photolithography, etching, ion implantation, metallization, and passivation. Test results show that the breakdown voltage of this embodiment reaches 650V, which is 35% higher than that of similar devices without a protective ring. The leakage current is less than 1μA under a 400V bias voltage. The on-state resistance of the device is 15mΩ·mm, the cutoff frequency is 25GHz, the maximum power density is 8W / mm, and there is no performance degradation after 1000 hours of continuous operation at 150℃. This fully verifies the effectiveness and practicality of the breakdown protection structure.

[0033] This embodiment is based on the improved scheme in paragraph 4 of the specific implementation method. A 6-inch sapphire substrate 1 with a thickness of 430 μm is used, and its surface is chemically and mechanically polished to a roughness of 0.3 nm. The buffer layer 21 adopts a gradient aluminum composition design with a total thickness of 2.5 μm. The bottom sublayer is 1000 nm thick with an aluminum composition of 20%, the middle sublayer is 800 nm thick with an aluminum composition of 15%, and the top sublayer is 700 nm thick with an aluminum composition of 8%, achieving better stress relief. The active layer 22 includes a 1.5 μm thick gallium nitride layer and a 20 nm thick aluminum gallium nitride layer, with an aluminum composition of 30%. Through optimized growth conditions, an electron gas concentration of 1.5 × 10^13 cm^(-2) and a mobility of 2200 cm^2 / V·s were obtained. The source 31 and drain 32 employ an improved metal system of Ti 15nm / Al 150nm / Ti 10nm / Au200nm, reducing the contact resistance to 5×10^(-7) Ω·cm^2, increasing the source-drain spacing to 15μm, and increasing the device width to 200μm. The gate 33 adopts a T-type structure design with a length of 0.25μm and a top width of 1μm, using a Pt20nm / Au 300nm metal system, achieving even lower gate resistance. The insulating layer 34 is made of silicon nitride with a thickness of 20nm and a dielectric constant of 7.5. The guard ring 41 adopts a three-ring structure design: the inner ring 431 is 30μm away from the active region, the middle ring is 20μm away from the inner ring 431, and the outer ring 432 is 20μm away from the middle ring. Each ring has a width of 25μm and a depth of 4μm. Twelve connecting bridges 433 are arranged with an angle interval of 30° and a width of 8μm. The resistor abutment structure 42 includes 48 abutment resistor units 421, each with a resistance value of 1.5kΩ, fabricated using phosphorus ion implantation and laser annealing processes. The entire chip area is 3mm×3mm, manufactured using an advanced 0.25μm process line. Tests show that the breakdown voltage of this embodiment reaches 800V, the on-state resistance is reduced to 12mΩ·mm, the cutoff frequency is increased to 40GHz, the maximum power density reaches 12W / mm, and the performance is stable after 500 hours of operation at 200℃. Compared with Embodiment 1, it has significant improvements in high-frequency performance and power density, while maintaining excellent reliability, making it suitable for more demanding power electronics applications. Specifically, the principle of this utility model is: when the chip is subjected to high voltage stress, the protective ring structure can bear and disperse the concentrated electric field, and the resistor abutment structure provides a controlled current discharge path, avoiding direct current impact on the active area of ​​the device. The dual-ring structure design forms a gradient protection mechanism, with the inner ring undertaking the main protection function and the outer ring providing secondary protection. The connecting bridge ensures uniform current distribution. The multilayer epitaxial structure optimizes carrier transport characteristics, and the insulating layer ensures the stability of gate control. The overall structure significantly improves breakdown resistance while maintaining normal device performance, achieving the design goal of a highly reliable power device.

Claims

1. A breakdown-resistant structure for a GaN-HEMT chip, comprising a substrate, an epitaxial layer, a source, a drain, a gate, and a guard ring, wherein the epitaxial layer is located on the upper surface of the substrate, the source and drain are respectively located at opposite ends of the epitaxial layer, and the gate is located on the epitaxial layer between the source and drain, characterized in that, The guard ring is arranged around the source and drain in the edge region of the epitaxial layer, and the guard ring is electrically connected to the epitaxial layer through a resistor contact structure.

2. The breakdown protection structure for a GaN-HEMT chip according to claim 1, characterized in that, The resistor connection structure includes multiple resistor units, which are evenly distributed along the circumference of the protective ring. The resistance value of each resistor unit ranges from 100Ω to 10kΩ.

3. The breakdown protection structure for a GaN-HEMT chip according to claim 2, characterized in that, The guard ring is twice the distance from the source electrode, which is twice the distance from the drain electrode. The guard ring width is 10μm to 50μm.

4. The breakdown protection structure for a GaN-HEMT chip according to claim 3, characterized in that, The epitaxial layer includes a buffer layer and an active layer. The buffer layer is located on the upper surface of the substrate, and the active layer is located on the upper surface of the buffer layer. The gate is isolated from the active layer by an insulating layer.

5. The breakdown protection structure for a GaN-HEMT chip according to claim 4, characterized in that, The protective ring consists of an inner ring section and an outer ring section. The inner ring section is arranged around the active region of the active layer, and the outer ring section is arranged around the inner ring section. The inner ring section and the outer ring section are connected by a connecting bridge.

6. The breakdown protection structure for a GaN-HEMT chip according to claim 5, characterized in that, The angular intervals when the connecting bridge rotates around the protective ring are 45° to 90°, and the width of the connecting bridge is 5μm to 15μm.

7. The breakdown protection structure for a GaN-HEMT chip according to claim 6, characterized in that, The substrate is made of silicon carbide or sapphire material, with a thickness of 200μm to 500μm and a surface roughness of less than 1nm.

8. The breakdown protection structure for a GaN-HEMT chip according to claim 7, characterized in that, The buffer layer consists of multiple gallium nitride sublayers with decreasing thicknesses, the bottom sublayer having a thickness of 500nm to 1000nm.

9. The breakdown protection structure for a GaN-HEMT chip according to claim 8, characterized in that, The active layer is composed of a heterostructure of aluminum gallium nitride and gallium nitride, with a total thickness of 20nm to 100nm.

10. The breakdown protection structure for a GaN-HEMT chip according to claim 9, characterized in that, The insulating layer is made of silicon oxide or silicon nitride material, with a thickness of 10nm to 50nm and a gate length of 0.1μm to 2μm.

Images