Semiconductor device

Abstract

A semiconductor device. The semiconductor device may include a first nanostructure and a second nanostructure; a gate structure located between the first nanostructure and the second nanostructure; a source / drain region along the sidewalls of the first nanostructure and the second nanostructure; and a spacer layer located between the source / drain region and the gate structure. A first portion of the spacer layer may protrude from the source / drain region toward the gate structure. The first portion of the spacer layer may protrude into a recess in the gate structure.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to T-shaped and U-shaped spacer layers between the gate structure and the source / drain regions. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form electronic components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to shrink the minimum structural size to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, allowing more components to be integrated into a given area. However, as the minimum structural size shrinks, additional problems need to be addressed. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device to solve at least one of the above-mentioned problems.

[0005] In one embodiment, the semiconductor device includes a first nanostructure and a second nanostructure; a gate structure located between the first nanostructure and the second nanostructure; a source / drain region along the sidewalls of the first nanostructure and the second nanostructure; and a spacer layer located between the source / drain region and the gate structure, wherein a first portion of the spacer layer protrudes from the source / drain region toward the gate structure, and wherein the first portion of the spacer layer protrudes into a recess in the gate structure.

[0006] In one embodiment, a first portion of the spacer layer is located between a first portion of the gate structure and a second portion of the gate structure.

[0007] In one embodiment, a first portion of the spacer layer contacts the upper surface of a first portion of the gate structure and the lower surface of a second portion of the gate structure.

[0008] In one embodiment, a first portion of the gate structure is located between a first portion of the spacer layer and the first nanostructure, and a second portion of the gate structure is located between a first portion of the spacer layer and the second nanostructure.

[0009] In one embodiment, a second portion of the spacer layer contacts the first nanostructure and the second nanostructure.

[0010] In one embodiment, the spacer layer is T-shaped.

[0011] In one embodiment, the wavy sidewalls of the spacer layer contact the gate structure.

[0012] In one embodiment, the length of the first portion of the spacer layer is between 0.5 nm and 5 nm.

[0013] In one embodiment, the length of the first portion of the spacer layer is in the ratio of 20% to about 80% to the length of the longest portion of the spacer layer.

[0014] In one embodiment, the width of the first portion of the spacer layer is between 0.5 nm and 5 nm. Attached Figure Description

[0015] Figure 1 Three-dimensional diagrams of nanostructured field-effect transistors are shown in some embodiments.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20CThe accompanying drawings illustrate intermediate processes for manufacturing semiconductor devices such as nanostructured field-effect transistors in some embodiments.

[0017] Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C The accompanying drawings illustrate intermediate processes for manufacturing semiconductor devices such as nanostructured field-effect transistors in some embodiments.

[0018] The attached figures are labeled as follows:

[0019] A-A', B-B', C-C': Reference profiles

[0020] L1, L2, L3, L4: Length

[0021] W1, W2, W3, W4: Width

[0022] 20: Divider

[0023] 50:Substrate

[0024] 50N: n-type region

[0025] 50P: p-type area

[0026] 51, 51A, 51B, 51C: First semiconductor layer

[0027] 52, 52A, 52B, 52C: First nanostructure

[0028] 53, 53A, 53B, 53C: Second semiconductor layer

[0029] 54, 54A, 54B, 54C: Second nanostructures

[0030] 55: Nanostructures

[0031] 64: Multi-layer stacking

[0032] 66: Fins

[0033] 68: Shallow trench isolation zone

[0034] 70: Virtual dielectric layer

[0035] 71: Dummy gate dielectric layer

[0036] 72: Dummy Gate Layer

[0037] 74: Masking layer

[0038] 76: Dummy Gate

[0039] 78: Mask

[0040] 81: Spacer

[0041] 86: First Depression

[0042] 87: First Sacrifice Layer

[0043] 88: Second depression

[0044] 89: Second Sacrificial Layer

[0045] 90: Inner spacer

[0046] 92: Epitaxial source / drain region

[0047] 92A: First liner layer

[0048] 92B: Second liner layer

[0049] 92C: Filler layer

[0050] 94: Contact Etching Stop Layer

[0051] 96: First interlayer dielectric layer

[0052] 98: Third depression

[0053] 100: Gate dielectric layer

[0054] 102: Gate

[0055] 104: Gate Mask

[0056] 106: Second interlayer dielectric layer

[0057] 108: Fourth Depression

[0058] 110: First silicide region

[0059] 112: Source / Drain Contact

[0060] 114: Gate contact

[0061] 120, 130: Semiconductor devices Detailed Implementation

[0062] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity.

[0063] It is understood that the different embodiments or examples provided below may implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where there are additional components between them that are not in direct contact. Furthermore, the same reference numerals may be repeated in various embodiments of the present invention for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0064] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0065] Various embodiments provide semiconductor devices and methods of forming them. The semiconductor device may be a nanostructured field-effect transistor (FET), comprising a channel region, source / drain regions located on the sidewalls of the channel region, a gate structure located between adjacent channel regions, and an inner spacer located on the sidewalls of the gate structure. Some embodiments provide a method of forming a nanostructured FET containing inner spacers and a gate structure of a specific shape and size, wherein a first sacrificial layer and a second sacrificial layer of a specific shape and size are formed between adjacent channel regions. The inner spacer of this shape and size provides sufficient electrical insulation between the source / drain regions and the gate structure, thereby reducing or eliminating leakage current between the source / drain regions and the gate structure. The gate structure of this shape and size reduces resistance in the channel region. This improves the performance and reliability of the semiconductor device.

[0066] Some of the embodiments described herein are illustrated with semiconductor devices containing nanostructured field-effect transistors. However, various embodiments can be used in grains containing other types of transistors (such as fin field-effect transistors, vertical field-effect transistors, complementary field-effect transistors, planar transistors, or the like) to replace or combine with nanostructured field-effect transistors.

[0067] Figure 1This is a three-dimensional diagram of a nanostructured field-effect transistor (such as a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like), as an example. The nanostructured field-effect transistor includes nanostructures 55 (such as nanosheets, nanowires, or the like) on fins 66 on a substrate 50 (such as a semiconductor substrate), wherein the nanostructures 55 serve as channel regions used by the nanostructured field-effect transistor. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation regions 68 are located between adjacent fins 66, and the fins 66 may protrude upwards from between adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are separated from the substrate 50 in the figures and description, the term "substrate" as used herein may refer solely to a semiconductor substrate or a combination of a semiconductor substrate and a shallow trench isolation region. Furthermore, although the bottom of the fins 66 and the substrate 50 are a single continuous material in the figures, the bottom of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this description, fin 66 can be considered as a portion extending between adjacent shallow trench isolation regions 68. Gate dielectric layer 100 is located on the upper surface of fin 66 and extends along the upper surface, sidewalls, and lower surface of nanostructure 55. Gate 102 is located on gate dielectric layer 100. Epitaxial source / drain regions 92 are located on fins 66 on both sides of gate dielectric layer 100 and gate 102.

[0068] Figure 1 The reference cross-sections used in the following figures are shown. Reference cross-section A-A' is along the longitudinal axis of the gate 102 and perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Reference cross-section B-B' is perpendicular to reference cross-section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanostructured field-effect transistors. Reference cross-section C-C' is perpendicular to reference cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor, and is within the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. The following figures are illustrated with reference to the reference cross-sections for clarity. Some embodiments disclosed herein are illustrated using nanostructured field-effect transistors formed using a post-gate fabrication process. In other embodiments, a gate-first process may be used.

[0069] Figures 2 to 20C The accompanying drawings illustrate intermediate processes for manufacturing semiconductor devices such as nanostructured field-effect transistors in some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A For along Figure 1 The cross-sectional view of reference section A-A' shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B For along Figure 1 The cross-sectional view of reference section B-B' shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C For along Figure 1 The cross-sectional view of reference section C-C' shown.

[0070] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate, a semiconductor-on-insulator (SIA) substrate, or the like, and may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a SIA substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium), or combinations thereof.

[0071] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as n-type metal-oxide-semiconductor transistors (e.g., n-type nanostructure field-effect transistors), while the p-type region 50P can be used to form p-type devices such as p-type metal-oxide-semiconductor transistors (e.g., p-type nanostructure field-effect transistors). The n-type region 50N may be physically separated from the p-type region 50P (e.g., separated by the separator 20 shown in the figure), and any number of device structures such as other active devices, doped regions, isolation structures, or the like may be located between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are shown in the figure, any number of n-type regions 50N and p-type regions 50P may be provided.

[0072] In addition Figure 2 In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes interleaved first semiconductor layers 51A to 51C (collectively considered as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively considered as second semiconductor layer 53). For illustrative purposes and the details below, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P. In some embodiments, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned in the n-type region 50N to form channel regions of nanostructured field-effect transistors in the n-type region 50N, and the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned in the p-type region 50P to form channel regions of nanostructured field-effect transistors in the p-type region 50P. In some embodiments, a second semiconductor layer 53 is removed from the n-type region 50N and a first semiconductor layer 51 is patterned to form a channel region for a nanostructured field-effect transistor in the n-type region 50N, and a first semiconductor layer 51 is removed from the p-type region 50P and a second semiconductor layer 53 is patterned to form a channel region for a nanostructured field-effect transistor in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions for nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P.

[0073] The multilayer stack 64 shown in the accompanying drawings contains three first semiconductor layers 51 and three second semiconductor layers 53, and is for illustrative purposes only. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. The epitaxial growth process of each layer of the multilayer stack 64 may employ chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, molecular beam epitaxy, or similar processes. In various embodiments, the first semiconductor layer 51 may be composed of a first semiconductor material such as silicon-germanium or the like, while the second semiconductor layer 53 may be composed of a second semiconductor material different from the first semiconductor material, such as silicon or the like.

[0074] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby patterning the second semiconductor layer 53 to form the channel region of the nanostructured field-effect transistor. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby patterning the first semiconductor layer 51 to form the channel region of the nanostructured field-effect transistor.

[0075] exist Figure 3 In some embodiments shown, fins 66 are formed in substrate 50, while nanostructures 55 are formed in multilayer stack 64. In some embodiments, the method of forming nanostructures 55 and fins 66 in multilayer stack 64 and substrate 50, respectively, may be etching trenches in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. Etching may be anisotropic. The process of etching multilayer stack 64 to form nanostructure 55 may further define first nanostructures 52A to 52C (which may be considered together as first nanostructure 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (which may be considered together as second nanostructure 54) may be defined from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 may be considered together as nanostructure 55.

[0076] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the patterning method for the fins 66 and nanostructures 55 can employ one or more photolithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0077] Figure 3The fins 66 in the n-type region 50N and p-type region 50P shown have substantially the same width and are for illustrative purposes only. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although the fins 66 and nanostructures 55 in the figures each have the same width, in other embodiments the fins 66 and / or nanostructures 55 may have tapered sidewalls, meaning the width of each fin 66 and / or nanostructure 55 may continuously increase in the direction toward the substrate 50. In these embodiments, the nanostructures 55 may each have different widths and may be trapezoidal.

[0078] exist Figure 4 Shallow trench isolation regions 68 can be formed adjacent to fins 66. The shallow trench isolation regions 68 can be formed by depositing an insulating material on the substrate 50, fins 66, nanostructures 55, and between adjacent fins 66. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar processes, or a combination thereof. Other insulating materials formed using any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. Although the insulating material in the figures is a single layer, some embodiments may employ multiple layers.

[0079] Next, a removal process can be applied to the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing, etch-back processes, combinations thereof, or similar processes can be employed. The planarization process exposes the nanostructure 55, such that the nanostructure 55 after planarization is substantially coplanar or flush with the upper surface of the insulating material. The insulating material can then be recessed to form shallow trench isolation regions 68. The insulating material can be recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent shallow trench isolation regions 68. An acceptable etching process can be used to recess the shallow trench isolation regions 68, such as an etching process that is selective to the insulating material and etches the insulating material at a rate greater than the rate at which the fins 66 and the nanostructure 55 are etched. For example, when the insulating material is an oxide, dilute hydrofluoric acid can be used. After the removal process, the upper surface of the shallow trench isolation region 68 can be a flat surface, a protruding surface, a recessed surface, or a combination thereof, as shown in the figures.

[0080] Figures 2 to 4The process described above is one example of how fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using a masking and epitaxial growth process. For example, a dielectric layer can be formed on the upper surface of the substrate 50, and etching can be performed through the dielectric layer to form trenches and expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trenches, causing the dielectric layer to be recessed, and the epitaxial structure to protrude from the dielectric layer to form fins 66 and / or nanostructures 55. The epitaxial structure may include the aforementioned interleaved semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments, the epitaxial structure is epitaxially grown, and the epitaxial growth material can be in-situ doped during growth to omit prior and / or subsequent implantation, but in-situ doping and implantation doping can be used in combination.

[0081] Furthermore, the first semiconductor layer 51 (and the final first nanostructure 52) in the p-type region 50P and the n-type region 50N described herein may comprise the same material, and the second semiconductor material 53 (and the final second nanostructure 54) in the p-type region 50P and the n-type region 50N may comprise the same material; this is for illustrative purposes only. In some embodiments, the first semiconductor layer 51 in the p-type region 50P and the n-type region 50N may comprise different materials. In some embodiments, the second semiconductor layer 53 in the p-type region 50P and the n-type region 50N may comprise different materials. In some embodiments, the first semiconductor layer 51 in the p-type region 50P and the n-type region 50N may comprise different materials, and the second semiconductor layer 53 in the p-type region 50P and the n-type region 50N may comprise different materials.

[0082] In addition Figure 4 Suitable wells (not shown) can be formed in the fins 66, nanostructures 55, and / or shallow trench isolation regions 68. In embodiments with different well morphologies, photoresist or other masks (not shown) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed on the fins 66, nanostructures 55, and shallow trench isolation regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology, and the patterning method can use acceptable photolithography technology. Once the photoresist is patterned, n-type impurities can be implanted into the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and their implantation concentration can be about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 The photoresist can be removed after injection, and the removal method can be an acceptable ashing process.

[0083] Before or after implantation into the p-type region 50P, photoresist or other masks (not shown) may be formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using spin coating technology, while the patterning method may employ acceptable photolithography techniques. Once the photoresist is patterned, p-type impurities can be implanted into the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like, and their implantation concentration may be approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 The photoresist can be removed after implantation, and the removal method can be an acceptable ashing process. After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth to omit implantation, but in-situ doping and implantation doping can be used in combination.

[0084] exist Figure 5 In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. For example, the dummy dielectric layer 70 may be silicon oxide, silicon nitride, a combination thereof, or the like, and its formation method may be deposition or thermal growth according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a masking layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70, and then planarized by methods such as chemical mechanical polishing. The masking layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material, and may be selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The deposition method for the dummy gate layer 72 may be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other techniques used for depositing selected materials. The dummy gate layer 72 can be composed of other materials that exhibit high etch selectivity relative to the etch process of the etched isolation region. For example, the mask layer 74 may include silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 may be formed on the n-type region 50N and the p-type region 50P. It is worth noting that the dummy dielectric layer 70 in the figures only covers the fins 66 and the nanostructures 55 and is for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that it covers the shallow trench isolation region 68 and extends between the dummy gate layer 72 and the shallow trench isolation region 68.

[0085] Figures 6A to 20CThese are some of the additional processes used to fabricate nanostructured field-effect transistor devices in some embodiments. Figures 6A to 20C The structure shown can be located in the n-type region 50N, the p-type region 50P, or both. Figures 6A to 6C In this process, a mask 78, a dummy gate 76, and a dummy gate dielectric layer 71 are formed. The dummy gate 76 and the dummy gate dielectric layer 71 can be considered together as a dummy gate structure. The mask layer 74 can be patterned using appropriate photolithography and etching processes (see...). Figure 5 A mask 78 is formed by etching. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 using a suitable etching process to form the dummy gate 76 and the dummy gate dielectric layer 71, respectively. The dummy gate 76 covers the individual channel regions of the fin 66 and the individual nanostructures 55 above it. The pattern of the mask 78 can be used to separate adjacent dummy gates 76. The length direction of the dummy gate 76 can also be substantially perpendicular to the length direction of the individual fins 66.

[0086] exist Figures 7A to 7C In this process, spacers 81 are formed. Spacers 81 can self-align with subsequently formed source / drain regions and protect the dummy gate dielectric layer 71 and dummy gate 76 during subsequent etching processes. Spacers 81 can be a single layer of one material or multiple sublayers of different materials with different etching rates. In some embodiments, spacers 81 comprise two sublayers of different materials with different etching rates, selected from silicon oxide, silicon nitride, silicon oxynitride, or the like. The spacer layer can be formed by thermal oxidation using a suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar processes, followed by patterning the spacer layer using a suitable etching process such as isotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching), or similar processes. The spacer layer can be formed on the upper surface of the shallow trench isolation region 68; the upper surface and sidewalls of the fins 66, nanostructures 55, and mask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric layer 71. After the etching process, spacers 81 may remain on the sidewalls of fins 66 and / or nanostructures 55 (e.g., Figure 7B As shown), and on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric layer 71 (as shown). Figure 7C (As shown).

[0087] In embodiments where spacer 81 comprises two sublayers of different materials, implantation for lightly doped source / drain regions (not shown) can be performed after the formation of the first sublayer and before the formation of the second sublayer. Figure 4Similar to the implantation described above, a mask, such as a photoresist, can be formed on the n-type region 50N, exposing the p-type region 50P. A suitable type of impurity (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration in the lightly doped source / drain regions can be approximately 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 Annealing can be used to repair injection damage and reactivate injected impurities.

[0088] exist Figures 8A to 8C In this structure, a first recess 86 is formed within the fin 66 and the nanostructure 55. The first recess 86 can extend through the first nanostructure 52 and the second nanostructure 54, and penetrate into the fin 66. For example... Figure 8B As shown, the upper surface of the shallow trench isolation region 68 (such as the upper surface of the fin 66) may be flush with the lower surface of the first recess 86. In some embodiments, the lower surface of the first recess 86 is lower than the upper surface of the shallow trench isolation region 68. The first recess 86 may be formed by using an anisotropic etching process such as reactive ion etching, neutral beam etching, or similar processes to etch the fin 66, the nanostructure 55, and the substrate 50. During the etching process of forming the first recess 86, the spacer 81 and the mask 78 may mask portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes may be used to etch each layer of the nanostructure 55 and / or the fin 66. A time-controlled etching process may stop etching after the first recess 86 reaches the desired depth.

[0089] exist Figures 9A to 9C In this process, the first nanostructure 52 is replaced with a first sacrificial layer 87 and a second sacrificial layer 89. Replacing the first nanostructure 52 with the first sacrificial layer 87 and the second sacrificial layer 89 prevents defects from forming on the surface of the second nanostructure 54 adjacent to the first nanostructure 52 during subsequent annealing processes. The method of replacing the first nanostructure 52 may include first removing the first nanostructure 52 via a suitable etching process, such as isotropic etching, using a first recess 86. The etching process may selectively remove material from the first nanostructure 52 without significantly removing material from the second nanostructure 54 or the semiconductor fin 66. In embodiments where the first nanostructure 52 comprises silicon-germanium and the second nanostructure 54 comprises silicon, the first nanostructure 52 may be removed by an etching process using tetramethylammonium hydroxide, ammonium hydroxide, or the like.

[0090] Next, a first sacrificial layer 87 and a second sacrificial layer 89 can be deposited to fill the space occupied by the first nanostructure 52 before it is removed. The first sacrificial layer 87 can be formed on the exposed upper and lower surfaces of the second nanostructure 54 and on the exposed upper surface of the fin 66, and can be formed by a suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar methods, followed by a suitable etching process such as anisotropic etching. The portion of the first sacrificial layer 87 formed on the exposed upper surfaces of the second nanostructure 54 and the fin 66 can be considered as a first portion of the first sacrificial layer 87. The portion of the first sacrificial layer 87 formed on the exposed lower surface of the second nanostructure 54 can be considered as a second portion of the first sacrificial layer 87. A gap may be present between the first portion of the first sacrificial layer 87 and the adjacent second portion of the first sacrificial layer 87. Next, a second sacrificial layer 89 is formed between the first portion of the first sacrificial layer 87 and the adjacent second portion of the first sacrificial layer 87, and the formation method can be a suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar process, followed by a suitable etching process such as anisotropic etching process.

[0091] The first sacrificial layer 87 and the second sacrificial layer 89 may comprise different materials and have different etching rates when exposed to the same etchant in subsequent etching processes, as detailed below. The first sacrificial layer 87 and the second sacrificial layer 89 may be selected from dielectric materials such as silicon oxide, aluminum oxide, silicon nitride, or the like. In some embodiments, the first sacrificial layer 87 comprises silicon oxide, and the second sacrificial layer 89 comprises aluminum oxide. In some embodiments, the first sacrificial layer 87 comprises aluminum oxide, and the second sacrificial layer 89 comprises silicon oxide. In some embodiments, the first sacrificial layer 87 comprises aluminum oxide, and the second sacrificial layer 89 comprises silicon nitride. In some embodiments, the first sacrificial layer 87 comprises silicon nitride, and the second sacrificial layer 89 comprises silicon oxide. In some embodiments, the first sacrificial layer 87 comprises silicon oxide, and the second sacrificial layer 89 comprises silicon nitride.

[0092] exist Figures 10A to 10C In this process, the first sacrificial layer 87 and the second sacrificial layer 89 are recessed to form a second recess 88, and then the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89 can be recessed from the sidewalls of the second nanostructure 54. Figure 10CIn the illustrated embodiment, the sidewalls of the second sacrificial layer 89 are more recessed than the sidewalls of the first and second portions of the first sacrificial layer 87. The shape and size of the first sacrificial layer 87 and the second sacrificial layer 89 can partially determine the shape and size of the subsequently formed inner spacers. The method of recessing the first sacrificial layer 87 and the second sacrificial layer 89 can be two separate selective etching processes. The first sacrificial layer 87 can be recessed before or after the second sacrificial layer 89 is recessed. In the selective etching process that selectively recesses the first sacrificial layer 87, the etching rate of the first sacrificial layer 87 is significantly higher than the etching rate of the second sacrificial layer 89. In the selective etching process that selectively recesses the second sacrificial layer 89, the etching rate of the second sacrificial layer 89 is significantly higher than the etching rate of the first sacrificial layer 87. The second nanostructure 54 and the fin 66 can remain substantially intact during the selective etching process. Figure 10C The first sacrificial layer 87 and the second sacrificial layer 89 shown are examples of straight sidewalls, while in other embodiments the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89 may be recessed or protruding.

[0093] In embodiments where the first sacrificial layer 87 comprises silicon oxide and the second sacrificial layer 89 comprises aluminum oxide, a first etching process (which may be dry etching using hydrofluoric acid, a mixture of hydrofluoric acid and ammonia, or the like as etchants) may be used to selectively recess the first sacrificial layer 87, and a second etching process (which may be wet etching using a mixture of hydrofluoric acid and a second acid, or the like as etchants) may be used to selectively recess the second sacrificial layer 89, with a process temperature of about 25°C to about 80°C. The second acid may be hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, acetic acid, or the like. The pH value of the mixture of hydrofluoric acid and the second acid may be about 1 to about 6. In embodiments where the first sacrificial layer 87 comprises aluminum oxide and the second sacrificial layer 89 comprises silicon oxide, a second etching process may be used to selectively recess the first sacrificial layer 87, and a first etching process may be used to selectively recess the second sacrificial layer 89.

[0094] In embodiments where the first sacrificial layer 87 comprises silicon nitride and the second sacrificial layer 89 comprises aluminum oxide, a first etching process may be used to selectively recess the first sacrificial layer 87, and a second, third, or fourth etching process may be used to selectively recess the second sacrificial layer 89. The third etching process may be a wet etching process using a mixture of sulfuric acid and hydrogen peroxide or the like as an etchant. The fourth etching process may be a wet etching process using a mixture of ammonium hydroxide and hydrogen peroxide or the like as an etchant. In embodiments where the first sacrificial layer 87 comprises aluminum oxide and the second sacrificial layer 89 comprises silicon nitride, a second, third, or fourth etching process may be used to selectively recess the first sacrificial layer 87, and a first etching process may be used to selectively recess the second sacrificial layer 89.

[0095] In embodiments where the first sacrificial layer 87 comprises silicon nitride and the second sacrificial layer 89 comprises silicon oxide, a second etching process or a fifth etching process (which may be a wet etching process using phosphoric acid or the like as an etchant) may be used to selectively recess the first sacrificial layer 87, and a first etching process or a sixth etching process (which may be a wet etching process using hydrofluoric acid or the like as an etchant) may be used to selectively recess the second sacrificial layer 89. In embodiments where the first sacrificial layer 87 comprises silicon oxide and the second sacrificial layer 89 comprises silicon nitride, a first etching process or a sixth etching process may be used to selectively recess the first sacrificial layer 87, and a second etching process or a fifth etching process may be used to selectively recess the second sacrificial layer 89.

[0096] exist Figures 11A to 11C An inner spacer 90 is formed in the second recess 88. The inner spacer 90 provides electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure. The inner spacer 90 may extend along the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89. The inner spacer 90 may contact exposed portions of the upper and lower surfaces of the second nanostructure 54. The shape and size of the inner spacer 90 may depend in part on the shape and size of the first sacrificial layer 87 and the second sacrificial layer 89. Figure 11C In the illustrated embodiment, the inner spacer 90 is T-shaped, with its protruding portion contacting the second sacrificial layer 89. The wavy sidewalls of the inner spacer 90 may contact the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89. The longest portion of the inner spacer 90 may have a length L1. The length L2 of the protruding portion of the inner spacer 90 may be between about 0.5 nm and about 5 nm. The ratio of length L2 to length L1 may be between about 20% and about 80%. The widest portion of the inner spacer 90 may have a width W1. The width W2 of the protruding portion of the inner spacer 90 may be between about 0.5 nm and about 5 nm. The ratio of width W2 to width W1 may be between about 20% and about 80%. The shape and size of the inner spacer 90 provide sufficient electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, and reduce channel resistance as detailed below.

[0097] The inner spacer 90 can be formed by depositing an inner spacer layer (not shown) on... Figures 10A to 10COn the structure shown, the inner spacer layer is then etched. The deposition method for the inner spacer layer can be a suitable deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The material comprising the inner spacer layer may be different from the materials of the first sacrificial layer 87 and the second sacrificial layer 89, and has high etch selectivity relative to the first sacrificial layer 87 and the second sacrificial layer 89. The inner spacer layer may include a dielectric material such as silicon oxycarbonate or the like. The dielectric constant of the material of the inner spacer layer may be less than about 3.5. The inner spacer layer may be etched to form the inner spacer 90, and the etching method may be anisotropic etching processes such as reactive ion etching, neutral beam etching, or a similar process. Figure 11C In the example shown, the outer sidewall of the inner spacer 90 is flat and flush with the sidewall of the second nanostructure 54. In some embodiments, the outer sidewall of the inner spacer 90 may be recessed into the sidewall of the second nanostructure 54, or protrude from or extend beyond the sidewall of the second nanostructure 54.

[0098] exist Figures 12A to 12C In this configuration, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. Figure 12C As shown, the epitaxial source / drain regions 92 are formed in the first recess 86, such that the dummy gates 76 are each located between individual adjacent epitaxial source / drain regions 92.

[0099] The method of forming the epitaxial source / drain region 92 in the n-type region 50N (such as an n-type metal-oxide-semiconductor region) may be to mask the p-type region 50P (such as a p-type metal-oxide-semiconductor region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may comprise a material to which tensile stress is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface protruding from an individual upper surface of the second nanostructure 54 and may have a crystal plane.

[0100] The method of forming the epitaxial source / drain region 92 in the p-type region 50P (such as a p-type metal-oxide-semiconductor region) may be to mask the n-type region 50N (such as an n-type metal-oxide-semiconductor region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may comprise any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may comprise a material to which compressive stress is applied to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 may have a surface raised from an individual upper surface of the second nanostructure 54 and may have a crystal plane.

[0101] Dopant can be implanted into the epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, which can be similar to the process described above used to form lightly doped source / drain regions. An annealing process can then be performed. The impurity concentration of the source / drain region can be between approximately 1 x 10⁻⁶. 19 atoms / cm 3 To approximately 1x10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0102] The epitaxial growth process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P results in a crystal plane on the upper surface of the epitaxial source / drain regions 92, which extends laterally outward beyond the sidewalls of the second nanostructure 54. In some embodiments, these crystal planes cause adjacent epitaxial source / drain regions 92 of the same nanostructure field-effect transistor to merge, such as... Figure 12B As shown. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as... Figure 12D As shown.

[0103] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes a first pad layer 92A located on the sidewall of the second nanostructure 54, a second pad layer 92B located on the first pad layer 92A, and a fill layer 92C located on the second pad layer 92B, such as... Figure 12C As shown. The first pad layer 92A, the second pad layer 92B, and the fill layer 92C can be composed of different semiconductor materials and / or have different dopant concentrations. The first pad layer 92A can be grown first, the second pad layer 92B can be grown on the first pad layer 92A, and the fill layer 92C can be grown on the second pad layer 92B.

[0104] exist Figures 13A to 13C In the middle, the first interlayer dielectric layer 96 was deposited. Figures 12A to 12C The structure shown. The first interlayer dielectric layer 96 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer 94 is located between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, the mask 78, and the spacer 81. The contact etch stop layer 94 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and its etch rate is different from the etch rate of the material of the upper first interlayer dielectric layer 96.

[0105] exist Figures 14A to 14C In this process, a planarization process, such as chemical mechanical polishing, can be performed to make the upper surface of the first interlayer dielectric layer 96 flush with the upper surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as portions of the spacers 81 along the sidewalls of the mask 78. After the planarization process, the dummy gate 76, the spacers 81, and the upper surface of the first interlayer dielectric layer 96 are flush (in process variations). In summary, the upper surface of the dummy gate 76 can be exposed from the first interlayer dielectric layer 96. In some embodiments, the mask 78 may be retained, and in this example, the planarization process makes the upper surface of the first interlayer dielectric layer 96 flush with the upper surfaces of the mask 78 and the spacers 81.

[0106] exist Figures 15A to 15C In this process, a dummy gate 76 and a dummy gate dielectric layer 71 are removed by one or more etching processes to form a third recess 98. In some embodiments, the dummy gate 76 and the dummy gate dielectric layer 71 are removed by an isotropic dry etching process. For example, the etching process may include a dry etching process in which the etchant used selectively etches the dummy gate 76 and the dummy gate dielectric layer 71 at a rate greater than the rate at which the first interlayer dielectric layer 96 and / or the spacer 81 are etched. The third recess 98 exposes a portion of the second nanostructure 54 and / or is located on a portion of the second nanostructure 54, which may serve as a channel region for a subsequently completed nanostructure field-effect transistor. The portion of the second nanostructure 54 may serve as a channel region and may be located between adjacent pairs of epitaxial source / drain regions 92. During the etching process, the dummy gate dielectric layer 71 may serve as an etch stop layer when the dummy gate 76 is removed, and the dummy gate dielectric layer 71 may be removed after the dummy gate 76 is removed.

[0107] exist Figures 16A to 16CIn the process of removing the first sacrificial layer 87 and the second sacrificial layer 89, a third recess 98 can be extended. The first sacrificial layer 87 and the second sacrificial layer 89 can be removed by two separate selective etching processes, which can be combined with... Figures 10A to 10C The selective etching process used to recess the first sacrificial layer 87 and the second sacrificial layer 89 is the same as or similar to that described above. The second nanostructure 54, fins 66, and inner spacers 90 remain substantially intact during selective etching. Figures 16A to 16C In the illustrated embodiment, the first sacrificial layer 87 and the second sacrificial layer 89 are completely removed. In other embodiments, the first sacrificial layer 87 and the second sacrificial layer 89 are partially removed.

[0108] exist Figures 17A to 17C In this configuration, gate dielectric layer 100 and gate 102 are formed in a third recess 98. Gate dielectric layer 100 and gate 102 can fill the space occupied by the first sacrificial layer 87 and the second sacrificial layer 89 before they are removed. Gate dielectric layer 100 can be compliantly deposited in the third recess 98, on the upper surface, sidewalls, and lower surface of the second nanostructure 54, and on the sidewalls of the inner spacer 90. Gate dielectric layer 100 can also be deposited on the first interlayer dielectric layer 96, the contact etch stop layer 94, the spacer 81, and the shallow trench isolation region 68. Gate dielectric layer 100 may include one or more dielectric layers, such as silicon oxide, metal oxide, the like, or a combination thereof. The gate dielectric layer 100 can be formed by a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, or a similar process. Gate 102 can be deposited on gate dielectric layer 100 and fill the remainder of the third recess 98. The gate 102 may include conductive materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, the like, or combinations thereof. Figures 17A to 17C The single-layer gate 102 shown is an example, and the gate 102 may include any number of pad layers, any number of work function adjustment layers, and fill material.

[0109] Gate dielectric layers 100 can be formed simultaneously in the n-type region 50N and the p-type region 50P, such that the gate dielectric layers 100 in each region are composed of the same material. Gates 102 can be formed simultaneously, such that the gates 102 in each region are composed of the same material. In some embodiments, the formation method of the gate dielectric layer 100 in each region can be a separate process, such that the gate dielectric layer 100 is composed of different materials and / or has a different number of layers; and / or the formation method of the gate 102 in each region can be a separate process, such that the gate 102 is composed of different materials and / or has a different number of layers. When using a separate process, various masking steps can be used to mask and expose suitable areas.

[0110] After filling the third recess 98, a planarization process such as chemical mechanical polishing can be performed to remove excess portions of the gate dielectric layer 100 and gate 102 above the upper surface of the first interlayer dielectric layer 96. The remaining portions of gate 102 and gate dielectric layer 100 can be considered together as the gate structure. The shape and size of the gate structure depend in part on the shape and size of the inner spacer 90. Figure 17C In the illustrated embodiment, the inner spacer 90 is T-shaped and has wavy sidewalls that contact the corresponding wavy sidewalls of the gate structure. The protruding portion of the inner spacer 90 can protrude from the epitaxial source / drain region 92 toward the gate structure. The shape and size of the inner spacer 90 separate the epitaxial source / drain region 92 from the gate structure and provide sufficient electrical insulation between the epitaxial source / drain region 92 and the gate structure. This reduces or eliminates leakage current between the epitaxial source / drain region 92 and the gate structure. The shape and size of the gate structure depend in part on the shape and size of the inner spacer 90, which can reduce resistance in the channel region (such as the second nanostructure 54). This improves the performance and reliability of the subsequently formed semiconductor device.

[0111] Taking the gate structure between the second nanostructure 54A and the second nanostructure 54B as an example, the first protrusion and the second protrusion of the gate structure protrude toward the inner spacer 90 on each side of the gate structure. A recess may be located between the first protrusion and the second protrusion of the gate structure on each side of the gate structure, and the corresponding protrusion of the inner spacer 90 may protrude into the recess. In this way, on each side of the gate structure, the protrusion of the inner spacer 90 may be located between the first protrusion and the second protrusion of the gate structure, and the protrusion of the inner spacer 90 may contact the lower surface of the first protrusion and the upper surface of the second protrusion of the gate structure. On each side of the gate structure, the protruding portion of the inner spacer 90 may be located between the second nanostructure 54A and the first protruding portion of the gate structure, the protruding portion of the inner spacer 90 may be located between the second nanostructure 54B and the second protruding portion of the gate structure, the first protruding portion of the gate structure may be located between the second nanostructure 54B and the protruding portion of the inner spacer 90, and the second protruding portion of the gate structure may be located between the second nanostructure 54A and the protruding portion of the inner spacer 90.

[0112] exist Figures 18A to 18CIn the process, a gate structure (containing a gate dielectric layer 100 and a corresponding upper gate 102) is recessed to form a gate mask 104 within the recess, and a second interlayer dielectric layer 106 is formed on the first interlayer dielectric layer 96 and the gate mask 104. The recess can be formed directly above the gate structure and between the two sides of the spacer 81. The gate mask 104 may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like. A planarization process can be performed to remove excess material from the gate mask 104. The second interlayer dielectric layer 106 may be composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or similar methods.

[0113] exist Figures 19A to 19C In this process, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a fourth recess 108, which may expose the epitaxial source / drain region 92 and / or some gate structure surfaces. The fourth recess 108 can be formed by etching, employing anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar methods. In some embodiments, a first etching process can be used to make the fourth recess 108 pass through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96, a second etching process can be used to make the fourth recess 108 pass through the gate mask 104, and then a third etching process can be used to make the fourth recess 108 pass through the contact etch stop layer 94. A patterned mask, such as photoresist, can be formed and patterned on the second interlayer dielectric layer 106 to shield portions of the second interlayer dielectric layer 106 from the first and second etching processes. In some embodiments, the etching process may be over-etched so that the fourth recess 108 extends into the epitaxial source / drain region 92 and / or some gate structures, and the bottom of the fourth recess 108 may be flush with (e.g. at the same height or at the same distance from the substrate 50) or lower than (e.g. closer to the substrate 50) the epitaxial source / drain region 92 and / or some gate structures.

[0114] After the fourth recess 108 is formed, a first silicide region 110 can be formed on the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or alloys thereof) on the exposed portion of the epitaxial source / drain region 92, and the metal can react with the semiconductor material (such as silicon, silicon-germanium, or germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region. A thermal annealing process is then performed to form the first silicide region. Unreacted portions of the deposited metal are then removed by methods such as etching. Although the first silicide 110 is considered a silicide region, it can also be a germanide region or a silicon-germanium region (such as a region containing both silicide and germanide).

[0115] exist Figures 20A to 20C In the middle, the source / drain contact 112 and the gate contact 114 (which can also be regarded as conductive contact) are formed in the fourth recess 108. Figures 20A to 20C The structure shown can be considered as a semiconductor device 120. The source / drain contact 112 and gate contact 114 may each include one or more layers such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, the source / drain contact 112 and gate contact 114 each include a barrier layer and a conductive material, which can be connected to the underlying conductive structure (such as gate 102 and / or the first silicide region 110). Gate contact 114 is electrically connected to gate 102, while source / drain contact 112 is electrically connected to the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes such as chemical mechanical polishing may be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0116] In some embodiments, Figures 21A to 24C The accompanying diagram illustrates an intermediate process for manufacturing semiconductor devices such as nanostructured transistors. Figure 21A , Figure 22A , Figure 23A and Figure 24A The cross-sectional view shown is along Figure 1 The reference section A-A' is shown. Figure 21B , Figure 22B , Figure 23B and Figure 24B The cross-sectional view shown is along Figure 1 The reference section B-B' is shown. Figure 21C , Figure 22C , Figure 23C and Figure 24C The cross-sectional view shown is along Figure 1 The reference section C-C' is shown.

[0117] Figures 21A to 21C The structure shown is similar to Figures 10A to 10C The structure shown is similar, and it is essentially similar to... Figures 1 to 9C The diagram shows the structure formed by the process, while similar labels are used to indicate similar structures formed by similar processes. Figures 21A to 21C In this process, the first sacrificial layer 87 and the second sacrificial layer 89 are recessed to form a second recess 88, and then the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89 can be recessed from the sidewalls of the second nanostructure 54. Figure 21C In the illustrated embodiment, the sidewalls of the first and second portions of the first sacrificial layer 87 may be more recessed than the sidewalls of the second sacrificial layer 89. The first sacrificial layer 87 and the second sacrificial layer 89 can be recessed by two separate selective etching processes, which can be combined with… Figures 10A to 10C The selective etching process used to recess the first sacrificial layer 87 and the second sacrificial layer 89 is the same as or similar to that described above. The first sacrificial layer 87 can be recessed before or after the second sacrificial layer 89 is recessed. During the selective etching process, the second nanostructure 54 and the fin 66 can remain substantially intact. In one example, the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89 shown in FIG. 21 are flat. In other embodiments, the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89 may be recessed or protruding.

[0118] exist Figures 22A to 22C In the second recess 88, an inner spacer 90 is formed. The inner spacer 90 provides electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure. The inner spacer 90 may extend along the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89. The inner spacer 90 may contact exposed portions of the upper and lower surfaces of the second nanostructure 54. The shape and size of the inner spacer may depend in part on the shape and size of the first sacrificial layer 87 and the second sacrificial layer 89. Figure 22C In the illustrated embodiment, the inner spacer 90 is U-shaped, with its protruding portion contacting the first and second portions of the first sacrificial layer 87. The inner spacer 90 may have wavy sidewalls to contact the sidewalls of the first sacrificial layer 87 and the second sacrificial layer 89. The longest portion of the inner spacer 90 may have a length L3. The length L4 of the protruding portion of the inner spacer 90 may be from about 0.5 nm to about 5 nm. The ratio of length L4 to length L3 may be from about 20% to about 80%. The widest portion of the inner spacer 90 may have a width W3. The width W4 of the protruding portion of the inner spacer 90 may be from about 0.5 nm to about 5 nm. The ratio of width W4 to width W3 may be from about 20% to about 80%. The shape and size of the inner spacer 90 provide sufficient electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, and reduce channel resistance as detailed below.

[0119] Figures 23A to 23C The structure shown is similar to Figures 17A to 17C The structure shown is similar, and it is essentially similar to... Figures 12A to 16C The diagram shows the structure formed by the process, while similar labels are used to indicate similar structures formed by similar processes. Figures 23A to 23C In this configuration, gate dielectric layer 100 and gate 102 are formed in the third recess 98. Gate dielectric layer 100 and gate 102 can fill the space occupied by the first sacrificial layer 87 and the second sacrificial layer 89 before they are removed. The method of forming gate dielectric layer 100 and gate 102 can be combined with... Figures 17A to 17C The methods described above are the same or similar. Gate 102 and gate dielectric layer 100 can be considered together as a gate structure.

[0120] The shape and size of the gate structure depend at least in part on the shape and size of the inner spacer 90. Figure 23C In the illustrated embodiment, the inner spacer 90 is U-shaped, with its wavy sidewalls contacting the corresponding wavy sidewalls of the gate structure. The protruding portion of the inner spacer 90 may protrude from the epitaxial source / drain structure 92 toward the gate structure. The shape and size of the inner spacer 90 separate the epitaxial source / drain region 92 from the gate structure and provide sufficient electrical insulation between the epitaxial source / drain region 92 and the gate structure, thereby reducing or eliminating leakage current between the epitaxial source / drain region 92 and the gate structure. The shape and size of this gate structure, partly dependent on the shape and size of the inner spacer 90, can reduce resistance in the channel region (such as the second nanostructure 54). This improves the performance and reliability of the subsequently formed semiconductor device.

[0121] Taking the gate structure between the second nanostructure 54A and the second nanostructure 54B as an example, the gate structure may include a protruding portion protruding from the inner spacer 90 on each side of the gate structure. A recess may be located between the first and second protruding portions of the inner spacer 90 on each side of the gate structure, and the corresponding protruding portion of the gate structure may protrude into the recess. Thus, on each side of the gate structure, the protruding portion of the gate structure may be located between the first and second protruding portions of the inner spacer 90, and the protruding portion of the gate structure may contact the lower surface of the first protruding portion of the inner spacer 90 and the upper surface of the second protruding portion of the inner spacer 90. On each side of the gate structure, the second protrusion of the inner spacer 90 may be located between the second nanostructure 54A and the protrusion of the gate structure, while the first protrusion of the inner spacer 90 may be located between the second nanostructure 54B and the protrusion of the gate structure, the protrusion of the gate structure may be located between the second nanostructure 54B and the second protrusion of the inner spacer 90, and the protrusion of the gate structure may be located between the second nanostructure 54A and the first protrusion of the inner spacer 90.

[0122] Figures 24A to 24CThe structure shown is similar to Figures 20A to 20C The structure shown is similar, and it is essentially similar to... Figures 18A to 19C The diagram shows the structure formed by the process, while similar labels are used to indicate similar structures formed by similar processes. Figures 24A to 24C The structure shown can be considered as a semiconductor device 130. In Figures 24A to 24C In the fourth recess 108, the source / drain contact 112 and the gate contact 114 (which can also be considered as conductive contacts) are formed. The method for forming the source / drain contact 112 and the gate contact 114 can be combined with... Figures 20A to 20C The methods described above are the same or similar.

[0123] This embodiment of the invention offers several advantages. By forming and recessing the first sacrificial layer 87 and the second sacrificial layer 89, an inner spacer 90 of a specific shape and size can be formed, along with a gate structure. The inner spacer 90 of this shape and size provides sufficient electrical insulation between the epitaxial source / drain region 92 and the gate structure, thereby reducing or eliminating leakage current between the epitaxial source / drain region 92 and the gate structure. The gate structure of this shape and size can reduce resistance in the channel region (such as the second nanostructure 54). This, in turn, improves the performance and reliability of the semiconductor device.

[0124] In one embodiment, the semiconductor device includes a first nanostructure and a second nanostructure; a gate structure located between the first nanostructure and the second nanostructure; a source / drain region along the sidewalls of the first nanostructure and the second nanostructure; and a spacer layer located between the source / drain region and the gate structure, wherein a first portion of the spacer layer protrudes from the source / drain region toward the gate structure, and wherein the first portion of the spacer layer protrudes into a recess in the gate structure. In one embodiment, the first portion of the spacer layer is located between a first portion of the gate structure and a second portion of the gate structure. In one embodiment, the first portion of the spacer layer contacts the upper surface of the first portion of the gate structure and the lower surface of the second portion of the gate structure. In one embodiment, the first portion of the gate structure is located between the first portion of the spacer layer and the first nanostructure, and wherein the second portion of the gate structure is located between the first portion of the spacer layer and the second nanostructure. In one embodiment, the second portion of the spacer layer contacts the first nanostructure and the second nanostructure. In one embodiment, the spacer layer is T-shaped. In one embodiment, the wavy sidewalls of the spacer layer contact the gate structure. In one embodiment, the length of the first portion of the spacer layer is between about 0.5 nm and about 5 nm. In one embodiment, the ratio of the length of the first portion of the spacer layer to the length of the longest portion of the spacer layer is between about 20% and about 80%. In one embodiment, the width of the first portion of the spacer layer is between about 0.5 nm and about 5 nm.

[0125] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure and a second nanostructure on a fin; forming a first sacrificial layer, wherein a first portion of the first sacrificial layer is located on the first nanostructure, and a second portion of the first sacrificial layer is located on the second nanostructure; forming a second sacrificial layer between the first portion and the second portion of the first sacrificial layer; forming a spacer layer on the first portion, the second portion, and the second sacrificial layer, wherein the spacer layer is T-shaped or U-shaped; forming source / drain regions on the first nanostructure, the second nanostructure, and the spacer layer; removing the first and second sacrificial layers to form a first opening; and forming a gate structure in the first opening. In one embodiment, the first portion of the spacer layer protrudes into a recess in the gate structure, and wherein the first portion of the spacer layer contacts the lower surface of the first portion of the gate structure and the upper surface of the second portion of the gate structure. In one embodiment, the first portion of the gate structure protrudes into a recess in the spacer layer, and wherein the first portion of the gate structure contacts the lower surface of the first portion of the spacer layer and the upper surface of the second portion of the spacer layer. In one embodiment, the wavy sidewalls of the gate structure contact the spacer layer. In one embodiment, the first sacrificial layer comprises aluminum oxide and the second sacrificial layer comprises silicon oxide. In one embodiment, the first sacrificial layer comprises silicon oxide and the second sacrificial layer comprises aluminum oxide.

[0126] In one embodiment, a method for forming a semiconductor device includes: forming a first nanostructure and a second nanostructure on a fin; forming a first sacrificial layer, wherein a first portion of the first sacrificial layer is located on an upper surface of the first nanostructure, and a second portion of the first sacrificial layer is located on a lower surface of the second nanostructure; forming a second sacrificial layer between the first portion and the second portion of the first sacrificial layer; recessing the first and second sacrificial layers; forming a spacer layer on the sidewalls of the first portion, the second portion, and the second sacrificial layer of the first sacrificial layer; and forming source / drain regions on the sidewalls of the first nanostructure, the second nanostructure, and the spacer layer. In one embodiment, the first sacrificial layer includes a first dielectric material, the second sacrificial layer includes a second dielectric material, and the second dielectric material is different from the first dielectric material. In one embodiment, the step of recessing the first and second sacrificial layers includes: recessing the first sacrificial layer using a first etching process, wherein the removal rate of the first sacrificial layer is greater than the removal rate of the second sacrificial layer; and recessing the second sacrificial layer using a second etching process, wherein the removal rate of the second sacrificial layer is greater than the removal rate of the first sacrificial layer. In one embodiment, after the first sacrificial layer and the second sacrificial layer are recessed, the sidewalls of the second sacrificial layer are more recessed than the sidewalls of the first portion and the second portion of the first sacrificial layer. In one embodiment, after the first sacrificial layer and the second sacrificial layer are recessed, the sidewalls of the first portion and the second portion of the first sacrificial layer are more recessed than the sidewalls of the second sacrificial layer. In one embodiment, the spacer layer is T-shaped or U-shaped. In one embodiment, the method further includes removing the first sacrificial layer and the second sacrificial layer to form a first opening; and forming a gate structure in the first opening.

[0127] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A first nanostructure and a second nanostructure; A gate structure is located between the first nanostructure and the second nanostructure; A source / drain region is formed along the sidewalls of the first nanostructure and the second nanostructure. as well as A spacer layer is located between the source / drain region and the gate structure, wherein a first portion of the spacer layer protrudes from the source / drain region toward the gate structure, and wherein the first portion of the spacer layer protrudes into a recess in the gate structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The first portion of the spacer layer is located between the first portion of the gate structure and the second portion of the gate structure.

3. The semiconductor device as claimed in claim 2, characterized in that, The first portion of the spacer layer contacts the upper surface of the first portion of the gate structure and the lower surface of the second portion of the gate structure.

4. The semiconductor device as claimed in claim 2, characterized in that, The first portion of the gate structure is located between the first portion of the spacer layer and the first nanostructure, and the second portion of the gate structure is located between the first portion of the spacer layer and the second nanostructure.

5. The semiconductor device as claimed in claim 1, characterized in that, The second portion of the spacer layer contacts the first nanostructure and the second nanostructure.

6. The semiconductor device as claimed in claim 1, characterized in that, The spacer layer is T-shaped.

7. The semiconductor device as claimed in claim 1, characterized in that, The wavy sidewalls of the spacer layer contact the gate structure.

8. The semiconductor device as claimed in claim 1, characterized in that, The length of the first portion of the spacer layer is between 0.5 nm and 5 nm.

9. The semiconductor device as claimed in claim 1, characterized in that, The length of the first portion of the spacer layer is in the ratio of 20% to about 80% of the length of the longest portion of the spacer layer.

10. The semiconductor device as claimed in claim 1, characterized in that, The width of the first portion of the spacer layer is between 0.5 nm and 5 nm.

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