A gallium nitride monolithic integrated power module

Abstract

This invention discloses a gallium nitride monolithic integrated power module, relating to the field of semiconductor technology. It includes a substrate layer, an epitaxial layer above the substrate layer, and phase-isolated SBD active regions and HEMT active regions on the epitaxial layer. An SBD device is disposed within the SBD active region, and a HEMT device is disposed within the HEMT active region. Both the SBD and HEMT devices employ a p-GaN layer with a variable doping structure, and the anode of the SBD device and the drain of the HEMT device are connected by a wire. This invention solves the technical problems of existing devices, such as easy gate leakage, high drain peak electric field, low breakdown voltage, susceptibility to current collapse effect, high forward voltage drop, poor reverse recovery characteristics, high peak electric field, large leakage current, and still relatively large parasitic inductance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a gallium nitride monolithic integrated power module. Background Technology

[0002] As power electronic devices evolve towards higher frequencies and higher power densities, power conversion systems place higher demands on the integration and performance of core components. In typical power factor correction (PFC) circuits and DC-DC converters, gallium nitride high electron mobility transistors (GaN HEMTs) are gradually replacing traditional silicon-based power devices due to their excellent switching characteristics (such as high electron mobility and low on-resistance).

[0003] However, existing GaN HEMTs still require the use of external diodes. This discrete architecture still faces several technical bottlenecks. For example, the interconnection between discrete components typically requires PCB traces, which introduces significant parasitic inductance (usually exceeding 5nH), leading to severe voltage overshoot and ringing at high frequencies, and also increases electromagnetic interference (EMI) issues. Secondly, the discrete component layout results in dispersed heat flow paths, easily forming localized hotspots during high-power operation, affecting system reliability. Furthermore, the independent packaging of each component results in a large space requirement in practical applications, making it difficult to meet the miniaturization and integration demands of modern electronic devices.

[0004] To address this, patent document CN107845630A proposes a GaN-based monolithically integrated half-bridge circuit. This circuit integrates two enhancement-mode GaN HEMTs and GaN-based diodes onto the same chip module to reduce parasitic inductance, increase the switching speed of the switching transistors, and thus reduce the switching power consumption. However, careful analysis reveals that the GaN HEMTs and GaN-based diodes in this circuit are arranged laterally, resulting in a longer device length and a still relatively large parasitic inductance.

[0005] Furthermore, the concentration of the p-GaN layer in this circuit is constant, and the p-GaN layer in the GaN HEMT and the p-GaN layer in the GaN-based diode are completely covered by the gate and anode, respectively.

[0006] For GaN HEMT devices, the p-GaN layer is completely covered by the gate metal, forming an ohmic contact rather than a Schottky contact. This makes the device prone to gate tunneling leakage under high voltage. Furthermore, the p-GaN layer not only causes the electric field to concentrate at the drain edge, easily leading to premature breakdown, but also makes it prone to capturing carriers during high-voltage switching, resulting in an increase in dynamic on-resistance. Therefore, in practical applications, these devices present technical problems such as easy gate leakage, high peak drain electric field, low breakdown voltage, and susceptibility to current collapse effects.

[0007] For GaN-based diodes, the anode directly covers the entire p-GaN layer, failing to optimize hole injection efficiency and leading to a higher forward voltage drop. Furthermore, the uniform doping of the p-GaN layer results in slow depletion region expansion under reverse bias, a large reverse recovery charge (Qrr), and a significant tail current. This also makes it difficult to effectively suppress the peak electric field at the Schottky junction edge, making tunneling leakage more likely. Therefore, in practical applications, these diodes suffer from technical problems such as high forward voltage drop, poor reverse recovery characteristics, high peak electric field, and large leakage current.

[0008] Therefore, it is necessary to provide a new technology to solve the above-mentioned technical problems. Utility Model Content

[0009] This invention addresses the shortcomings and defects of the existing technologies by proposing a gallium nitride monolithic integrated power module. It aims to solve the technical problems of existing GaN HEMTs and GaN-based diode integrated devices, such as easy gate leakage, high drain peak electric field, low breakdown voltage, easy current collapse effect, high forward voltage drop, poor reverse recovery characteristics, high electric field peak, large leakage current, and still large parasitic inductance.

[0010] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0011] A gallium nitride monolithic integrated power module includes a substrate layer, an epitaxial layer disposed above the substrate layer, and phase-isolated SBD active regions and HEMT active regions disposed on the epitaxial layer. An SBD device is disposed within the SBD active region, and a HEMT device is disposed within the HEMT active region.

[0012] The SBD device includes a cathode, an anode, and a p-GaN layer. The cathode and anode are located at the front and rear ends of the active region of the SBD, respectively. The p-GaN layer includes an integrally formed control section and a suppression section. The thickness of the control section is greater than the thickness of the suppression section, so that the p-GaN layer forms a variable doping structure. The control section forms an ohmic contact with the anode. The anode is provided with a control section that extends towards the cathode and covers part of the control section. The control section forms an ohmic contact with the p-GaN layer.

[0013] The HEMT device includes a source, a drain, a gate, and a p-GaN layer. The source and drain are located at the front and rear ends of the HEMT active region, respectively, and both the source and drain form ohmic contacts with the epitaxial layer. The p-GaN layer and the gate are located between the source and drain. The p-GaN layer includes an integrally formed enhancement section and an optimization section. The thickness of the enhancement section is greater than the thickness of the optimization section, so that the p-GaN layer forms a variable doping structure. The gate covers part of the enhancement section and forms a Schottky contact with the enhancement section.

[0014] The anode of the SBD device is connected to the drain of the HEMT device via a wire.

[0015] Both the SBD device and the HEMT device include an insulating dielectric layer. In the SBD device, the insulating dielectric layer is located between the cathode and the anode, and simultaneously covers the control section, the regulation section, the suppression section, and the epitaxial layer. In the HEMT device, the insulating dielectric layer is located between the source and the drain, and simultaneously covers the gate, the enhancement section, the optimization section, and the epitaxial layer.

[0016] The thickness of the control section is 90-100 nm, and the thickness of the suppression section is 45-50 nm.

[0017] The thickness of the reinforcing part is 90-100 nm, and the thickness of the optimizing part is 45-50 nm.

[0018] The epitaxial layer includes a GaN buffer layer, a GaN channel layer, an AlN nucleation layer, and an AlGaN barrier layer, which are sequentially fixed above the substrate. The SBD active region and the HEMT active region are both arranged along the front-back direction of the substrate and are located between the GaN channel layer and the AlGaN barrier layer.

[0019] An isolation region is formed on the epitaxial layer from the AlGaN barrier layer to the GaN channel layer by ion implantation, and the SBD active region and the HEMT active region are isolated by the isolation region.

[0020] The substrate is a silicon substrate, a SiC substrate, or a sapphire substrate, with a thickness of 800-1200 μm, a GaN buffer layer with a thickness of 1.8-2.2 μm, a GaN channel layer with a thickness of 240-280 nm, an AlN nucleation layer with a thickness of 0.4-0.6 nm, and an AlGaN barrier layer with a thickness of 18-22 nm.

[0021] In the SBD device, a cathode field plate extending towards the anode is integrally formed on the upper part of the cathode, and an anode field plate extending towards the cathode is integrally formed on the upper part of the anode. The cathode field plate and the anode field plate are isolated by an insulating dielectric layer, and the upper surfaces of the cathode field plate, the anode field plate, and the insulating dielectric layer are all located on the same plane.

[0022] In the HEMT device, a source field plate extending towards the drain is integrally formed on the upper part of the source, and a drain field plate extending towards the source is integrally formed on the upper part of the drain. The source field plates are isolated from each other by an insulating dielectric layer, and the upper surface of the source field plate, the upper surface of the source field plate, and the upper surface of the insulating dielectric layer are all located on the same plane.

[0023] The integrated power module also includes an insulating housing, in which the substrate, epitaxial layer, SBD device, and HEMT device are all encapsulated.

[0024] Compared with the prior art, the beneficial effects of this utility model are as follows:

[0025] 1. This utility model adopts a structure in which SBD active region and HEMT active region are longitudinally spaced on the epitaxial layer, and SBD device and HEMT device are longitudinally integrated (SBD device and HEMT device are arranged along the front and back of the substrate). Compared with the prior art, this structure can effectively reduce the length of the module and further compress the parasitic inductance of electrode interconnection to <1nH, thereby effectively reducing the switching power consumption of the module.

[0026] Furthermore, the design of SBD devices sharing the substrate and epitaxial layer with HEMT devices can further improve the power density of the module while reducing the module size. Moreover, the process flow is fully compatible with standard p-GaN-based HEMT devices, improving the tape-out yield by 30% and reducing the manufacturing cost by 25%.

[0027] Furthermore, the variable-doped p-GaN layer in SBD devices includes a control section and a suppression section. The control section regulates reverse recovery characteristics and reduces forward voltage drop, while the suppression section suppresses electric field peaks and reduces leakage current. Similarly, the variable-doped p-GaN layer in HEMT devices includes an enhancement section and an optimization section. The enhancement section enhances the HEMT device and suppresses gate leakage, while the optimization section reduces the drain peak electric field, optimizes breakdown voltage, and reduces current collapse effects. By employing variable-doped p-GaN layers in both SBD and HEMT devices, the technical problems of easy gate leakage, high drain peak electric field, low breakdown voltage, susceptibility to current collapse effects, high forward voltage drop, poor reverse recovery characteristics, high electric field peaks, and large leakage current can be effectively solved.

[0028] 2. The insulating dielectric layer in this invention, through its full-coverage design, can block surface leakage current and carrier trapping, reducing dynamic resistance fluctuation to <5% and leakage current. Simultaneously, the insulating dielectric layer can work in conjunction with the field plate to achieve a uniform electric field distribution, reducing the peak electric field and improving the breakdown voltage. The insulating dielectric layer can also seal and protect the gate and p-GaN layer, improving gate lifetime while remaining compatible with mass production processes.

[0029] 3. In this invention, the thickness of the control part is set to 90-100nm, and the thickness of the suppression part is set to 45-50nm. This allows the control part to effectively control the reverse recovery characteristics, improve the hole injection efficiency, and reduce the forward voltage drop, while the suppression part effectively suppresses the electric field peak and reduces leakage current while optimizing the electric field distribution.

[0030] 4. In this invention, the thickness of the enhancement part is set to 90-100nm, and the thickness of the optimization part is set to 45-50nm. This makes the enhancement part effectively increase the gate barrier height and suppress gate leakage current, and the optimization part effectively disperses the drain electric field, increases the device breakdown voltage, and alleviates the current collapse effect.

[0031] 5. The present invention has an isolation zone that completely blocks the lateral leakage path between the SBD device and the HEMT device, ensuring that the device can work independently.

[0032] 6. This utility model improves module performance through precise optimization of the substrate and epitaxial layer thicknesses. Specifically, the 800-1200μm substrate balances mechanical strength and heat dissipation; the 1.8-2.2μm GaN buffer layer filters defects and supports 650V withstand voltage; and the 240-280nm GaN channel layer provides low-resistance 2DEG channels. With advantages as low as 5mΩ·mm, the 0.4-0.6nm AlN nucleation layer has the advantage of increasing the 2DEG density by 30% through quantum confinement, and the 18-22nm AlGaN barrier layer has the advantage of achieving a breakdown voltage of >650V with a uniform electric field. The synergy of each layer enables the module to have three major advantages: high withstand voltage, low loss (switching frequency >10MHz), and strong heat dissipation.

[0033] 7. This utility model incorporates a cathode field plate, an anode field plate, a source field plate, and a drain field plate in its module. The field plate structure can attract some electric field lines to further smooth the electric field distribution and reduce the peak electric field.

[0034] 8. This utility model can encapsulate the substrate layer, epitaxial layer, SBD device and HEMT device within an insulating shell, which has the advantages of effectively protecting internal components and improving module stability and service life. Attached Figure Description

[0035] Figure 1 This is a three-dimensional structural diagram of the present invention;

[0036] Figure 2 for Figure 1 A schematic diagram of the cross-section of the SBD device viewed from the left.

[0037] Figure 3 for Figure 1 A cross-sectional schematic diagram of a HEMT device viewed from the right.

[0038] Figure 4 This is a schematic diagram of the external inductor structure of this utility model.

[0039] The following are labeled in the figure: 1. Substrate layer, 2. GaN buffer layer, 3. GaN channel layer, 4. AlN nucleation layer, 5. AlGaN barrier layer, 6. p-GaN layer, 7. SBD active region, 8. HEMT active region, 9. Cathode, 10. Anode, 11. Control section, 12. Suppression section, 13. Source, 14. Drain, 15. Gate, 16. Enhancement section, 17. Optimization section, 18. Insulating dielectric layer, 19. Isolation region, 20. Control section, 21. Cathode field plate, 22. Anode field plate, 23. Source field plate, 24. Drain field plate. Detailed Implementation

[0040] The present invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0041] like Figure 1 As shown, this utility model provides a gallium nitride monolithic integrated power module, including a substrate layer 1, an epitaxial layer above the substrate layer 1, and isolated SBD active regions 7 and HEMT active regions 8 on the epitaxial layer. Both SBD active regions 7 and HEMT active regions 8 are arranged along the longitudinal direction of the epitaxial layer (front-to-back direction). SBD devices are housed within the SBD active region 7, and HEMT devices are housed within the HEMT active region 8. The SBD devices and HEMT devices share the substrate layer 1 and the epitaxial layer.

[0042] like Figure 2 As shown, the SBD device includes a cathode 9, an anode 10, and a p-GaN layer 6. The cathode 9 and anode 10 are located at the front and rear ends of the SBD active region 7, respectively. The anode 10 can be formed by stacking Ti / Al / Ni / Au metals and forming an ohmic contact with the epitaxial layer, with a forward voltage drop of less than 0.5V. The cathode 9 can be formed by stacking Ti / Al / Ni / Au metals and forming an ohmic contact with the epitaxial layer. The p-GaN layer 6 is located in the middle to rear part of the SBD active region 7 and close to the anode 10. To better improve the performance of the SBD device, this embodiment designs the p-GaN layer 6 as a structure including an integrally formed control part 11 and a suppression part 12. The control part 11 forms an ohmic contact with the anode 10, and the thickness of the control part 11 is greater than the thickness of the suppression part 12, so that the p-GaN layer 6 forms a variable doping structure. Based on this structure, the control section 11 can regulate reverse recovery characteristics, improve hole injection efficiency, and reduce forward voltage drop, while the suppression section 12 can suppress electric field peaks and reduce leakage current while optimizing electric field distribution. Furthermore, the anode 10 has a control section 20 extending towards the cathode 9 and partially covering the control section 11, and this control section 20 forms an ohmic contact with the p-GaN layer 6. This control section 20 can perform depletion control on the p-GaN layer 6.

[0043] like Figure 3 As shown, the HEMT device includes a source 13, a drain 14, a gate 15, and a p-GaN layer 6. The source 13 and drain 14 are located at the front and rear ends of the HEMT active region 8, respectively. The source 13 and drain 14 can be formed by electron beam evaporation of Ti / Al / Ni / Au metal stacks followed by rapid annealing at 850°C. Both the source 13 and drain 14 form ohmic contacts with the epitaxial layer, with a contact resistance of less than 0.5 Ω•mm. The p-GaN layer 6 and gate 15 are located between the source 13 and drain 14. To further improve the performance of the HEMT device, this embodiment designs the p-GaN layer 6 as a structure including an integrally formed enhancement portion 16 and an optimization portion 17. The thickness of the enhancement portion 16 is greater than the thickness of the optimization portion 17, forming a variable doping structure in the p-GaN layer 6. The gate 15 covers part of the enhancement portion 16 and forms a Schottky contact with the enhancement portion 16. The optimization portion 17 is located between the enhancement portion 16 and the drain 14. Based on this structure, the enhancement part 16 can increase the barrier height of the gate 15 and suppress the leakage current of the gate 15, and the optimization part 17 can disperse the electric field of the drain 14, increase the breakdown voltage of the device and alleviate the current collapse effect.

[0044] like Figure 1 As shown, the anode 10 of the SBD device is connected to the drain 14 of the HEMT device via a wire. In practical applications, the power module provided by this invention is typically connected to an inductor, such as... Figure 4 As shown, the anode 10 of the SBD device and the drain 14 of the HEMT device are both connected to the output terminal of the inductor.

[0045] In this embodiment, as Figure 2 , 3 As shown, both SBD devices and HEMT devices include an insulating dielectric layer 18 ( Figure 1 (Not shown in the diagram) In an SBD device, the insulating dielectric layer 18 is located between the cathode 9 and the anode 10, and simultaneously covers the control section 20, the regulation section 11, the suppression section 12, and the epitaxial layer; in a HEMT device, the insulating dielectric layer 18 is located between the source 13 and the drain 14, and simultaneously covers the gate 15, the enhancement section 16, the optimization section 17, and the epitaxial layer. The insulating dielectric layer 18 is typically made of materials such as SiN, covering the entire surface of the active region, and has the functions of providing surface passivation, reducing interface states, suppressing current collapse, and mitigating dynamic resistance degradation.

[0046] In this embodiment, as Figure 1As shown, substrate 1 is a silicon substrate, SiC substrate, or sapphire substrate. The epitaxial layers include a GaN buffer layer 2, a GaN channel layer 3, an AlN nucleation layer 4, and an AlGaN barrier layer 5. The GaN buffer layer 2, GaN channel layer 3, AlN nucleation layer 4, and AlGaN barrier layer 5 are sequentially epitaxially grown on substrate 1 using metal-organic chemical vapor deposition (MOCVD). The p-GaN layer 6 is grown on the AlGaN barrier layer 5 using MOCVD. The SBD active region 7 and HEMT active region 8 are defined and formed using photolithography and inductively coupled plasma (ICP) etching processes. Both the SBD active region 7 and HEMT active region 8 are located along the front-back direction of substrate 1 and are situated between the GaN channel layer 3 and the AlGaN barrier layer 5.

[0047] Specifically, the substrate layer 1 has a thickness of 800-1200 μm, the GaN buffer layer 2 has a thickness of 1.8-2.2 μm, the GaN channel layer 3 has a thickness of 240-280 nm, the AlN nucleation layer 4 has a thickness of 0.4-0.6 nm, and the AlGaN barrier layer 5 has a thickness of 18-22 nm. Preferably, the substrate layer 1 has a thickness of 1000 μm, the GaN buffer layer 2 has a thickness of 2 μm, the GaN channel layer 3 has a thickness of 260 nm, the AlN nucleation layer 4 has a thickness of 0.5 nm, and the AlGaN barrier layer 5 has a thickness of 20 nm.

[0048] Specifically, the GaN buffer layer 2 can alleviate the lattice mismatch (e.g., the mismatch rate between Si and GaN reaches 17%) and the difference in thermal expansion coefficients between the substrate (Si / SiC / sapphire) and the GaN material. The GaN channel layer 3 and the upper AlGaN barrier layer 5 form a heterojunction interface, utilizing the polarization effect to induce a high-mobility 2DEG (area density ~1×10⁻⁶). 13 cm -2 The mobility is >2000 cm² / V•s). An AlN nucleation layer 4 is inserted between the GaN channel layer 3 and the AlGaN barrier layer 5, utilizing high spontaneous polarization intensity (AlN: 0.081 C / m² vs AlGaN: 0.03 C / m²) to increase the 2DEG density. The polarization between the AlGaN barrier layer 5 and the underlying GaN channel layer 3 generates a high-density 2DEG, ensuring a 2DEG mobility >1500 cm² / V•s.

[0049] In this embodiment, as Figure 1 As shown, an isolation region 19 is formed on the epitaxial layer from the AlGaN barrier layer 5 to the GaN channel layer 3 by ion implantation. The SBD active region 7 and the HEMT active region 8 are isolated by the isolation region 19.

[0050] In one specific embodiment, the area of ​​the control section 11 and the area of ​​the suppression section 12 may be the same or different, and the area of ​​the enhancement section 16 and the area of ​​the optimization section 17 may be the same or different, depending on the actual needs and process.

[0051] In this embodiment, the thickness of the control section 11 is 90-100 nm, the thickness of the suppression section 12 is 45-50 nm, the thickness of the enhancement section 16 is 90-100 nm, and the thickness of the optimization section 17 is 45-50 nm. Preferably, the thickness of the control section 11 is 95 nm, the thickness of the suppression section 12 is 48 nm, the thickness of the enhancement section 16 is 95 nm, and the thickness of the optimization section 17 is 48 nm.

[0052] In a specific embodiment, such as Figure 2 As shown, in the SBD device, a cathode field plate 21 extending towards the anode 10 is integrally formed on the upper part of the cathode 9, and an anode field plate 22 extending towards the cathode 9 is integrally formed on the upper part of the anode 10. The cathode field plate 21 and the anode field plate 22 are isolated by an insulating dielectric layer 18, and the upper surfaces of the cathode field plate 21, the anode field plate 22, and the insulating dielectric layer 18 are all located on the same plane. The suppression portion 12 of the p-GaN layer 6 extends beyond the coverage area of ​​the anode field plate 22. The field plate structure further smooths the electric field distribution and reduces the peak electric field.

[0053] In a specific embodiment, such as Figure 3 As shown, in the HEMT device, a source field plate 23 extending towards the drain 14 is integrally formed on the upper part of the source 13, and a drain field plate 24 extending towards the source 13 is integrally formed on the upper part of the drain 14. The source field plates 23 are isolated from each other by an insulating dielectric layer 18, and the upper surfaces of the source field plates 23, the source field plates 23, and the insulating dielectric layer 18 are all located on the same plane. The optimized portion 17 of the p-GaN layer 6 extends beyond the coverage area of ​​the drain field plate 24. The field plate structure further smooths the electric field distribution and reduces the peak electric field.

[0054] In one specific embodiment, the integrated power module further includes an insulating housing, in which the substrate layer 1, the epitaxial layer, the SBD device, and the HEMT device are all encapsulated to provide better protection for the power module.

[0055] like Figure 1As shown, the gallium nitride monolithic integrated power module proposed in this invention adopts a vertical layout structure, arranging the SBD active region 7 and HEMT active region 8 along the front-to-back direction of the substrate, and directly connecting the SBD anode 10 and HEMT drain 14 through short wires. This design not only significantly shortens the electrode spacing but also compresses the interconnect parasitic inductance to below 1nH, far lower than the 5nH level of the traditional lateral layout, thereby greatly reducing voltage overshoot and ringing during switching. Simultaneously, the shared substrate and epitaxial layer design reduces the module size while increasing power density, making it particularly suitable for applications such as high-frequency PFC circuits.

[0056] In the SBD device, a variable-doped p-GaN layer 6 is used. The p-GaN layer 6 is designed with a control section 11 and a suppression section 12 of varying thicknesses. The thicker control section 11 effectively improves hole injection efficiency, reducing the forward voltage drop to below 0.5V; while the thinner suppression section 12 weakens the electric field strength at the cathode 9 edge, significantly reducing reverse leakage current and tunneling risk. The control section 20 extending from the anode 10 further realizes dynamic depletion control of the p-GaN layer 6, optimizing reverse recovery characteristics and significantly reducing Qrr and tail current.

[0057] HEMT devices also employ a variable-doped p-GaN layer 6 design, which is divided into an enhancement section 16 and an optimization section 17. The enhancement section 16 increases the barrier height of the gate 15 by increasing its thickness, successfully reducing gate leakage current by more than 50%. The optimization section 17 effectively disperses the edge electric field of the drain 14, raising the breakdown voltage to over 650V, while mitigating current collapse and ensuring dynamic resistance fluctuations are controlled within 5%. The Schottky contact design between the gate 15 and the enhancement section 16 further enhances device reliability.

[0058] The power module was also tested according to the following:

[0059] Regarding static characteristics, test results show that the gate 15 leakage current of the experimental HEMT group using the variable-doped p-GaN design is only 0.28 μA / mm² (under the conditions of VGS=-10V, VDS=600V); the SBD forward voltage drop is 0.42V at a current density of 100A / cm²; and the breakdown voltage reaches 672V. These data fully demonstrate the advantages of the variable-doped structure in suppressing gate 15 leakage current, reducing conduction losses, and improving breakdown voltage.

[0060] Dynamic characteristic testing employed a dual-pulse test circuit (Vin=400V, Iload=10A, Tj=150℃). The experimental group performed exceptionally well: the module's parasitic inductance was only 0.8nH; the switching overshoot voltage was controlled at 32V; the reverse recovery charge Qrr decreased to 18nC; and the dynamic on-resistance fluctuation was controlled at 4.2%. In the equivalent test circuit, the voltage ringing phenomenon in the experimental group decayed in less than 20ns, and the tailing phenomenon of the reverse recovery current essentially disappeared. These results validate the significant effects of vertical layout and field board design on reducing parasitic inductance and optimizing switching characteristics.

[0061] The above description is only a specific embodiment of the present utility model. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All features or steps in all methods or processes disclosed may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A gallium nitride monolithic integrated power module, characterized in that: The system includes a substrate layer (1), an epitaxial layer above the substrate layer (1), and isolated SBD active regions (7) and HEMT active regions (8) on the epitaxial layer. An SBD device is disposed within the SBD active region (7), and an HEMT device is disposed within the HEMT active region (8). The SBD device includes a cathode (9), an anode (10), and a p-GaN layer (6). The cathode (9) and the anode (10) are located at the front end and the rear end of the active region (7) of the SBD, respectively. The p-GaN layer (6) includes an integrally formed control part (11) and a suppression part (12). The thickness of the control part (11) is greater than the thickness of the suppression part (12) so that the p-GaN layer (6) forms a variable doping structure. The control part (11) forms an ohmic contact with the anode (10). The anode (10) is provided with a control part (20) that extends towards the cathode (9) and covers part of the control part (11). The control part (20) forms an ohmic contact with the p-GaN layer (6). The HEMT device includes a source (13), a drain (14), a gate (15), and a p-GaN layer (6). The source (13) and drain (14) are located at the front and rear ends of the HEMT active region (8), respectively, and both the source (13) and drain (14) form ohmic contacts with the epitaxial layer. The p-GaN layer (6) and the gate (15) are located between the source (13) and drain (14). The p-GaN layer (6) includes an integrally formed enhancement part (16) and an optimization part (17). The thickness of the enhancement part (16) is greater than the thickness of the optimization part (17) so that the p-GaN layer (6) forms a variable doping structure. The gate (15) covers part of the enhancement part (16) and forms a Schottky contact with the enhancement part (16). The anode (10) of the SBD device is connected to the drain (14) of the HEMT device by a wire.

2. The gallium nitride monolithic integrated power module according to claim 1, characterized in that: Both the SBD device and the HEMT device include an insulating dielectric layer (18). In the SBD device, the insulating dielectric layer (18) is located between the cathode (9) and the anode (10), and simultaneously covers the control section (20), the regulation section (11), the suppression section (12), and the epitaxial layer. In the HEMT device, the insulating dielectric layer (18) is located between the source (13) and the drain (14), and simultaneously covers the gate (15), the enhancement section (16), the optimization section (17), and the epitaxial layer.

3. A gallium nitride monolithically integrated power module according to claim 1, characterized in that: The thickness of the regulation part (11) is 90-100 nm, and the thickness of the suppression part (12) is 45-50 nm.

4. A gallium nitride monolithically integrated power module according to claim 1, characterized in that: The thickness of the reinforcing part (16) is 90-100 nm, and the thickness of the optimizing part (17) is 45-50 nm.

5. A gallium nitride monolithically integrated power module according to claim 1, characterized in that: The epitaxial layer includes a GaN buffer layer (2), a GaN channel layer (3), an AlN nucleation layer (4) and an AlGaN barrier layer (5) that are fixed sequentially on the substrate layer (1). The SBD active region (7) and the HEMT active region (8) are both arranged along the front-back direction of the substrate layer (1) and are both located between the GaN channel layer (3) and the AlGaN barrier layer (5).

6. A gallium nitride monolithically integrated power module according to claim 5, characterized in that: An isolation region (19) is formed on the epitaxial layer from the AlGaN barrier layer (5) to the GaN channel layer (3) by ion implantation. The SBD active region (7) and the HEMT active region (8) are isolated by the isolation region (19).

7. A gallium nitride monolithically integrated power module according to claim 5, characterized in that: The substrate (1) is a silicon substrate, a SiC substrate or a sapphire substrate. The thickness of the substrate (1) is 800-1200 μm, the thickness of the GaN buffer layer (2) is 1.8-2.2 μm, the thickness of the GaN channel layer (3) is 240-280 nm, the thickness of the AlN nucleation layer (4) is 0.4-0.6 nm, and the thickness of the AlGaN barrier layer (5) is 18-22 nm.

8. A gallium nitride monolithic integrated power module according to any one of claims 1-7, characterized in that: In the SBD device, a cathode field plate (21) extending toward the anode (10) is integrally formed on the upper part of the cathode (9), and an anode field plate (22) extending toward the cathode (9) is integrally formed on the upper part of the anode (10). The cathode field plate (21) and the anode field plate (22) are isolated by an insulating dielectric layer (18), and the upper surface of the cathode field plate (21), the upper surface of the anode field plate (22) and the upper surface of the insulating dielectric layer (18) are all located on the same plane.

9. A gallium nitride monolithic integrated power module according to any one of claims 1-7, characterized in that: In the HEMT device, a source field plate (23) extending toward the drain (14) is integrally formed on the upper part of the source (13), and a drain field plate (24) extending toward the source (13) is integrally formed on the upper part of the drain (14). The source field plate (23) is isolated from the source field plate (23) by an insulating dielectric layer (18), and the upper surface of the source field plate (23), the upper surface of the source field plate (23), and the upper surface of the insulating dielectric layer (18) are all located on the same plane.

10. A gallium nitride monolithically integrated power module according to claim 1, characterized in that: The integrated power module also includes an insulating housing, and the substrate layer (1), epitaxial layer, SBD device and HEMT device are all encapsulated in the insulating housing.

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