Semiconductor device

Abstract

This disclosure provides a semiconductor device including a substrate, fins covering the substrate and providing multiple active regions for at least two devices, and a fin insulating structure disposed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a first dielectric material and a pair of seam isolation structures adjacent to the fins on multiple opposing sides of the fins, wherein the pair of seam isolation structures define multiple boundaries of the fin insulating structure on the sides of the fins.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] In recent years, the integrated circuit (IC) industry has experienced rapid and sustained growth. Technological advancements in IC materials and design have led to continuous improvements in ICs generation after generation. Each new generation of products features smaller and more complex circuits than its predecessor, enabling higher functional density (i.e., the number of interconnect devices per wafer area) and smaller geometries (i.e., the smallest components or lines that can be created using a single manufacturing process). This scaling down of processes improves production efficiency and reduces associated costs. However, as feature sizes continue to shrink, manufacturing processes become more challenging, making it increasingly difficult to ensure the reliability of semiconductor devices. Therefore, the industry faces the ongoing challenge of developing processes capable of manufacturing smaller, more reliable ICs. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor device includes a substrate, fins, fin insulating structures, and a pair of seam isolation structures. The fins cover the substrate and provide multiple active regions for at least two devices. The fin insulating structures are configured to electrically isolate the active regions of the at least two devices, wherein the fin insulating structures extend through the fins and into the substrate, and wherein the fin insulating structures include a first dielectric material. A pair of seam isolation structures are located adjacent to the fins on multiple opposing sides of the fins, wherein the seam isolation structures define multiple boundaries of the fin insulating structures on the sides of the fins.

[0004] According to some embodiments of this disclosure, a semiconductor device includes a substrate, fins, a plurality of seam isolation structures, a plurality of active regions of at least two devices, and a fin insulating structure. The fins cover the substrate. The plurality of seam isolation structures are located adjacent to the fins on a plurality of oppositely disposed sides of the fins. The plurality of active regions of at least two devices are disposed on the fins. The fin insulating structure is configured to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a dielectric layer, and wherein the seam isolation structures define a plurality of boundaries of the fin insulating structure on the sides of the fins.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a substrate, fins, multiple active regions of multiple devices, multiple seam isolation structures, multiple gate structures, fin insulating structures, and multiple contacts. The fins cover the substrate. Multiple active regions of the multiple devices are disposed on the fins. Multiple seam isolation structures are disposed adjacent to the fins on multiple opposing sides of the fins, wherein the seam isolation structures extend from a shallow trench isolation within a location adjacent to the fins, and wherein the seam isolation structures include a first dielectric layer. Multiple gate structures are disposed between the active regions of the device. A fin insulating structure is disposed to electrically isolate at least two active regions in the device, wherein the fin insulating structure allows the seam isolation structure to directly contact the fin insulating structure, wherein the fin insulating structure includes a second dielectric layer, and wherein the seam isolation structure defines multiple boundaries of the fin insulating structure on the sides of the fins. Multiple contacts are electrically coupled to the active regions of the device. Attached Figure Description

[0006] When the following detailed description and appendix Figure 1 When reading this document, the following detailed description is recommended for a better understanding of its format. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of an exemplary method for forming a semiconductor structure according to some embodiments;

[0008] Figures 2 to 45 A first method for forming a semiconductor structure according to some embodiments is illustrated schematically;

[0009] Figures 46 to 85 This schematically illustrates a second method for forming a semiconductor structure according to some embodiments;

[0010] Figure 86 A partial top view schematically illustrating a portion of a semiconductor device at one stage of an integrated circuit manufacturing process, according to some embodiments;

[0011] Figure 87 A partial top view schematically illustrating a portion of a semiconductor device at one stage of an integrated circuit manufacturing process, according to some embodiments;

[0012] Figure 88 A perspective view schematically illustrating a portion of a semiconductor device at one stage of an integrated circuit manufacturing process, according to some embodiments.

[0013] [Symbol Explanation]

[0014] 100: Method

[0015] 110: Steps

[0016] 112: Steps

[0017] 114: Steps

[0018] 116: Steps

[0019] 118: Steps

[0020] 120: Steps

[0021] 122: Steps

[0022] 124: Steps

[0023] 126: Steps

[0024] 210: Fins

[0025] 211: Region

[0026] 212: Dummy sacrificial gate layer or insulating layer

[0027] 214: Hard mask layer

[0028] 216: Shallow trench isolation

[0029] 218: Fictitious fins

[0030] 220: Source / Drain Structure

[0031] 222: Etching Stop Layer

[0032] 224: Spacer layer

[0033] 226: ILD layer

[0034] 228: Hard mask layer

[0035] 230: Hard mask layer

[0036] 232: Trench

[0037] 233: Trench

[0038] 236: Trench

[0039] 240: Trench

[0040] 242: First gate spacer

[0041] 244: Second gate spacer

[0042] 246: Metal gate layer

[0043] 248: Trench

[0044] 250: Metal layer

[0045] 252: SAC Sacrificial Material Layer

[0046] 254: Hard mask layer

[0047] 256: Bottom layer

[0048] 258: Intermediate Layer

[0049] 260: Photoresist layer

[0050] 262: Trench

[0051] 264: Trench

[0052] 266: Trench

[0053] 268: Fin insulation structure

[0054] 270:Substrate

[0055] 272: Trench

[0056] 274: Metal contact layer

[0057] 276: SAC insulation material layer

[0058] 278: Trench

[0059] 280: Dielectric layer

[0060] 282: Conductive layer

[0061] 290: Joint isolation structure

[0062] 292: Extended virtual fins

[0063] 294: Seam

[0064] x-cut: X-cut

[0065] y-cut: Y-cut Detailed Implementation

[0066] The following disclosure provides numerous different embodiments or instances of various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these examples are merely exemplary and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0067] As used herein, terms such as “first” and “second” describe various elements, components, regions, layers and / or sections, but these elements, components, regions, layers and / or sections should not be limited by these terms. These terms may be used only to distinguish elements, components, regions, layers or sections from one another. Unless expressly indicated herein, terms such as “first” and “second” as used herein do not imply a sequence or order.

[0068] For the sake of brevity, conventional techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into a more comprehensive step or process with additional functionality not described in detail herein. In particular, various processes for manufacturing semiconductor devices are well known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. It will become apparent to those skilled in the art, upon a full reading of this disclosure, that the structures disclosed herein can employ various techniques and can be incorporated into a wide variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in a figure may represent multiple elements.

[0069] Furthermore, spatial relative terms, such as “below,” “below,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship of one element or feature relative to another element or feature, as illustrated in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those described in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be understood accordingly. When spatially related terms (such as those exemplified above) are used to describe a first element and an associated second element, the first element may be directly on the other element, or there may be an intermediate element or membrane layer present. When referring to an element or membrane layer “on” another element or membrane layer, it is directly on and in contact with the other element or membrane layer.

[0070] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing that feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0071] Some embodiments of this disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are generally used to refer to the same parts throughout the text. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other examples, structures and arrangements are illustrated in block diagram form to facilitate the description of the claimed subject matter.

[0072] Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be substituted or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some features described below may be substituted or eliminated for different embodiments. Although some embodiments are described with operations performed in a specific order, these operations may be performed in a different logical order.

[0073] As used in this article, a “layer” is a region, such as a region with arbitrary boundaries, and not necessarily with uniform thickness. For example, a layer can be a region that includes at least some variation in thickness.

[0074] In semiconductor manufacturing, self-aligning contact (SAC) technology is used to establish contacts between metal interconnects and underlying semiconductor devices, such as transistors. SAC processes often use sacrificial material to temporarily fill the gaps between metal interconnects before the final contact is formed. This sacrificial material is then removed, leaving the self-aligned contact. In advanced nodes with stringent scaling requirements, SAC processes are needed to prevent leakage between the metal gate and the metal contacts connecting the source or drain.

[0075] Continuous metal on diffusion edge (CMODE) processes can be used, where a metal gate extends along the edge of the diffusion region. These processes can improve device performance and reduce parasitic resistance and capacitance. For the purposes of this disclosure, "diffusion edge" can be equivalently referred to as an active edge, where, for example, an active edge adjoins an adjacent active region. Furthermore, active regions include areas that form transistor structures (e.g., including source / drain structures and gate / channel structures). In some examples, active regions can be situated between insulating regions. The CMODE process provides isolation regions between adjacent active regions by performing an etching process along the active edge (e.g., at the boundary of adjacent active regions) to form cut regions and filling the cut regions with refill material, thereby providing isolation regions between adjacent transistors.

[0076] However, combining SAC and CMODE processes presents several challenges. For example, if the SAC sacrificial material includes seams extending through it, byproduct materials from the etching process and / or refill materials may flow or diffuse into the seams connected to the diced area, potentially leading to serious defects in the semiconductor device and increasing the risk of leakage.

[0077] This document presents embodiments of semiconductor devices and methods for forming semiconductor devices using a combination of SAC and CMODE processes. To reduce the likelihood of unwanted material entering the seams of the SAC sacrificial material, the exemplary semiconductor devices disclosed herein include seam isolation structures configured to seal multiple line ends of the semiconductor device. As used herein, a “line end” refers to the point where a metal gate line terminates or ends. The metal gate is a conductive path made of metal (e.g., TiN, TiAl, or W) patterned on the surface of the semiconductor device. These metal gates are used to turn transistors on or off on an integrated circuit. In some examples, the seam isolation structure is formed in the semiconductor device prior to performing the SAC and / or CMODE processes.

[0078] refer to Figure 1 The flowchart provides an exemplary method 100 for forming a semiconductor device according to various paradigms. For example, at least some operations (or steps) of method 100 can be used to form a fin field-effect transistor (FinFET) device, a gate-all-around (GAA) FET device, a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, etc. It should be noted that method 100 is merely exemplary and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 1 Method 100 provides additional operations before, during, and after, and this document may only briefly describe some of these other operations. For convenience, please refer to [reference needed]. Figures 2 to 88 Various views of exemplary semiconductor devices illustrating different manufacturing stages of the integrated circuit manufacturing process are used to describe certain operations of method 100. However, it should be understood that the semiconductor devices and methods disclosed herein are not limited to method 100 or... Figures 2 to 88 The example shown. Figures 2 to 85 In the diagram, even-numbered figures are cross-sectional views of the semiconductor structure from an x-cut perspective, while odd-numbered figures are cross-sectional views of the semiconductor structure from a y-cut perspective.

[0079] Method 100 may begin at step 110. In step 112, method 100 includes providing a semiconductor device at an intermediate stage of the manufacturing process. For convenience, semiconductor devices at various intermediate stages of the manufacturing process will be referred to herein as semiconductor structures. The semiconductor device can be any of the various types of semiconductor devices as described above. As an example, Figure 2 and Figure 3 Cross-sectional views of the semiconductor structure along the x and y directions are shown respectively at intermediate stages of the FinFET device fabrication process (in... Figure 88 In this context, they are referred to as the x-section and y-section.

[0080] exist Figure 2 and Figure 3 The manufacturing stage shown includes a semiconductor structure comprising a fin structure (fin) 210, which is disposed of from a substrate 270 (e.g., Figures 50 to 85 and Figure 88 The fin extends through the shallow trench isolation (STI) 216 above the substrate 270 and into the dummy sacrificial gate layer 212 above the STI 216. Optionally, the dummy fin 218 extends from the STI 216 and into the insulating layer 212. A hard mask layer 214 covers the insulating layer 212.

[0081] Substrate 270 can be one of many types of semiconductor substrates commonly used in semiconductor integrated circuit manufacturing, and integrated circuits can be formed therein and / or on it. Substrate 270 can be any construction including semiconductor materials, including but not limited to bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. Other semiconductor materials can be used, including group III, group IV, and / or group V semiconductors.

[0082] Fin 210 may be formed from one or more materials commonly used for active fins in semiconductor devices. In some examples, fin 210 may include certain conductive materials, such as, but not limited to, silicon and silicon-based materials. In some examples, fin 210 may be formed by various combinations of lithography and etching processes.

[0083] The lithography and etching processes discussed herein may include, for example, the formation of a mask layer (which may include multiple layers, such as a pad oxide layer and a covering pad nitride layer) over the layer to be modified (e.g., substrate 270). The pad oxide layer may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the layer to be modified and the covering pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. For example, the pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Lithography techniques may be used to pattern the mask layer. Generally, lithography utilizes the deposition, irradiation (exposure), and development of photoresist material to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). For example, a patterned mask is formed by using a photoresist material to pattern the pad oxide layer and the pad nitride layer. Once the patterned mask is formed, an etching process can be used to etch the layer to be modified.

[0084] The etching processes discussed in this article may include plasma etching processes, which may possess a certain degree of anisotropic characteristics. In such plasma etching processes (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources (such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), ammonia (NH3), and other suitable gas sources and combinations thereof) may be used in conjunction with passivation gases (such as oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof). Furthermore, for plasma etching processes, the gas source and / or passivation gas can be diluted and controlled using gases such as argon (Ar), helium (He), neon (Ne), nitrogen (N2), and other suitable diluting gases and combinations thereof to control the etching rate.

[0085] In another example, the etching process discussed herein may include a wet etching process combined with a plasma etching process, which may have a certain degree of isotropic characteristic. In such a wet etching process, the primary etching chemicals (e.g., hydrofluoric acid (HF), fluorine (F2), and other suitable primary etching chemicals and combinations thereof) may be used together with auxiliary etching chemicals (e.g., sulfuric acid (H2SO4), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH3), phosphoric acid (H3PO4), and other suitable auxiliary etching chemicals and combinations thereof) and solvents (e.g., deionized water, alcohol, acetone, and other suitable solvents and combinations thereof) to control the aforementioned etching rate.

[0086] The dummy sacrificial gate layer 212 may include various insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), certain high-k dielectric materials (e.g., hafnium oxide (HfO2) or aluminum oxide (Al2O3)), and polysilicon. In some examples, a thin layer of silicon oxide-based dielectric material may be disposed between the dummy sacrificial gate layer 212 and the fin 210 and separate the dummy sacrificial gate layer 212 and the fin 210. The STI 216 may include one or more materials commonly used in STIs in semiconductor devices. In some examples, the STI 216 may include various insulating materials, such as silicon dioxide (SiO2). The dummy fin 218 may include one or more materials commonly used in dummy fins in semiconductor devices. In some examples, the dummy fin 218 may include the same or different materials as the fin 210. In some examples, the dummy fin 218 may include one or more layers of insulating material, such as, but not limited to, silicon nitride (Si3N4). The hard mask layer 214 may include one or more materials commonly used in hard masks in semiconductor devices. In some examples, the hard mask layer 214 may include various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO).

[0087] In step 114, method 100 includes designating a region of the semiconductor device to form a fin insulating structure. This region can be designated to separate individual active regions of the semiconductor device. Figure 3 In this context, region 211 is indicated as the location of the wing insulation structure that will typically be generated in a later stage of method 100.

[0088] As described above, a seam isolation structure is formed around region 211 before the fin insulating structure is formed. However, in some examples, other components of the semiconductor structure may be formed before the seam isolation structure is formed. For example, method 100 may include forming a source / drain structure, an ILD, etc. Figures 4 to 7An exemplary process is shown for forming various components in a semiconductor structure prior to forming a seam isolation structure.

[0089] exist Figures 4 to 5 In this process, a trench 236 is formed in the semiconductor structure by removing multiple portions of the dummy sacrificial gate layer 212 and the fin 210. In some examples, as previously described, multiple portions of the dummy sacrificial gate layer 212 and the fin 210 can be removed using lithography and etching processes. The cavity in the fin 210 at the bottom of the trench 236 is filled to form a source / drain structure 220.

[0090] The etch stop layer 222 may be formed on the walls of the trench 236 adjacent to the hard mask layer 214 and the dummy sacrificial gate layer 212. In some examples, the etch stop layer 222 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process (e.g., plasma enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or a combination thereof), an atomic layer deposition (ALD) process, another suitable process, or a combination thereof. The etch stop layer 222 may be formed of a material resistant to etchants used to remove other materials from the semiconductor structure in subsequent steps of method 100, which is discussed in more detail below. In some examples, the etch stop layer 222 may comprise a silicon oxide (SiO)-based low-k material or be formed of a silicon oxide (SiO)-based low-k material.

[0091] At the bottom of trench 236, a source / drain structure 220 can be formed on the exposed portion of fin 210 using, for example, an epitaxial layer growth process. In some examples, the epitaxial layer growth process may include depositing a thin layer of semiconductor material, such as, but not limited to, silicon germanium (SiGe) or other materials suitable for enhancing transistor performance characteristics, on the surface of fin 210. Chemical vapor deposition (CVD) processes can be used for epitaxial growth. CVD processes may include introducing a precursor gas containing the desired semiconductor element into a reaction chamber at a high temperature. These gases decompose and react on the surface, resulting in the deposition of a crystalline semiconductor layer. Depending on the specific transistor to be produced, dopant atoms may be introduced during epitaxial growth to achieve desired electrical characteristics in the source / drain regions. Dopants such as phosphorus, arsenic, or boron may be used to control the conductivity and carrier concentration in the epitaxial layer. After epitaxial growth, an annealing process may be performed to improve crystal quality and activate the dopants in the epitaxial layer.

[0092] exist Figures 6 to 7In this configuration, trench 236 may fill spacer layer 224, ILD layer 226, and hard mask layer 228. In some examples, spacer layer 224 may comprise one or more materials commonly used as spacers in semiconductor devices, or be formed of one or more materials, such as silicon oxide, silicon nitride, or silicon carbide-based materials. In some examples, ILD layer 226 may comprise one or more materials commonly used as ILD layers in semiconductor devices, or be formed of one or more materials commonly used as ILD layers in semiconductor devices. In some examples, ILD layer 226 may comprise various dielectric materials, including silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or combinations thereof. In some examples, hard mask layer 228 may comprise one or more materials commonly used as hard masks in semiconductor devices. In some examples, the hard mask layer 228 may comprise various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO). The spacer layer 224, the ILD layer 226, and the hard mask layer 228 can all be formed by various processes, such as certain deposition processes. A chemical mechanical polishing (CMP) process can be performed to remove any remaining portion of the hard mask layer 228.

[0093] In step 116, method 100 may include forming a seam isolation structure around a region designated for the fin insulation structure (e.g., region 211). Various methods may be used to form the seam isolation structure. Figures 8 to 13 An exemplary process for forming a seam isolation structure in a semiconductor structure is shown.

[0094] exist Figures 8 to 9 In this process, a hard mask layer 230 is formed on the semiconductor structure. In some examples, the hard mask layer 230 may include various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO). A patterning process (e.g., dicing polysilicon) is performed to form a trench 232 that extends through the hard mask layer 230, through the dummy sacrificial gate layer 212, and exposes multiple portions of a dummy fin 218 disposed on opposite sides of region 211, enabling simultaneous gate patterning and seam isolation structure formation in the CMODE process. In some examples, the dummy fin 218 may be omitted and the trench 232 may extend to STI 216.

[0095] exist Figures 10 to 11In the process, trench 232 is filled to form a seam isolation structure 290. The seam isolation structure 290 may include or be formed of one or more dielectric materials, such as, but not limited to, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon carbide, etc., or combinations thereof. In some examples, the seam isolation structure 290 may be formed of or comprise the same material as the hard mask layer 230. Figures 12 to 13 In the process, CMP has been performed to remove the hard mask layer 230.

[0096] After the seam isolation structure 290 is formed and before the fin isolation feature is formed, other components of the semiconductor device, such as, but not limited to, the gate structure, may be formed. Figures 14 to 19 An exemplary process for a gate structure in a semiconductor structure is shown.

[0097] exist Figures 14 to 15 In this process, trench 240 is formed by removing portions of the dummy sacrificial gate layer 212 to expose fins 210, STI 216, and dummy fins 218. In some examples, an etching process can be used to remove the insulating layer 212. Figures 16 to 17 In this design, trench 240 is filled with various layers forming a gate structure, such as a first gate spacer 242, a second gate spacer 244, and a metal gate layer 246. In some examples, the first gate spacer 242 and the second gate spacer 244 may comprise a single common layer or a combination of two or more common layers. In some examples, the first gate spacer 242 may comprise a dielectric material, such as, but not limited to, a silicon-based dielectric, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. In some examples, the second gate spacer 244 may comprise a high-k dielectric material, such as, but not limited to, hafnium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, etc. In some examples, a combination of the first gate spacer 242 and the second gate spacer 244 having an opposite or repeating order may be used.

[0098] In some examples, the metal gate layer 246 may be formed of one or more layers of metal material. For example, the metal gate layer 246 may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals may include TiN, TAN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals may include Ti, Ag, TaAl, TaAIC, TiAlN, TAC, TACN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0099] The first gate spacer 242, the second gate spacer 244, and the metal gate layer 246 can be formed using various processes, such as certain deposition processes. CMP processes can be used between the formation processes as needed.

[0100] exist Figures 18 to 19 In this process, trench 248 is formed by removing portions of the gate structure layers to achieve the desired gate structure dimensions. In some examples, removal can be performed using a metal gate etch-back process. Optionally, metal layer 250 can be selectively formed on exposed portions of metal gate layer 246. Portions of etch stop layer 222 and spacer layer 224 can be removed to expose portions of ILD layer 226 and hard mask layer 228. A portion of seam isolation structure 290 may also be exposed.

[0101] In step 118, method 100 includes forming a SAC sacrificial material layer. Figures 20 to 21 In this configuration, trench 248 is filled with a SAC sacrificial material layer 252. The SAC sacrificial material layer 252 can be formed using various processes, such as certain deposition processes. The SAC sacrificial material layer 252 may include one or more materials commonly used in semiconductor devices as SAC sacrificial materials, or may be formed from one or more materials commonly used in semiconductor devices as SAC sacrificial materials. In some examples, the SAC sacrificial material layer 252 may include or be formed from amorphous silicon. A hard mask layer 254 may be formed to cover the SAC sacrificial material layer 252 and the seam isolation structure 290. The hard mask layer 254 may include one or more materials commonly used in hard masks in semiconductor devices. In some examples, the hard mask layer 214 may include various insulating materials, such as silicon nitride (Si3N4), silicon oxide (SiO2), or silicon. Figure 20 As shown, the SAC sacrificial material layer 252 may include a seam extending through the semiconductor structure above the gate structure (e.g., Figure 86 and Figure 87 (Seam 294 in the middle).

[0102] In step 120, method 100 includes forming a fin insulation structure between the seam isolation structures 290. Figures 22 to 23 An exemplary process for forming fin insulating structures in a semiconductor structure is shown. Figures 22 to 23 In this process, a photoresist layer 260, an intermediate layer 258, and a bottom layer 256 have been formed to cover the hard mask layer 254. A trench 262 has been formed in the photoresist layer 260, which exposes the intermediate layer 258 and is aligned with the region 211 designated for the fin insulation structure. Figure 88 yes Figures 22 to 23 The diagram shows a perspective view of the semiconductor structure at different manufacturing stages, where the ILD layer 226 is partially transparent to allow for observation of the other layers.

[0103] exist Figures 24 to 25 In this process, lithography and etching processes have been performed to extend trench 262 through a portion of intermediate layer 258, bottom layer 256, hard mask layer 254, and SAC sacrificial material layer 252 to define trench 264 and expose the metal layer 250 covering trench 264. The photoresist layer 260, intermediate layer 258, and bottom layer 256 are then removed. Specifically, at least some sidewalls of trench 264 are defined by seam isolation structures 290, preventing trench 264 from accessing seams within the SAC sacrificial material layer 252; that is, trench 264 is not in fluid communication with its adjacent seams.

[0104] exist Figures 26 to 27 In this process, another etching process has been performed to remove the gate structure exposed by trench 264 and expose fin 210 and a portion of the STI 216 beneath it. Figure 28 and Figure 29 In this process, another etching process can be performed to remove portions of the fin 210, as well as the adjacent STI 216 and substrate 270, within the designated region 211 for the fin insulation structure. The removal of the fin 210 and adjacent material extends the trench 264 to define additional trench 266.

[0105] exist Figures 30 to 31 In this process, a CMODE refill process has been performed to fill trenches 264 and 266 to form fin insulation structure 268. Fin insulation structure 268 can be formed from a CMODE refill material, such as a low-k material or a dielectric material. It is noteworthy that the CMODE refill material does not flow or diffuse into the seams of the SAC sacrificial material layer 252 because the CMODE refill material is constrained by the seam isolation structure 290. Figures 32 to 33 In the process, CMP is performed to remove excess portions of the fin insulation structure 268, hard mask layer 254, and SAC sacrificial material layer 252 sufficient to expose the hard mask layer 228. Figure 86 It is a schematic representation Figures 32 to 33 The diagram shows a top view of some layers of the semiconductor structure at the manufacturing stage (other layers and features are omitted for clarity). From this perspective, it is clear that the seam isolation structure 290 blocks the seam of the SAC sacrificial material layer 252, thereby preventing or reducing the possibility of CMODE refill material (or any other undesirable material) flowing or diffusing into the seam.

[0106] In step 122, method 100 includes removing the SAC sacrificial material layer. Figures 34 to 35 In this process, the SAC sacrificial material layer 252 has been removed to define the trench 272 and expose the gate structure beneath it, as well as a portion of the etch stop layer 222 and spacer layer 224.

[0107] In step 124, method 100 includes performing a SAC process to form source / drain contacts. Figures 36 to 45 An exemplary process for forming source / drain contacts in a semiconductor structure is shown. Figures 36 to 37 In this configuration, trench 272 is filled with a SAC insulating material layer 276 covering the gate structure, hard mask layer 228, seam isolation structure 290, and fin insulating structure 268. In some examples, the SAC insulating material layer 276 may include silicon nitride (SiN). In some examples, a metal contact layer 274 may be formed on the gate structure prior to the formation of the SAC insulating material layer 276. The metal contact layer 274 may include a conductive material of tungsten (W) or cobalt (Co).

[0108] exist Figures 38 to 39 In the process, a CMP process has been performed to remove excess portions of the SAC insulating material layer 276 and the hard mask layer 228 to expose the ILD layer 226. Figures 40 to 41 In the process, an etching process has been performed to remove the ILD layer 226, forming a trench 278 and exposing a portion of the source / drain structure 220.

[0109] exist Figures 42 to 43 In this configuration, a dielectric layer 280 has been formed over a SAC insulating material layer 276, and trenches 278 have been filled with a conductive layer 282. In some embodiments, a silicide may be formed between the conductive layer 282 and the source / drain structure 220 to reduce the contact resistance between the metal and the source or drain. The dielectric layer 280 may comprise or be formed from various dielectric materials and may be formed by various deposition, lithography, and etching processes. Although represented as a single layer, the conductive layer 282 may comprise two or more layers to prevent metal migration to the dielectric layer. For example, the conductive layer 282 may include filler materials and pads. In some embodiments, these layers may include pads formed of noble metals or alloys thereof, such as, but not limited to, rhenium (Re), rhodium (Rh), ruthenium (Ru), or alloys thereof. In some embodiments, these layers may include filler materials formed of copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. The conductive layer 282 may be formed by various deposition processes. Figures 44 to 45 In this process, a CMP process has been performed to remove excess material from the conductive layer 282, thereby defining source / drain contacts above the source / drain structure 220.

[0110] Method 100 can end at step 126.

[0111] Figures 46 to 85 An alternative process for forming seam isolation structures in a semiconductor structure is illustrated. For simplicity, throughout... Figure 2 Up to section 85, consistent reference numerals are used to identify identical or functionally related / equivalent elements. Given the similarity between the examples, Figures 46 to 85The following discussion will focus primarily on aspects of the paradigm that distinguish it from other paradigms in some significant or marked ways. Other aspects of the paradigm not discussed in detail may be substantially the same as those of one or more other paradigms (including...). Figures 2 to 45 (as described in the example).

[0112] Initially, semiconductor structures could have the same characteristics as... Figure 2 and Figure 3 The structure shown is the same as the structure shown. Figure 47 In the diagram, region 211 is shown, which typically specifies the location of the fin insulation structure. Figures 2 to 45 Unlike the previous example, in this example, a seam isolation structure can be formed before other components of the semiconductor structure. Therefore, in Figures 46 to 47 In this process, trench 233 is formed by removing a portion of the hard mask layer 214 and the dummy sacrificial gate layer 212 to expose a portion of the dummy fin 218. In some examples, a portion of the hard mask layer 214 can be removed using processes such as lithography and etching. Figures 48 to 49 In this configuration, trench 233 is filled with insulating material to extend dummy fin 218 to define extended dummy fin 292. In some examples, the insulating material may be the same material used to form dummy fin 218. A CMP process may be performed to remove excess portions of hard masking layer 214 and extended dummy fin 292. In this example, extended dummy fin 292 defines a seam isolation structure and may be considered to extend from or be integrated with dummy fin 218 and thus extend from STI 216.

[0113] Figures 50 to 53 An exemplary process for forming the source / drain structure 220, spacer layer 224, ILD layer 226, and hard masking layer 228 is shown. In some examples, the source / drain structure 220, spacer layer 224, ILD layer 226, and hard masking layer 228 can be configured according to... Figures 4 to 7 It is formed by describing it.

[0114] Figures 54 to 59 An exemplary process for forming a gate structure in a semiconductor structure is illustrated. In some examples, the gate structure can be configured according to... Figures 14 to 19 It is formed by the description.

[0115] Figures 60 to 61 An exemplary process for forming a SAC sacrificial material layer 252 in a semiconductor structure is shown. In some examples, the SAC sacrificial material layer 252 can be configured according to... Figures 20 to 21 It is formed by the description.

[0116] Figures 62 to 73 An exemplary process for forming a fin insulating structure in a semiconductor structure is illustrated. In some examples, the fin insulating structure can be configured according to... Figures 22 to 33 It is formed by the description. Figure 87 It is a schematic representation Figures 72 to 73 The diagram shows a top view of some layers of a semiconductor structure at a manufacturing stage (other layers and features are omitted for clarity). From this perspective, it is clear that the extended dummy fins 292 block the seams of the SAC sacrificial material layer 252, thereby preventing or reducing the possibility of CMODE refill material (or any other undesirable material) flowing or diffusing into the seams.

[0117] exist Figures 2 to 45 In one example, the semiconductor structure includes a seam isolation structure 290 formed to cover the dummy fin 218, and... Figures 46 to 73 In one example, the semiconductor structure includes an extended dummy fin 292 covering the dummy fin 218. However, in some examples, the dummy fin 218 may be omitted, and either a seam isolation structure 290 formed to directly contact the STI 216 or the extended dummy fin 292 may be used. Figures 2 to 73 The methods shown and described in the document.

[0118] Figures 74 to 75 An exemplary process for removing the SAC sacrificial material layer 252 is shown. In some instances, it can be based on... Figures 34 to 35 The description is about removing the SAC sacrificial material layer 252.

[0119] Figures 76 to 85 An exemplary process for forming source / drain contacts in a semiconductor structure is illustrated. In some instances, the source / drain contacts can be configured according to the figure. Figures 36 to 45 It is formed by the description.

[0120] Therefore, this disclosure provides a semiconductor device and a method for manufacturing the same that can significantly reduce the likelihood of defects in a semiconductor device. In some embodiments, the semiconductor device includes a seam isolation structure configured to reduce the possibility of material flow or diffusion into the SAC sacrificial material during the CMODE process.

[0121] According to one embodiment, a semiconductor device is provided, including a substrate, fins covering the substrate and providing multiple active regions for at least two devices, and a fin insulating structure disposed to electrically isolate the active regions of at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a dielectric material, and a butt joint isolation structure adjacent to the fins on multiple opposing sides of the fins, wherein the butt joint isolation structure defines multiple boundaries of the fin insulating structure on the sides of the fins.

[0122] In some embodiments, the butt joint isolation structure is located at multiple ends of the metal grid lines. In some embodiments, the fin insulation structure makes direct contact between the butt joint isolation structure and the fin insulation structure. In some embodiments, the fin insulation structure extends between two opposite sidewalls of the butt joint isolation structure, and the fin insulation structure and the butt joint isolation structure extend in different directions. In some embodiments, the butt joint isolation structure covers multiple dummy fins adjacent to the fins, and the butt joint isolation structure is formed of a first material different from the second material forming these dummy fins. In some embodiments, the butt joint isolation structure covers multiple dummy fins adjacent to the fins, and the butt joint isolation structure is formed of the same material as these dummy fins. In some embodiments, the butt joint isolation structure is formed of a second dielectric material.

[0123] According to another embodiment, a method for manufacturing a semiconductor device is provided. This method includes providing a substrate; forming a fin-covered substrate; forming a plurality of seam isolation structures adjacent to the fins on a plurality of oppositely disposed sides of the fins; forming a plurality of active regions of at least two devices on the fins; and forming fin insulating structures disposed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structures extend through the fins and into the substrate, wherein the fin insulating structures include a first dielectric material, and wherein the seam isolation structures define a plurality of boundaries of the fin insulating structures on the sides of the fins.

[0124] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a plurality of self-aligned contact sacrificial material layers after forming the seam isolation structures and before forming the fin insulating structures, wherein the seam isolation structures are disposed between the self-aligned contact sacrificial material layers and the fin insulating structures; removing the self-aligned contact sacrificial material layers after forming the fin insulating structures; and performing a self-aligned contact process to form a plurality of contacts coupled to active regions of at least two devices. In some embodiments, forming the seam isolation structures includes positioning the seam isolation structures at a plurality of line ends of metal gate lines of the semiconductor device. In some embodiments, the fin insulating structures make direct contact between the seam isolation structures and the fin insulating structures. In some embodiments, the fin insulating structures extend between two opposite sidewalls of the seam isolation structures, and the fin insulating structures and the seam isolation structures extend in different directions. In some embodiments, the seam isolation structures cover a plurality of dummy fins adjacent to the fins, and the seam isolation structures are formed of a first material different from the second material forming the dummy fins. In some embodiments, the seam isolation structures cover a plurality of dummy fins adjacent to the fins, and the seam isolation structures are formed of the same material as the dummy fins. In some embodiments, these seam isolation structures are formed of a second dielectric material.

[0125] According to yet another embodiment, a method for manufacturing a semiconductor device is provided. This method includes providing a substrate; forming a fin-covered substrate; forming a plurality of active regions for a plurality of devices on the fins; forming a plurality of seam isolation structures adjacent to the fins on a plurality of opposing sides of the fins, wherein the seam isolation structures extend from shallow trench isolation within a location adjacent to the fins, wherein the seam isolation structures are formed of a first dielectric material; forming a plurality of gate structures between the active regions of the devices; forming fin insulating structures disposed to electrically isolate at least two of the active regions of the devices, wherein the fin insulating structures extend through the fins and into the substrate, wherein the fin insulating structures include a second dielectric material, wherein the seam isolation structures define a plurality of boundaries of the fin insulating structures on the sides of the fins; and forming a plurality of contacts electrically coupled to the active regions of the devices.

[0126] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a plurality of self-aligned contact sacrificial material layers after forming the seam isolation structures and before forming the fin insulating structures, wherein the seam isolation structures are disposed between the self-aligned contact sacrificial material layers and the fin insulating structures; and removing the self-aligned contact sacrificial material layers after forming the fin insulating structures, wherein forming the contacts includes performing a self-aligned contact process. In some embodiments, forming the seam isolation structures includes positioning the seam isolation structures at a plurality of line ends of metal gate lines of the semiconductor device. In some embodiments, the fin insulating structures bring the seam isolation structures into direct contact with the fin insulating structures. In some embodiments, the fin insulating structures extend between two opposite sidewalls of the seam isolation structures, and the fin insulating structures and the seam isolation structures extend in different directions.

[0127] According to another embodiment, a semiconductor device is provided, including a substrate, fins, a plurality of seam isolation structures, a plurality of active regions of at least two devices, and a fin insulating structure. The fins cover the substrate. The plurality of seam isolation structures are located adjacent to the fins on a plurality of oppositely disposed sides of the fins. The plurality of active regions of at least two devices are disposed on the fins. The fin insulating structure is configured to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a dielectric layer, and wherein the seam isolation structures define a plurality of boundaries of the fin insulating structure on the sides of the fins.

[0128] According to another embodiment, a semiconductor device is provided, including a substrate, fins, multiple active regions of multiple devices, multiple seam isolation structures, multiple gate structures, fin insulating structures, and multiple contacts. The fins cover the substrate. Multiple active regions of the multiple devices are disposed on the fins. Multiple seam isolation structures are disposed adjacent to the fins on multiple opposing sides of the fins, wherein the seam isolation structures extend from a shallow trench isolation within a location adjacent to the fins, and wherein the seam isolation structures include a first dielectric layer. Multiple gate structures are disposed between the active regions of the device. A fin insulating structure is disposed to electrically isolate at least two active regions in the device, wherein the fin insulating structure allows the seam isolation structure to directly contact the fin insulating structure, wherein the fin insulating structure includes a second dielectric layer, and wherein the seam isolation structure defines multiple boundaries of the fin insulating structure on the sides of the fins. Multiple contacts are electrically coupled to the active regions of the device.

[0129] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0130] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A fin covers the substrate and provides multiple active areas for at least two devices; A fin insulating structure is provided to electrically isolate the plurality of active regions of the at least two devices, wherein the fin insulating structure extends through the fin and into the substrate, wherein the fin insulating structure includes a dielectric layer; and A pair of seam isolation structures are located adjacent to the fin on multiple opposing sides of the fin, wherein the seam isolation structures define multiple boundaries of the fin insulation structure on the multiple sides of the fin.

2. The semiconductor device as claimed in claim 1, characterized in that, The joint isolation structure is located at multiple ends of a metal grid.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The fin insulation structure allows the butt joint isolation structure to be in direct contact with the fin insulation structure.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that, The fin insulation structure extends between the two opposite sidewalls of the butt joint isolation structure, and the fin insulation structure and the butt joint isolation structure extend in different directions.

5. A semiconductor device, characterized in that, include: A fin covers a substrate; Multiple seam isolation structures are located on multiple opposing sides of the fin adjacent to the fin; Multiple active regions of at least two devices are disposed on the fin; as well as A fin insulating structure is provided to electrically isolate the plurality of active regions of the at least two devices, wherein the fin insulating structure extends through the fin and into the substrate, wherein the fin insulating structure includes a dielectric layer, and wherein the plurality of seam isolation structures define a plurality of boundaries of the fin insulating structure on the plurality of sides of the fin.

6. The semiconductor device as claimed in claim 5, characterized in that, The plurality of seam isolation structures are located at the plurality of ends of a metal gate line of the semiconductor device.

7. The semiconductor device as claimed in claim 5 or 6, characterized in that, The fin insulation structure allows the plurality of seam isolation structures to be in direct contact with the fin insulation structure.

8. The semiconductor device as claimed in claim 5 or 6, characterized in that, The fin insulation structure extends between two opposite sidewalls of the plurality of seam isolation structures, and the fin insulation structure and the plurality of seam isolation structures extend in different directions.

9. A semiconductor device, characterized in that, include: A fin covers a substrate; Multiple active regions of multiple devices are disposed on this fin; Multiple seam isolation structures are disposed on multiple opposing sides of the fin adjacent to the fin, wherein the multiple seam isolation structures extend from a shallow trench isolation in a location adjacent to the fin, and wherein the multiple seam isolation structures include a first dielectric layer. Multiple gate structures are disposed between the multiple active regions of the multiple devices; A fin insulating structure is provided to electrically isolate at least two of the plurality of active regions of the plurality of devices, wherein the fin insulating structure allows the plurality of seam isolation structures to be in direct contact with the fin insulating structure, wherein the fin insulating structure includes a second dielectric layer, wherein the plurality of seam isolation structures define a plurality of boundaries of the fin insulating structure on the plurality of sides of the fin. as well as Multiple contacts are electrically coupled to the multiple active areas of the multiple devices.

10. The semiconductor device as claimed in claim 9, characterized in that, Forming the plurality of seam isolation structures includes positioning the plurality of seam isolation structures at multiple ends of a metal gate line of the semiconductor device.

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