Solar cells, photovoltaic modules and laser patterning

Abstract

This application relates to the field of photovoltaic solar cell technology, and discloses a solar cell, a photovoltaic module, and a laser pattern. The solar cell includes: a semiconductor wafer having a first surface; a polycrystalline silicon layer disposed on the first surface in a grid-like structure; and metal grid lines disposed on the side of the polycrystalline silicon layer facing away from the first surface. In this application, the grid-like polycrystalline silicon layer replaces the finger-like or strip-like structures in the prior art, allowing the trenched area to change from multiple parallel strips to interlaced rectangles. This enables charge carriers in the trenched area to not only travel along the periphery to the nearest polycrystalline silicon layer, but also significantly reduces the carrier transport path, decreases series resistance, and improves solar cell efficiency.

Description

Technical Field

[0001] This application relates to the field of photovoltaic solar cell technology, and more particularly to a solar cell, photovoltaic module, and laser pattern. Background Technology

[0002] For TOPCon (Tunnel Oxide Passivated Contact) cells, the passivation effect of the back silicon oxide tunnel layer plus polycrystalline silicon structure is very obvious, and the turn-on voltage is greatly improved. However, the polycrystalline silicon layer has a large proportion of long-wavelength parasitic absorption, resulting in a large current loss. The back parasitic absorption can be reduced and the cell efficiency can be improved by using polyfinger structure technology (polycrystalline silicon patterned finger structure technology).

[0003] However, existing polyfinger patterns are all parallel designs, forming finger-like or strip-like shapes. In the slotted region, the transport path of charge carriers is longer, increasing series resistance and affecting the improvement of battery efficiency. Utility Model Content

[0004] This application discloses a solar cell that replaces the finger-shaped or strip-shaped structure in the prior art with a grid-shaped polycrystalline silicon layer. This changes the multiple parallel strips in the prior art into interlaced rectangles, allowing the charge carriers in the grid area to be transferred to the nearest polycrystalline silicon layer along the periphery. This significantly reduces the transport path of the charge carriers, reduces series resistance, and improves the efficiency of the solar cell.

[0005] To achieve the above objectives, according to a first aspect disclosed in this application, a solar cell is provided, comprising: a semiconductor wafer having a first surface;

[0006] A polycrystalline silicon layer is disposed on the first surface, and the polycrystalline silicon layer is in the form of a grid structure laid on the first surface;

[0007] Metal grid lines are disposed on the side of the polysilicon layer facing away from the first surface. A full-surface polysilicon layer can be formed on the first surface first, and then grooves can be cut into the surface of the polysilicon layer to create a grid-like structure. The polysilicon layer has relatively grooved and non-grooved regions. The grooved regions are more conducive to the formation of charge carriers. In this embodiment, the area of ​​each grooved region is smaller than that of the parallel long grooved regions in a polyfinger pattern, allowing charge carriers in the grooved regions to have shorter transport paths, reducing series resistance and improving solar cell efficiency.

[0008] As an optional implementation, the polycrystalline silicon layer includes:

[0009] Multiple first linear bodies, the first linear bodies being arranged along a first direction;

[0010] Multiple second lines, the second lines being arranged along a second direction;

[0011] In this design, multiple second lines are disposed between each pair of adjacent first lines, and the first and second lines intersect to form a grid. The area enclosed by the grid is the slotted region, while each first and second line constitutes a non-slotted region. Compared to the existing technology where slotted regions are long strips extending in one direction, the slotted region in this application is smaller, resulting in a shorter carrier transport path and lower series resistance, thus improving the efficiency of the solar cell.

[0012] As an optional implementation, the second lines located on both sides of the first line are staggered in the first direction. Alternating left and right arrangements along the first direction a allow the second lines to cover a larger area, which is more conducive to carrier collection.

[0013] As an optional implementation, the second lines between two adjacent first lines are parallel to each other and perpendicular to the first lines. This makes the shapes of the non-grooved regions substantially the same, allowing charge carriers in each region to have substantially the same transport path, resulting in more uniform and efficient charge carrier transport, which is beneficial for improving the efficiency of solar cells.

[0014] As an optional implementation, the spacing between each of the second lines intersecting the same first line is the same, and the spacing between each pair of adjacent second lines between two adjacent first lines is also the same. This ensures that the size and shape of each non-grooved region are substantially the same, allowing charge carriers in each region to have substantially the same transport path, resulting in more uniform and efficient charge carrier transport, which is beneficial for improving the efficiency of solar cells.

[0015] As an optional implementation, the width of the first line body is the same as the width of the second line body, and both are 5um to 1000um.

[0016] As an optional implementation, multiple solder strips are provided, each corresponding to a plurality of second wires arranged along the second direction. The metal grid lines on each second wire are electrically connected to the solder strips. The staggered feature formed by the second wires allows for covering a larger area with fewer metal grid lines. In other words, the staggered arrangement of the second wires not only ensures normal current collection but also saves half the number of grid lines along the second direction b, reducing production costs.

[0017] As an optional implementation, the solar cell further includes:

[0018] An alumina layer is disposed on the surface of the first surface and the surface of the polycrystalline silicon layer;

[0019] A silicon nitride layer is disposed on the surface of the alumina layer;

[0020] The metal grid lines are disposed on the surface of the silicon nitride layer. The aluminum oxide layer effectively passivates the semiconductor wafer surface, reducing carrier recombination at the surface and improving the open-circuit voltage and photoelectric conversion efficiency of the solar cell. As a good passivation material, the aluminum oxide layer can reduce the surface state density, suppress nonradiative recombination of carriers, and enhance cell performance. The silicon nitride layer, disposed on the surface of the aluminum oxide layer, has excellent anti-reflection properties, which can reduce light reflection entering the cell, improve light absorption efficiency, and thus increase the short-circuit current and photoelectric conversion efficiency of the cell. The silicon nitride layer also has good insulation properties and chemical stability, effectively protecting the aluminum oxide layer and the polycrystalline silicon layer, improving the stability and durability of the cell.

[0021] According to an embodiment of the second aspect of this application, a photovoltaic module is provided, including the aforementioned solar cell.

[0022] According to an embodiment of a third aspect of this application, a laser pattern is provided, comprising:

[0023] Multiple sets of slotting paths are spaced apart along a first direction. Each set of slotting paths includes multiple rectangular slotting paths spaced apart along a second direction, and the rectangular slotting paths in two adjacent sets of slotting paths are staggered in the first direction.

[0024] The rectangular slotted paths are used to form the mesh holes of the polysilicon layer. The spacing between two adjacent groups of rectangular slotted paths forms the first line body, and the spacing structure between the slotted paths in the same group forms the second line body.

[0025] The second direction is perpendicular to the first direction.

[0026] Compared with the prior art, the beneficial effects of this application are:

[0027] The solar cell provided in this application embodiment has a polycrystalline silicon layer disposed on the first surface of a semiconductor wafer. The polycrystalline silicon layer has a grid-like structure laid on the first surface, meaning it has grid-like non-grooved regions and multiple grooved regions separated by the grid structure. This shortens the path for charge carriers in the grooved regions to reach the non-grooved regions, allowing them to reach the non-grooved regions more quickly and with less loss, thereby improving the solar cell's charge carrier collection efficiency and ultimately its efficiency. Compared to finger-shaped or strip-shaped polycrystalline silicon layers, the grid-like structure of the polycrystalline silicon layer in this application embodiment shortens the transport path of charge carriers in the grooved regions, reduces series resistance, and improves the solar cell's efficiency. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a solar cell in which the polycrystalline silicon layer is in the form of fingers or strips, as disclosed in the embodiments of this application.

[0030] Figure 2 This is a schematic diagram of the structure of a solar cell with a grid-like polycrystalline silicon layer as disclosed in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of the cross-sectional structure of the solar cell disclosed in the embodiments of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100' - Semiconductor wafer; 200' - Polysilicon layer; 21' - Grooved region; 100 - Semiconductor wafer; 200 - Polysilicon layer; 21 - First line; 22 - Second line; 23 - Grooved region; 300 - Alumina layer; 400 - Silicon nitride layer; 500 - Metal gate line; a - First direction; b - Second direction. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In this application, the terms "upper," "lower," "top," "bottom," "inner," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0036] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0037] Furthermore, the terms "set up," "equipped with," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0038] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0039] A solar cell, also known as a solar cell or photovoltaic cell, is a semiconductor device that directly converts sunlight into electrical energy. It utilizes the photovoltaic effect to achieve energy conversion and is the core component of solar power generation. Its working principle is based on the photovoltaic effect of semiconductor materials. When sunlight shines on the surface of a solar cell, the energy of the photons excites electrons in the semiconductor material, causing them to jump from the valence band to the conduction band, thus generating electron-hole pairs. These electrons and holes separate under the influence of a built-in electric field; electrons move towards the negative electrode of the cell, and holes move towards the positive electrode, thereby creating a potential difference across the two ends of the cell and generating a current.

[0040] The core material of a solar cell is the solar cell wafer. The wafer is made from silicon wafers through a series of processes to transform them into a power-generating material. The current generated by the silicon wafer is conducted through silver grid lines printed on it; these grid lines are generally called the electrodes of the solar cell. The semiconductor wafer, as the foundation of the wafer, is usually made of silicon and is classified as P-type or N-type semiconductors. When sunlight shines on the semiconductor wafer, photon energy excites electron-hole pairs, generating photogenerated charge carriers. These photogenerated charge carriers separate under the influence of a built-in electric field, with electrons and holes collected by the N-type and P-type semiconductors, respectively. The grid lines collect and transport these charge carriers.

[0041] For TOPCon (Tunnel Oxide Passivated Contact) cells, the passivation effect of the backside silicon oxide tunnel layer plus polycrystalline silicon structure is very significant, resulting in a high on-state voltage improvement. However, the polycrystalline silicon layer exhibits a high proportion of long-wavelength parasitic absorption, leading to substantial current loss. While polyfinger structure technology (a patterned finger structure process for polycrystalline silicon) can reduce backside parasitic absorption and improve solar cell efficiency, existing polyfinger patterns are all parallel designs. These polyfinger patterns form finger-like or strip-like shapes, resulting in longer carrier transport paths in the trenched regions, increased series resistance, and hindering efficiency improvements.

[0042] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a solar cell with a finger-shaped or strip-shaped polycrystalline silicon layer as disclosed in the embodiments of this application. In existing TOPCon cells, the polycrystalline silicon layer 200' covering the surface of the semiconductor wafer 100' is a finger-shaped or strip-shaped structure. There are multiple parallel slotted regions 21' between the polycrystalline silicon layer 200'. Although the slotted regions 21' can reduce parasitic absorption on the back side and improve the efficiency of the solar cell, the transport path for charge carriers in the slotted regions 21' to move to the non-slotted regions and collect on the metal grid lines is relatively long. In particular, charge carriers located in the middle of the slotted regions 21' cannot quickly reach the metal grid lines, resulting in increased series resistance and affecting the improvement of cell efficiency.

[0043] Based on this, this application provides a solar cell that replaces the finger-shaped or strip-shaped structure in the prior art with a grid-shaped polycrystalline silicon layer. This changes the slotted area from multiple parallel strips in the prior art to interlaced rectangles, allowing the charge carriers in the slotted area to not only be transferred along the periphery to the nearest polycrystalline silicon layer, but also significantly reducing the transport path of the charge carriers, decreasing series resistance, and improving the efficiency of the solar cell.

[0044] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0045] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a solar cell with a grid-like polycrystalline silicon layer disclosed in an embodiment of this application. The embodiment of this application discloses a solar cell including: a semiconductor wafer 100, a polycrystalline silicon layer 200, and metal grid lines 500. The semiconductor wafer 100 has a first surface; the polycrystalline silicon layer 200 is disposed on the first surface, and the polycrystalline silicon layer 200 has a grid-like structure laid on the first surface; the metal grid lines 500 are disposed on the side of the polycrystalline silicon layer 200 facing away from the first surface.

[0046] Specifically, semiconductor wafer 100 can be a silicon wafer. Polycrystalline silicon wafers are made by fusing multiple single crystal particles together. The photoelectric conversion efficiency of polycrystalline silicon solar cells is slightly lower, but the material preparation is simple and the cost is low, so they are widely used in large-scale applications such as photovoltaic power plants.

[0047] The semiconductor wafer 100 can be in direct contact with the polysilicon layer 200. The polysilicon layer 200 can be tightly bonded to the semiconductor wafer 100 through its grid structure to form an electrical connection, enabling photogenerated carriers to be transported between the two. The metal gate line 500 is located above the polysilicon layer 200, which can collect carriers and provide an outlet path for the carriers. Moreover, the metal gate line 500 can avoid direct contact with the semiconductor wafer 100, thus preventing the metal gate line 500 from corroding the semiconductor wafer 100.

[0048] The polysilicon layer 200 proposed in this application embodiment has a grid structure, which can significantly reduce the transport path of charge carriers. The grid structure in this application is a grid pattern formed by the intersection of lines in two directions, specifically a grid pattern formed by the intersection of horizontal and vertical lines.

[0049] In actual production, a full-surface polycrystalline silicon layer 200 can be first set on the first surface, and then grooves can be made on the surface of the polycrystalline silicon layer 200 to make the polycrystalline silicon layer 200 into a grid structure. The polycrystalline silicon layer 200 has relatively grooved regions 23 and non-grooved regions. The grooved regions 23 are more conducive to the formation of charge carriers. In the embodiments of this application, the area of ​​each grooved region 23 is smaller than that of each parallel long grooved region 23 in the polyfinger pattern. This allows the charge carriers in the grooved regions 23 to have a smaller transport path, which can reduce series resistance and improve the efficiency of solar cells.

[0050] According to an embodiment of the present invention, a polycrystalline silicon layer 200 is disposed on the first surface of a semiconductor wafer 100. The polycrystalline silicon layer 200 has a grid-like structure laid on the first surface, meaning that the polycrystalline silicon layer 200 on the first surface has grid-like non-grooved regions and multiple grooved regions 23 separated by the grid-like structure. This shortens the path for charge carriers in the grooved regions 23 to reach the non-grooved regions, allowing charge carriers in the grooved regions 23 to reach the non-grooved regions more quickly and with less loss, thereby improving the collection efficiency of charge carriers in the solar cell and thus improving the efficiency of the solar cell. Compared to finger-shaped or strip-shaped polycrystalline silicon layers 200, the grid-like structure of the polycrystalline silicon layer 200 in this embodiment of the present application can shorten the transport path of charge carriers in the grooved regions 23, reduce series resistance, and improve the efficiency of the solar cell.

[0051] Combination Figure 2 In some embodiments, the polysilicon layer 200 includes: a plurality of first lines 21 and a plurality of second lines 22, wherein the first lines 21 are arranged along a first direction a; the second lines 22 are arranged along a second direction b; wherein a plurality of second lines 22 are provided between each pair of adjacent first lines 21, and the first lines 21 and the second lines 22 intersect to form a mesh hole.

[0052] Specifically, the polycrystalline silicon layer 200 with a grid structure has multiple first lines 21 and multiple second lines 22. The first lines 21 can be long lines, with a length along the first direction a that is equivalent to the entire semiconductor wafer 100. The second lines 22 can be short lines. Multiple second lines 22 are provided between each pair of adjacent first lines 21. Multiple grid holes can be formed by the first lines 21 and the second lines 22. The first surface of the semiconductor wafer 100 is exposed through the grid holes. The area enclosed by the grid holes is the slotted area 23. Each first line 21 and each second line 22 is a non-slotted area. Compared with the slotted areas 23 in the prior art, which are all long strips extending in one direction, the slotted area 23 in this application has a smaller area, a shorter carrier transport path, and lower series resistance, which can improve the efficiency of the solar cell.

[0053] Combination Figure 2 In some embodiments, in the first direction a, the second lines 22 located on both sides of the first line 21 are staggered.

[0054] Specifically, each first line body 21 has second lines body 22 intersecting it on both sides along the second direction b, and these second lines body 22 are staggered along the first direction a, i.e. Figure 2 As shown, the alternating arrangement of the second line body 22 along the first direction a allows it to cover a larger area, which is more conducive to the collection of charge carriers.

[0055] Combination Figure 2In some embodiments, each of the second lines 22 between two adjacent first lines 21 is parallel to each other, and the second lines 22 are perpendicular to the first lines 21.

[0056] Specifically, each of the second lines 22 between two adjacent first lines 21 is parallel to each other and perpendicular to the first lines 21, so that each non-grooved region enclosed by the first lines 21 and the second lines 22 is rectangular, making the shape of each non-grooved region basically the same, so that the charge carriers in each region can have basically the same transmission path, making the transmission of charge carriers more uniform and efficient, which is conducive to improving the efficiency of solar cells.

[0057] Combination Figure 2 In some embodiments, the spacing between each second line body 22 intersecting the same first line body 21 is the same, and the spacing between each pair of adjacent second line bodies 22 between two adjacent first line bodies 21 is the same.

[0058] Specifically, the spacing between the second bodies 22 that intersect with the same first body 21 is the same, and the spacing between each pair of adjacent second bodies 22 between two adjacent first bodies 21 is the same. This makes the size and shape of each non-grooved region basically the same, so that the charge carriers in each region can have basically the same transmission path, making the transmission of charge carriers more uniform and efficient, which is beneficial to improving the efficiency of solar cells.

[0059] Combination Figure 2 In some embodiments, the width of the first line body 21 is the same as the width of the second line body 22, and both are 5um to 1000um.

[0060] Specifically, each metal grid line 500 can have the same diameter. The metal grid lines 500 are set on the first line body 21 and the second line body 22. The charge carriers are collected and transported through the metal grid lines 500. The width of the first line body 21 and the second line body 22 is sufficient to accommodate the metal grid lines 500.

[0061] Each mesh hole, i.e. each slotted area 23, can have a width of 5~5000um and a length of 5~10000um. The length of the first wire 21 can be 5~10000um, and the length of the second wire 22 can be 5~10000um.

[0062] Combination Figure 2 In some embodiments, the solar cell further includes a plurality of solder strips, which are configured in one-to-one correspondence with a plurality of second wires 22 arranged along the second direction b.

[0063] Specifically, the solder strip can help fix the metal grid line 500 and cooperate with each of the second wire bodies 22. The metal grid line 500 set on each second wire body 22 is electrically connected to the solder strip. The staggered feature formed by the second wire bodies 22 can cover more area with fewer metal grid lines 500. That is, the staggered arrangement of the second wire bodies 22 can not only ensure normal current collection, but also save half of the grid lines along the second direction b, reducing production costs.

[0064] Combination Figure 3 , Figure 3 This is a schematic cross-sectional view of the solar cell disclosed in an embodiment of this application. In some embodiments, the solar cell further includes: an aluminum oxide layer 300 and a silicon nitride layer 400, wherein the aluminum oxide layer 300 is disposed on the surface of the first surface and the surface of the polycrystalline silicon layer 200; the silicon nitride layer 400 is disposed on the surface of the aluminum oxide layer 300; wherein, metal grid lines 500 are disposed on the surface of the silicon nitride layer 400.

[0065] Specifically, the surface of the polycrystalline silicon layer 200 is the surface relatively exposed to air after the polycrystalline silicon is deposited on the first surface of the semiconductor wafer 100. The aluminum oxide layer 300 and the silicon nitride layer 400 are sequentially covered on the surface of the polycrystalline silicon layer 200. The aluminum oxide layer 300 effectively passivates the surface of the semiconductor wafer 100, reducing carrier recombination on the surface and improving the open-circuit voltage and photoelectric conversion efficiency of the solar cell. As a good passivation material, the aluminum oxide layer 300 reduces the surface state density, suppresses non-radiative recombination of carriers, and enhances cell performance. The silicon nitride layer 400 is disposed on the surface of the aluminum oxide layer 300 and has excellent anti-reflection properties, reducing light reflection entering the cell, improving light absorption efficiency, and thus increasing the short-circuit current and photoelectric conversion efficiency of the cell. The silicon nitride layer 400 also has good insulation properties and chemical stability, effectively protecting the aluminum oxide layer 300 and the polycrystalline silicon layer 200, improving cell stability and durability.

[0066] Understandably, in combination Figure 3 , Figure 3 The unshaded portion of the polysilicon layer 200 that is selected is the first line body 21 arranged along the first direction a, which can be directly observed in the cross-sectional structure, while the shaded portion of the polysilicon layer 200 is the second line body 22 arranged along the second direction b, which is cut by the cross-section.

[0067] This application discloses a photovoltaic module, including the aforementioned solar cell.

[0068] Specifically, photovoltaic modules with the aforementioned solar cells can reduce the carrier transport path, decrease series resistance, and improve efficiency through a grid-structured polycrystalline silicon layer 200.

[0069] This application discloses a laser pattern, including: multiple sets of slotted paths spaced apart along a first direction a, each set of slotted paths including multiple rectangular slotted paths spaced apart along a second direction b, and the rectangular slotted paths in adjacent sets of slotted paths are staggered in the first direction a; wherein, the rectangular slotted paths are used to form mesh holes in a polysilicon layer 200, the interval between adjacent sets of rectangular slotted paths forms a first line 21, and the interval structure between slotted paths in the same set forms a second line 22.

[0070] Wherein, the second direction b is perpendicular to the first direction a.

[0071] Specifically, the grooved area 23 on the solar cell provided in this application can be processed by the laser pattern provided in this application. In the laser pattern provided in this application, the grooved path corresponds to the grid holes of the polycrystalline silicon layer 200, that is, it corresponds to the grooved area 23 of the solar cell.

[0072] In this embodiment, the solar cell uses a grid-like polycrystalline silicon layer 200 instead of the finger-like or strip-like structure in the prior art. Compared to the strip-shaped slotted regions 23 formed between the finger-like or strip-like polycrystalline silicon layers 200 in the prior art, the slotted regions 23 in this application are replaced by multiple shorter, intersecting rectangular regions. This is equivalent to retaining multiple polycrystalline silicon layer lines 200 perpendicular to the finger-like structure within the strip-like regions of the prior art, reducing the area of ​​each slotted region 23. This provides a shorter path for charge carriers in the slotted regions 23 to reach the polycrystalline silicon layer 200, enabling them to reach the metal grid lines 500 more quickly. This significantly reduces the carrier transport path, decreases series resistance, and improves the solar cell efficiency. Furthermore, the intersecting arrangement of the slotted regions 23 maximizes the coverage of the collection area while saving on the required metal grid lines 500, thus reducing costs.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A solar cell, characterized in that, include: A semiconductor wafer (100) having a first surface; A polycrystalline silicon layer (200) is disposed on the first surface, and the polycrystalline silicon layer (200) is in the form of a grid structure laid on the first surface; Metal gate line (500) is disposed on the side of the polysilicon layer (200) away from the first surface.

2. The solar cell according to claim 1, characterized in that, The polysilicon layer (200) includes: Multiple first line bodies (21) are arranged along a first direction (a); Multiple second line bodies (22) are arranged along a second direction (b); In this configuration, a plurality of second lines (22) are provided between each pair of adjacent first lines (21), and the first lines (21) and the second lines (22) intersect to form a grid hole.

3. The solar cell according to claim 2, characterized in that, In the first direction (a), the second lines (22) located on both sides of the first line (21) are staggered.

4. The solar cell according to claim 3, characterized in that, Each of the second lines (22) between two adjacent first lines (21) is parallel to each other, and the second lines (22) are perpendicular to the first lines (21).

5. The solar cell according to claim 4, characterized in that, The spacing between each second line body (22) intersecting the same first line body (21) is the same, and the spacing between each pair of adjacent second line bodies (22) between two adjacent first line bodies (21) is the same.

6. The solar cell according to claim 2, characterized in that, The width of the first line body (21) is the same as the width of the second line body (22), and both are 5um to 1000um.

7. The solar cell according to claim 2, characterized in that, The solar cell also includes: Multiple solder strips are provided in a one-to-one correspondence with multiple second lines (22) arranged along the second direction (b).

8. The solar cell according to claim 1, characterized in that, The solar cell also includes: An aluminum oxide layer (300) is disposed on the surface of the first surface and the surface of the polycrystalline silicon layer (200); A silicon nitride layer (400) is disposed on the surface of the aluminum oxide layer (300); The metal gate line (500) is disposed on the surface of the silicon nitride layer (400).

9. A photovoltaic module, characterized in that, include: The solar cell as described in any one of claims 1-8.

10. A laser pattern applied to a solar cell as described in any one of claims 1-8, characterized in that, include: Multiple sets of slotting paths are spaced apart along a first direction (a), each set of slotting paths includes multiple rectangular slotting paths spaced apart along a second direction (b), and the rectangular slotting paths in two adjacent sets of slotting paths are staggered in the first direction (a). The rectangular slotting path is used to form the mesh holes of the polysilicon layer (200), the interval between two adjacent groups of rectangular slotting paths forms a first line body (21), and the interval structure between the slotting paths in the same group forms a second line body (22). Wherein, the second direction (b) is perpendicular to the first direction (a).

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