Display motherboard, display panel and display device

Abstract

A display motherboard, display panel, and display device are provided to facilitate narrow bezels. The display motherboard includes: a substrate, a plurality of signal contact pad groups disposed on the substrate, a plurality of first-type traces, and at least one test contact pad group. The substrate includes a plurality of substrate regions and a cut-out region surrounding the substrate regions. The substrate regions include: a display region and a first bezel region located on one side of the display region along a first direction. The first bezel region includes: at least one signal access region. Each signal access region is provided with at least one signal contact pad group. Each group of first-type traces includes a plurality of first-type traces extending from the substrate region to the cut-out region, and each first-type trace is connected to at least one signal contact pad. At least one test contact pad group is located in the cut-out region, and each test contact pad group is configured to provide test signals to signal contact pads in at least two substrate regions through at least two groups of first-type traces.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, the field of display technology, and particularly to a display motherboard, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This utility model provides a display motherboard, a display panel, and a display device to facilitate narrowing of the bezel.

[0005] On one hand, this embodiment provides a display motherboard, including: a substrate, a plurality of signal contact pad groups disposed on the substrate, a plurality of first-type traces, and at least one test contact pad group. The substrate includes a plurality of substrate regions and a cut-out region surrounding the substrate regions. The substrate regions include: a display region and a first border region located on one side of the display region along a first direction. The first border region includes: at least one signal access region. Each signal contact pad group includes a plurality of signal contact pads, and each signal access region is provided with at least one signal contact pad group. Each group of first-type traces includes a plurality of first-type traces extending from the substrate region to the cut-out region, and each first-type trace is connected to at least one signal contact pad. At least one test contact pad group is located in the cut-out region; each test contact pad group includes a plurality of test contact pads, and each test contact pad group is configured to provide test signals to signal contact pads in at least two substrate regions through at least two groups of first-type traces. Each test contact pad group is located on the same side of the at least two connected substrate regions along a direction.

[0006] In some exemplary embodiments, the test contact pad group is located on the same side of the at least two connected substrate regions along the second direction, and a plurality of test contact pads in the test contact pad group are arranged along the first direction; the first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction intersect.

[0007] In some exemplary embodiments, the display motherboard further includes: a composite insulating layer located in the cutting region; the cutting region includes: a cutting channel region surrounding the substrate region, the composite insulating layer having a plurality of cutting grooves in the cutting channel region; in the cutting channel region, the orthographic projection of the plurality of first-type traces on the substrate is located within the orthographic projection range of the composite insulating layer on the substrate.

[0008] In some exemplary embodiments, in the cutting channel region, the plurality of first-type traces are spaced apart from the plurality of cutting slots.

[0009] In some exemplary embodiments, the display motherboard further includes: at least one test circuit located in the cut area, a plurality of second-type traces, and a plurality of third-type traces. The at least one test circuit is located on one side of the substrate area along the first direction; the at least one test circuit is configured to be connected to a plurality of signal contact pads in the substrate area via the plurality of second-type traces, and is also configured to be connected to the test contact pad group via the plurality of third-type traces.

[0010] In some exemplary embodiments, the plurality of second-type traces and the plurality of first-type traces are in the same layer, or the film layer containing the plurality of second-type traces is located on the side of the film layer containing the plurality of first-type traces closer to the substrate.

[0011] In some exemplary embodiments, the plurality of second-type traces are located in the gate metal layer or the source / drain metal layer.

[0012] In some exemplary embodiments, the display motherboard further includes: a composite insulating layer located in the cutting region; the cutting region includes: a cutting channel region surrounding the substrate region; in the cutting channel region, the orthographic projection of the plurality of second-type traces on the substrate is located within the orthographic projection range of the composite insulating layer on the substrate.

[0013] In some exemplary embodiments, the composite insulating layer includes: at least one inorganic insulating layer and at least one organic insulating layer; the cutting groove has a first edge close to the signal access area and a second edge away from the signal access area; the maximum distance between the boundaries of adjacent stacked inorganic and organic insulating layers of the composite insulating layer at the first edge is less than the maximum distance between the boundaries at the second edge.

[0014] In some exemplary embodiments, the display motherboard further includes: an auxiliary conductive layer located on the side of the plurality of signal contact pads away from the substrate; the signal contact pads include a plurality of pad layers stacked along a direction away from the substrate; the auxiliary conductive layer covers the edge of the pad layer of the plurality of signal contact pads furthest from the substrate, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the pad layer of the plurality of signal contact pads furthest from the substrate on the substrate.

[0015] In some exemplary embodiments, the first border area further includes: an encapsulation area located between the display area and the signal access area; the display motherboard further includes: a power line located in the encapsulation area; the power line is connected to at least one signal contact pad; the auxiliary conductive layer covers the edge of the power line, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

[0016] In some exemplary embodiments, the display motherboard further includes a plurality of light-emitting elements located in the display area of ​​the substrate region, the light-emitting elements including a first electrode, an organic light-emitting layer and a second electrode disposed sequentially; the auxiliary conductive layer and the first electrode of the light-emitting element are of the same layer structure.

[0017] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of signal contact pads disposed on the substrate, and an auxiliary conductive layer. The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including: at least one signal access area; the plurality of signal contact pads are located in the signal access area. The auxiliary conductive layer is located on the side of the plurality of signal contact pads away from the substrate; the auxiliary conductive layer covers the edge of the pad layer of the plurality of signal contact pads furthest from the substrate, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the pad layer of the plurality of signal contact pads furthest from the substrate on the substrate.

[0018] In some exemplary embodiments, the first border area further includes: an encapsulation area located between the display area and the signal access area; the display panel further includes: a power line located in the encapsulation area; the power line is connected to at least one signal contact pad; the auxiliary conductive layer covers the edge of the power line, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

[0019] In some exemplary embodiments, the display panel further includes a plurality of light-emitting elements located in the display area, each light-emitting element comprising a first electrode, a light-emitting functional layer, and a second electrode disposed sequentially; the auxiliary conductive layer is of the same layer structure as the first electrode of the light-emitting element.

[0020] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0021] The display motherboard provided in this embodiment, by placing the test contact pad group outside the substrate area and having multiple substrate areas share one test contact pad group, can facilitate the narrowing of the display panel bezel and reduce manufacturing costs.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0024] Figure 1 This is a partial plan view of the display motherboard according to at least one embodiment of the present invention; Figure 2 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention; Figure 3 This is another partial plan view of the display motherboard according to at least one embodiment of the present invention; Figure 4 for Figure 1 A magnified view of a portion of the central region S1; Figure 5 for Figure 4 A partial cross-sectional view of the central region along the QQ' direction; Figure 6 for Figure 4 A partial cross-sectional view of the central region along the PP' direction; Figure 7 This is a partial planar schematic diagram of the cutting groove according to at least one embodiment of the present invention; Figure 8 for Figure 7 A partial cross-sectional view along the RR' direction; Figure 9 for Figure 1 A magnified view of a portion of the central region S2; Figure 10 for Figure 1 Another enlarged view of a portion of the central region S2; Figure 11 This is a schematic diagram illustrating a black line display defect that occurs during the manufacturing process of a display panel. Figure 12 This is a partial schematic diagram of the first border region of at least one embodiment of the present invention; Figure 13 This is an example diagram of the first border area of ​​at least one embodiment of the present invention; Figure 14 for Figure 13 A partial cross-sectional view along the VV' direction; Figure 15 This is another example diagram of the first border region of at least one embodiment of the present invention; Figure 16 for Figure 15 A partial cross-sectional view along the UU' direction; Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present invention. Detailed Implementation

[0025] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this utility model. Therefore, this utility model should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this utility model can be arbitrarily combined with each other.

[0026] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, one aspect of the invention is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of the invention is not limited to the shapes or values ​​shown in the drawings.

[0027] The ordinal numbers "first," "second," and "third" used in this specification are provided to avoid confusion among the constituent elements, not to limit the quantity. In this utility model, "multiple" refers to two or more items.

[0028] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0029] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this invention according to the specific circumstances.

[0030] In this specification, "connection" includes "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0031] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0032] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0033] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0034] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0035] In this invention, "approximately" and "about" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this invention, "same" can include cases where the index values ​​differ by no more than 10%.

[0036] In this invention, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this invention, "A extends along direction B" refers to "the main part of A extends along direction B".

[0037] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at approximately the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this invention refers to the shape of the orthographic projection of A onto the substrate.

[0038] To better meet people's needs for various functions and a better screen experience, narrowing the bezels has become increasingly important in the design and research of OLED display devices.

[0039] This embodiment provides a display motherboard, a display panel, and a display device, which can facilitate narrow bezel design.

[0040] This embodiment provides a display motherboard, including: a substrate, a plurality of signal contact pad groups disposed on the substrate, a plurality of first-type traces, and at least one test contact pad group. The substrate includes a plurality of substrate regions and a cut-out region surrounding the substrate regions. The substrate regions include: a display region and a first border region located on one side of the display region along a first direction. The first border region includes: at least one signal access region. Each signal contact pad group includes a plurality of signal contact pads, and each signal access region is provided with at least one signal contact pad group. Each group of first-type traces includes a plurality of first-type traces extending from the substrate region to the cut-out region, and each first-type trace is connected to at least one signal contact pad. At least one test contact pad group is located in the cut-out region; each test contact pad group includes a plurality of test contact pads, and each test contact pad group is configured to provide test signals to signal contact pads in at least two substrate regions through at least two groups of first-type traces. Each test contact pad group is located on the same side of the at least two connected substrate regions along a one-way direction.

[0041] The display motherboard provided in this embodiment, by placing the test contact pad group outside the substrate area and having multiple substrate areas share one test contact pad group, can facilitate the narrowing of the display panel bezel and reduce manufacturing costs.

[0042] In some exemplary embodiments, the display motherboard may further include: a composite insulating layer located in a cutting region; the cutting region includes: a cutting track region surrounding a substrate region, the composite insulating layer having multiple cutting grooves in the cutting track region; in the cutting track region, the orthographic projections of the multiple first-type traces onto the substrate may be located within the orthographic projection range of the composite insulating layer onto the substrate. In other words, in the cutting track region, the orthographic projections of the multiple first-type traces onto the substrate and the orthographic projections of the multiple cutting grooves onto the substrate may not overlap. In some examples, in the cutting track region, the multiple first-type traces and the multiple cutting grooves may be spaced apart. This example, by retaining the composite insulating layer at the first-type traces, can help reduce the step difference caused by the cutting grooves to the first-type traces, avoiding short circuits or open circuits in the first-type traces.

[0043] In some exemplary embodiments, the display motherboard may further include: at least one test circuit located in the cut area, a plurality of second-type traces, and a plurality of third-type traces. The at least one test circuit may be located on one side of the substrate area along a first direction; the at least one test circuit is configured to be connected to a plurality of signal contact pads in the substrate area via the plurality of second-type traces, and further configured to be connected to a group of test contact pads via the plurality of third-type traces. This example, by placing the test circuit outside the substrate area, can further facilitate a narrower bezel design for the display panel.

[0044] In some exemplary embodiments, the composite insulating layer may include at least one inorganic insulating layer and at least one organic insulating layer. The cut groove of the composite insulating layer has a first edge near the signal access region and a second edge away from the signal access region. The maximum distance between the boundaries of adjacent stacked inorganic and organic insulating layers at the first edge is less than the maximum distance between their boundaries at the second edge. This example, by flattening the step of the composite insulating layer at the second edge away from the signal access region, can help reduce material residue in the metal film layer prepared after the composite insulating layer and improve problems such as short circuits in the traces caused by this.

[0045] The following examples illustrate the solution of this embodiment. In some examples, during the fabrication of the display panel, a display motherboard is first fabricated, and then the display motherboard is divided into multiple display panels, each of which can be used to form a single display device.

[0046] Figure 1This is a partial plan view of the display motherboard according to at least one embodiment of the present invention. Figure 1 The illustration primarily depicts two complete substrate regions and partial areas of two other substrate regions included in the display motherboard 10. In some examples, such as... Figure 1 As shown, multiple substrate regions 200 on the display motherboard 10 can be arranged in a periodic and regular pattern, and the cutting region 210 can be located outside the substrate region 200. For example, the multiple substrate regions 200 can be arranged in an array along a first direction D1 and a second direction D2, and the cutting region 210 can surround each substrate region 200. The substrate region 200 can include a display region 201 and a border region surrounding the display region 201. The border region can include a first border region 203 located on one side of the display region 201 along the first direction D1, and a second border region 202 located on the remaining sides of the display region 201. The second border region 202 and the first border region 203 can surround the display region 201 after being connected.

[0047] In some examples, the display area 201 may be a flat area, which may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL forming a pixel array. The multiple sub-pixels PX can be configured to display dynamic or still images. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The orthographic projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. In some examples, the pixel control signals may include scan signals and emission control signals, or may include scan signals, or may include scan signals, reset control signals, and emission control signals. For example, a gate driving circuit can be set in the second frame area, and the gate driving circuit can be configured to provide pixel control signals to multiple gate lines.

[0048] In some examples, such as Figure 1 As shown, the second direction D2 can be the extension direction of the grid line GL in the display area 201 (e.g., the row direction), and the first direction D1 can be the extension direction of the data line DL in the display area 201 (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0049] In some examples, a pixel unit of display area 201 may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Alternatively, a pixel unit may include one red sub-pixel, one blue sub-pixel, and two green sub-pixels.

[0050] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, 8T2C, or 9T2C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the manufacturing process, reduce the manufacturing difficulty of the display panel, and improve product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0051] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display panel—an LTPS+Oxide (LTPO) display panel—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0052] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0053] In some examples, the orthographic projection of the light-emitting element of a sub-pixel onto the substrate can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0054] Figure 2 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present invention. Figure 2 The diagram illustrates the structure of a sub-pixel within the display area. In this example, multiple transistors in the pixel circuit are of the same type; for instance, all transistors in the pixel circuit may be low-temperature polysilicon thin-film transistors (LTPS) or oxide thin-film transistors (OTFTs). In other examples, the multiple transistors in the pixel circuit may be both LTPS and OTFTs.

[0055] In some examples, such as Figure 2 As shown, in a direction perpendicular to the substrate 100, the display area may include: the substrate 100, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 100. The circuit structure layer 12 may include pixel circuits for multiple sub-pixels located in the display area, each pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 13 may be located in the display area and may include light-emitting elements for multiple sub-pixels. In some possible implementations, the display area may include other film layers, such as spacers, touch structure layers, etc., which are not limited in this embodiment.

[0056] In some examples, substrate 100 can be a rigid substrate, such as a glass substrate. However, this embodiment is not limited to this. For example, the substrate can be a flexible substrate, such as one made of an insulating material like resin. Additionally, the substrate can be a single-layer or multi-layer structure. When the substrate is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be disposed in single or multiple layers between the layers.

[0057] In some examples, Figure 2 The diagram illustrates an example where each sub-pixel includes a transistor 16 and a capacitor 17. The circuit structure layer 12 may include: a semiconductor layer, a gate metal layer (e.g., including a first gate metal layer and a second gate metal layer), and a source / drain metal layer (e.g., including a first source / drain metal layer and a second source / drain metal layer) disposed on the substrate 100. A first insulating layer (also referred to as a first gate insulating layer) 101 may be disposed between the semiconductor layer and the first gate metal layer; a second insulating layer (also referred to as a second gate insulating layer) 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer (also referred to as an interlayer insulating layer) 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a fourth insulating layer (also referred to as a first planarization layer) 104 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and a fifth insulating layer (also referred to as a second planarization layer) 105 may be disposed on the side of the second source / drain metal layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can be inorganic insulating layers, while the fourth insulating layer 104 and the fifth insulating layer 105 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can also be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, a passivation layer can also be provided between the first source / drain metal layer and the second source / drain metal layer. The passivation layer can be located on the side of the first planarization layer near the substrate.

[0058] In some examples, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this invention is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0059] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0060] In some examples, such as Figure 2As shown, the semiconductor layer of the display area may include at least the active layer 160 of transistor 16. The active layer 160 of transistor 16 may include a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first gate metal layer may include at least the gate 163 of transistor 16 and the first electrode 171 of capacitor 17. The orthographic projection of the gate 163 of transistor 16 onto the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 onto the substrate 100. The second gate metal layer may include at least the second electrode 172 of capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of capacitor 17 onto the substrate 100 may at least partially overlap; for example, they may coincide. The first source-drain metal layer may include at least the source 161 and the drain 162 of transistor 16. The third insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 1601 of the active layer 160. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can also be removed, exposing at least a portion of the surface of the second region 1602 of the active layer 160. The source 161 of the transistor 16 can be electrically connected to the first region 1601 of the active layer 160 through the first pixel via, and the drain 162 can be electrically connected to the second region 1602 of the active layer 160 through the second pixel via. The second source-drain metal layer may include an anode transition electrode 181. The anode transition electrode 181 can be electrically connected to the drain 162 of the transistor 16 of the pixel circuit through the third pixel via formed in the fourth insulating layer 104. The anode adapter electrode 181 can also be connected to the light-emitting element through the fourth pixel via formed in the fifth insulating layer 105. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the anode adapter electrode 181.

[0061] In some examples, the gate lines of the display area may be located in the first gate metal layer, the data lines of the display area may be located in the second source-drain metal layer, and the high-potential power lines of the display area may be located in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0062] In some examples, such as Figure 2As shown, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a fifth insulating layer 105 and electrically connected to an anode transfer electrode 181 through a fourth pixel via formed in the fifth insulating layer 105. The pixel definition layer 134 is disposed on the first electrode 131 and the fifth insulating layer 105, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be a cathode, and can be disposed on and in contact with the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133. An isolation pillar layer can also be set on the side of the pixel definition layer 134 away from the substrate 100. The isolation pillar layer can include multiple isolation pillars (PS).

[0063] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and one or more films including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0064] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0065] In some examples, such as Figure 2 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, while the second encapsulation layer 142 may be made of organic materials. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0066] In some examples, such as Figure 1 As shown, the display area 201 of the substrate area 200 can be circular or elliptical, and the border area can be an annular area surrounding the display area 201. A first border area 203 can be located on one side of the display area 201 along a first direction D1. The first border area 203 can include a signal access area 2031. The signal access area 2031 can include at least one group of signal contact pads, each group of signal contact pads can include multiple signal contact pads, and the multiple signal contact pads can be arranged sequentially along a second direction D2, for example, arranged in a row along the second direction D2. The multiple signal contact pads within the signal access area 2031 can be configured to bond and connect with a flexible circuit board or a driver chip to acquire signals from the flexible circuit board or the driver chip.

[0067] In some examples, such as Figure 1As shown, each signal access area 2031 can be provided with a signal contact pad group. Multiple signal contact pads within each signal contact pad group can be connected to a set of first-type traces. The set of first-type traces can include multiple first-type traces 41 extending from the substrate area 200 to the cut area 210. For example, the multiple first-type traces 41 can extend at least along a first direction D1. Each first-type trace 41 can be connected to at least one signal contact pad.

[0068] In some examples, such as Figure 1 As shown, the cutting area 210 is provided with at least one test contact pad 31. The test contact pad group 31 may include multiple test contact pads 311, which may be arranged sequentially along the first direction D1, for example, in a row. Figure 1 In this example, a test contact pad group 31 can be connected to two signal contact pad groups within the signal access areas 2031 of two substrate regions 200 via two sets of Type I traces. For example, test contact pad 311 can be connected to a Type I trace 41 extending from the nearest substrate region 200 via a Type IV trace 44. The Type I trace 41 can be connected to at least one signal contact pad, and Type I traces 41 extending from adjacent substrate regions and transmitting the same signal can be connected via a Type V trace 45. The test contact pad group 31 can be located on the same side of the two connected substrate regions 200 along the second direction D2. The test contact pad 311 in this example can be configured to perform electrical testing (ET). Electrical testing focuses on the electrical characteristics of the display panel, such as voltage, current, and power consumption, and can evaluate the electrical performance of the display panel under different operating conditions, thereby ensuring the stability and reliability of the display panel in practical applications. Multiple test contact pads 311 can be configured to provide test signals during the electrical testing phase. For example, test signals may include: start signals, clock signals and voltage signals provided to the gate drive circuit, control signals provided to the test circuit, power signals and initial signals provided to the pixel circuit, etc.

[0069] In some examples, such as Figure 1 As shown, two adjacent substrate regions 200 along the second direction D2 can be considered as a group of substrate regions and connected to the same test contact pad group 31. The test contact pad group 31 can be located on the same side of the group of substrate regions along the second direction D2. In this example, a group of substrate regions can use the same FMM, which helps to reduce the number of FMM strands, thereby saving costs and improving substrate utilization. Moreover, a group of substrate regions sharing a single test contact pad group, and the test contact pad group being arranged on the same side of the group of substrate regions, can help save space and allow for simultaneous electrical testing of the group of substrate regions.

[0070] In some examples, the cut area 210 may also be provided with multiple test circuits 32. A test circuit 32 may be configured to provide test data signals to multiple data lines DL within the display area 201 of at least one substrate area 200 under the control of a control signal. For example, a test circuit 32 may be configured to provide test data signals to a substrate area 200. The test circuit 32 corresponding to each substrate area 200 may be located on one side of that substrate area 200 along a first direction D1; or, test circuits 32 corresponding to a group of substrate areas may be arranged together, for example, located on one side of one of the substrate areas in the group along the first direction D1. For example, two test circuits 32 corresponding to a group of substrate areas may be located on both sides of a group of first-type traces corresponding to one of the substrate areas along a second direction D2.

[0071] Figure 3 This is another partial plan view of the display motherboard according to at least one embodiment of the present invention. Figure 3 The diagram illustrates three complete substrate regions 200 comprising the display motherboard 10. In this example, the display area 201 included in the substrate region 200 can be rectangular, such as a rounded rectangle. In some examples, such as... Figure 3 As shown, three substrate regions 200 arranged sequentially along the second direction D2 constitute a group of substrate regions, which are connected to a test contact pad group 31. The test contact pad group 31 can be located on one side of the group of substrate regions along the second direction D2. Multiple test contact pads 311 within the test contact pad group 31 can be aligned and arranged along the first direction D1.

[0072] In some examples, such as Figure 3 As shown, in the cutting area 210, multiple test circuits 32 corresponding to a group of substrate areas can be arranged together, for example, arranged on one side of one of the substrate areas in the group of substrate areas along the first direction D1. For example, multiple test circuits 32 corresponding to a group of substrate areas can be arranged on one side of the first substrate area in the group of substrate areas along the first direction D1, and the first substrate area is located on the side of the remaining substrate areas away from the test contact pad 31 along the second direction D2.

[0073] In the display motherboard provided in this example, by placing the test contact pads and test circuits in the cutting area, the subsequent fabricated display panel no longer includes the test contact pads and test circuits, which is beneficial for the narrow bezel design of the display panel. Moreover, the arrangement of the test contact pads and test circuits in the cutting area in this example can help save costs and improve substrate utilization.

[0074] Figure 4 for Figure 1 A magnified view of a portion of region S1. In some examples, such as... Figure 1 and Figure 4 As shown, the cutting region 210 may include a cutting channel region 2101 and a cutting channel outer region 2102. The cutting channel region 2101 may surround the substrate region 200, and the cutting channel outer region 2102 is located on the side of the cutting channel region 2101 away from the substrate region 200. Multiple first-type traces 41 can extend from the substrate region 200 through the cutting channel region 2101 to the cutting channel outer region 2102. To facilitate the cutting of the display motherboard, the cutting channel region 2101 is thinned using a deep-hole design to achieve the desired cutting effect. However, the deep-hole design of the cutting channel region 2101 has a large film layer step difference, which can easily cause the extended metal traces to break or short-circuit, and can also easily cause material residue problems. For example, during the fabrication of the first electrode of the light-emitting element, when performing the conductive material exposure process, the photoresist in the cutting channel region is thicker and the superimposed conductive material is obliquely reflected at the slope of the deep hole, resulting in insufficient exposure energy, which can easily lead to conductive material residue at that location and cause defects.

[0075] In some examples, such as Figure 4 As shown, the display motherboard may include a composite insulating layer located in the cutting area 210, wherein the composite insulating layer has a plurality of cutting grooves 2050 in the cutting groove area 2101. The plurality of cutting grooves 2050 may extend along a first direction D1 and be spaced apart from a plurality of first-type traces 41 along a second direction D2. In other words, the orthographic projection of the first-type traces 41 on the substrate and the orthographic projection of the cutting grooves 2050 on the substrate do not overlap.

[0076] Figure 5 for Figure 4 A partial cross-sectional view of the central region along the QQ' direction. Figure 6 for Figure 4 A partial cross-sectional view of the central region along the PP' direction. Figure 7 This is a plan view of the cutting groove according to at least one embodiment of the present invention. Figure 8 for Figure 7 A partial cross-sectional view along the RR' direction.

[0077] In some examples, such as Figure 4 and Figure 5As shown, the signal contact pad 51 provided in the signal access area 2031 may include multiple pad layers stacked sequentially along a direction away from the substrate 100, such as a first pad layer 511 and a second pad layer 512. The first pad layer 511 and the second pad layer 512 can be in direct contact, and the first pad layer 511 may be located on the side of the second pad layer 512 away from the substrate 100. For example, the second pad layer 512 may be disposed on the same layer as the first gate metal layer of the display area, and the first pad layer 511 may be disposed on the same layer as the first source / drain metal layer of the display area. The first type of trace 41 may be disposed on the same layer as the first source / drain metal layer of the display area. The first type of trace 41 may be connected to the first pad layer 511 of the signal contact pad 51, for example, it may be an integral structure.

[0078] In some examples, such as Figure 5 and Figure 6 As shown, the composite insulating layer of the cut area may include an inorganic insulating layer group 601 and an organic insulating layer group 602. The inorganic insulating layer group 601 may include at least one inorganic insulating layer, and the organic insulating layer group 602 may include at least one organic insulating layer. For example, the inorganic insulating layer group 601 may include one or more of a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103, and the organic insulating layer group 602 may include one or more of a fourth insulating layer 104, a fifth insulating layer 105, and a pixel definition layer 134. The inorganic insulating layer group 601 may be located on the side of the first type of trace 41 closest to the substrate 100, and the organic insulating layer group 602 may be located on the side of the first type of trace 41 furthest from the substrate 100.

[0079] In some examples, such as Figure 4 and Figure 6 As shown, the composite insulating layer within the cutting groove 2050 can be removed, exposing the surface of the substrate 100. Within the cutting groove region 2101, the orthographic projection of the organic insulating layer group 602 onto the substrate 100 can cover the orthographic projection of the first type of trace 41 onto the substrate 100, and the orthographic projection of the inorganic insulating layer group 601 onto the substrate 100 can also cover the orthographic projection of the first type of trace 41 onto the substrate 100. In other words, the orthographic projection of the first type of trace 41 onto the substrate 100 can be located within the orthographic projection range of the composite insulating layer onto the substrate 100. The orthographic projection of the cutting groove 2050 onto the substrate 100 does not overlap with the orthographic projection of the first type of trace 41 onto the substrate 100. For example, the cutting groove 2050 and the first type of trace 41 can be spaced apart along the second direction D2.

[0080] In this example, by providing an inorganic insulating layer group 601 on the side of the first type of trace 41 near the substrate 100, the film layer step difference between the signal access area 2301 and the dicing area 2101 can be reduced, thereby reducing the risk of open circuit in the first type of trace 41. Moreover, by providing an organic insulating layer group 602 on the side of the first type of trace 41 away from the substrate 100, and by using a dicing groove 2050 to separate the first type of trace 41 in the dicing area 2101, not only can short circuits between adjacent traces be avoided, but the dicing effect can also be guaranteed.

[0081] In some examples, such as Figure 7 and Figure 8 As shown, the inorganic insulating layer group 601 of the composite insulating layer includes a third insulating layer 103, and the organic insulating layer group 602 includes a planarization layer (such as a stacked fourth insulating layer 104 and a fifth insulating layer 105) and a pixel definition layer 134 as an example. The third insulating layer 103 has a first sub-groove 2051 in the kerf region, the planarization layer has a second sub-groove 2052 in the kerf region, and the pixel definition layer 134 has a third sub-groove 2053 in the kerf region. The orthographic projection of the third sub-groove 2053 onto the substrate can cover the orthographic projection of the second sub-groove 2052 onto the substrate, and the orthographic projection of the second sub-groove 2052 onto the substrate can cover the orthographic projection of the first sub-groove 2051 onto the substrate; the first sub-groove 2051, the second sub-groove 2052, and the third sub-groove 2053 can be connected to form a kerf 2050. The kerf 2050 has a first edge 611 near the signal access region and a second edge 612 away from the signal access region. The first edge 611 has a first step formed by the sequential stacking of a third insulating layer 103, a planarization layer, and a pixel definition layer 134, and the second edge 612 has a second step formed by the sequential stacking of the third insulating layer 103, a planarization layer, and a pixel definition layer 134. The first step and the second step are different. Specifically, the maximum distance between the boundary of the inorganic insulating layer (e.g., the third insulating layer 103) at the first edge 611 and the boundary of the adjacent stacked organic insulating layer (e.g., the planarization layer) may be less than the maximum distance between the boundary of the inorganic insulating layer (e.g., the third insulating layer 103) at the second edge 612 and the boundary of the adjacent stacked organic insulating layer (e.g., the planarization layer). In other examples, the inorganic insulating layer group 601 may include a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially.

[0082] In some examples, such as Figure 7 and Figure 8As shown, at the first edge 611, the maximum distance between the boundary of the third insulating layer 103 and the boundary of the planarization layer is L4, and the maximum distance between the boundary of the planarization layer and the boundary of the pixel definition layer 134 is L3; at the second edge 612, the maximum distance between the boundary of the third insulating layer 103 and the boundary of the planarization layer is L2, and the maximum distance between the boundary of the planarization layer and the boundary of the pixel definition layer 134 is L1. Wherein, L2 is greater than L4, L2 is greater than L1, and L2 is greater than L3. For example, L1, L3, and L4 are all approximately 5 micrometers, and L2 can be approximately 10 micrometers.

[0083] In this example, by improving the step shape of the composite insulating layer at the second edge of the cutting groove, the second step at the second edge is made flatter. This can improve the situation where, during the fabrication of the first electrode of the light-emitting element, the photoresist at this location is thick and the superimposed conductive material obliquely reflects at the slope of the deep hole, resulting in insufficient exposure energy and causing residual conductive material at this location to produce defects. This can improve the signal short circuit and the abnormal test conditions caused by this.

[0084] In some examples, such as Figure 1 and Figure 4 As shown, the cutting area is also provided with a fourth type of trace 44 and a fifth type of trace 45. The first type of trace 41 extends from the substrate region to the cutting area along the first direction D1 and can be connected to either the fourth type of trace 44 or the fifth type of trace 45. The fourth type of trace 44 can extend towards and connect to the test contact pad. The first type of trace 41 and the connected fourth type of trace 44 can be in the same layer, for example, as a single unit. First type of traces 41 extending from different substrate regions and transmitting the same signal can be connected through the fifth type of trace 45. First type of traces 41 connected to contact pads transmitting the same signal in different substrate regions can be connected through the fifth type of trace 45 and connected to the same test contact pad through the fourth type of trace 44. The film layer containing the fifth type of trace 45 can be located on the side of the film layer containing the first type of trace 41 closer to the substrate. For example, the fifth type of trace 45 can be disposed in the same layer as the gate metal layer of the display area, or the fifth type of trace 45 can be disposed in the same layer as the first gate metal layer of the display area.

[0085] This example, by placing the test circuit and test contact pad outside the substrate area, can facilitate the narrow bezel design of the display panel. Furthermore, by improving the insulating layer and trace film in the cut area, it can avoid short circuits or open circuits in the traces and help ensure the test results.

[0086] Figure 9 for Figure 1 A magnified view of a portion of region S2. In some examples, such as... Figure 9As shown, a test circuit 32 can be installed in the area 2102 outside the cutting channel. Multiple signal contact pads 51 within the signal access area 2031 can include: a first type of signal contact pad 51a and a second type of signal contact pad 51b. The first type of signal contact pad 51a can be connected to a first type of trace 41, and the second type of signal contact pad 51b can be connected to a second type of trace 42. The second type of signal contact pad 51b can be connected to a data fan-out line within the first border area, and the data fan-out line can be connected to the data line of the display area. The test data signal can be transmitted sequentially to the data line of the display area via the test circuit 32, the second type of trace 42, the second type of signal contact pad 51b, and the data fan-out line.

[0087] In some examples, such as Figure 9 As shown, the test circuit 32 may include multiple test units, and each test unit may include multiple test transistors, such as a first test transistor T1, a second test transistor T2, and a third test transistor T3. The multiple test units may be arranged sequentially along the second direction D2. The first test transistor T1, the second test transistor T2, and the third test transistor T3 of a single test unit may be aligned along the first direction D1.

[0088] In some examples, such as Figure 9As shown, the gate of the first test transistor T1 can be connected to the first control line 321a, and the first terminal of the first test transistor T1 can be connected to the first test data line 322; the gate of the second test transistor T2 can be connected to the second control line 321b, and the first terminal of the second test transistor T2 can be connected to the second test data line 323; the gate of the third test transistor T3 can be connected to the third control line 321c, and the first terminal of the third test transistor T3 can be connected to the third test data line 324; the second terminals of the first test transistor T1, the second test transistor T2, and the third test transistor T3 can be connected to the same second-type trace 42. The first control line 321a, the second control line 321b, the third control line 321c, the first test data line 322, the second test data line 323, and the third test data line 324 can be in the same layer and all extend along the second direction D2. The first control line 321a, the second control line 321b, the third control line 321c, the first test data line 322, the second test data line 323, and the third test data line 324 can be connected to the corresponding third-type trace 43, for example, connected to the corresponding test contact pad through the third-type trace 43. The film layer containing the third-type trace 43 can be located on the side of the film layer containing the first-type trace 41 closer to the substrate, for example, it can be set in the same layer as the second gate metal layer of the display area. Under the control of the first control line 321a, the second control line 321b, and the third control line 321c, the test circuit of this example can transmit the test data signals provided by the first test data line 322, the second test data line 323, and the third test data line 324 to the corresponding data lines.

[0089] In some examples, such as Figure 9 As shown, the second type of trace 42 can extend along the first direction D1 and, after passing through the cut channel region 2101, connect to the second type of signal contact pad 51b within the signal access region 2031. For example, the second type of trace 42 can be integrally formed with one of the pad layers (such as the first pad layer) of the second type of signal contact pad 51b. The first type of trace 41 can be integrally formed with one of the pad layers (such as the first pad layer) of the first type of signal contact pad 51a. The first type of trace 41 and the second type of trace 42 can be in the same layer, for example, both can be disposed in the same layer as the first source / drain metal layer of the display area.

[0090] In some examples, such as Figure 9 As shown, in the cut area 2101, the composite insulation layer can cover the orthographic projection of the first type of trace 41 and the second type of trace 42 onto the substrate. The cut groove 2050 of the composite insulation layer can be provided in the spacing area of ​​the first type of trace 41 and the spacing area of ​​the first type of trace 41 and the second type of trace 42.

[0091] In this example, placing the test circuit in the cut area facilitates the narrow bezel design of the display panel; the arrangement of the second type of trace in the cut area is similar to that of the first type of trace, which helps ensure the transmission effect of test data signals. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0092] Figure 10 for Figure 1 Another enlarged view of a portion of the central region S2. In some examples, such as... Figure 10 As shown, the second type of trace 42 and the first type of trace 41 can be located in different film layers, and the film layer where the second type of trace 42 is located can be located on the side of the film layer where the first type of trace 41 is located closer to the substrate. For example, the second type of trace 42 can be disposed in the same layer as the gate metal layer of the display area (such as the first gate metal layer or the second gate metal layer), and the first type of trace 41 can be disposed in the same layer as the first source / drain metal layer of the display area. A first insulating layer can be disposed on the side of the second type of trace 42 closer to the substrate, and a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a pixel definition layer can be disposed on the side of the second type of trace 42 away from the substrate.

[0093] This example protects the second type of trace 42 by covering it with an inorganic insulating layer (e.g., including a second insulating layer and a third insulating layer, or including a third insulating layer) and an organic insulating layer (e.g., including a fourth insulating layer, a fifth insulating layer, and a pixel definition layer). This composite insulating layer prevents defects such as trace breaks caused by etching of the second type of trace during the fabrication of the first electrode of the light-emitting element. Further details regarding this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0094] Figure 11 This is a schematic diagram illustrating a black line display defect that occurs during the manufacturing process of a display panel. (Example) Figure 11As shown, the source / drain metal layer may include a first sublayer 811, a second sublayer 812, and a third sublayer 813 stacked sequentially. The first sublayer 811 and the third sublayer 813 are made of the same material, and the material stability of the first sublayer 811 and the third sublayer 813 is greater than that of the second sublayer 812. For example, the first sublayer 811 and the third sublayer 813 may be made of titanium (Ti), and the second sublayer 812 may be made of aluminum (Al). After the source / drain metal layer is fabricated, the planarization layer 82 will partially cover the source / drain metal layer when there is no inorganic layer covering it. During the fabrication of the first electrode 131 of the light-emitting element, the second sublayer 812 of the source / drain metal layer not covered by the planarization layer 82 will be etched laterally, while the first sublayer 811 and the third sublayer 813 not covered by the planarization layer 82 will remain, forming a protruding structure. During the fabrication of the first electrode 131 of the light-emitting element, the protruding third sublayer 813 may be washed away by water pressure and may fall between adjacent first electrodes 131 of the light-emitting element, causing a short circuit. During the fabrication of the pixel definition layer 134, the third sub-layer 813, which causes an open circuit by connecting to the first electrode 131, is directly covered, making it impossible for subsequent processes to resolve the resulting black line display issue. The inventors discovered that the exposed source / drain metal layers during fabrication are primarily located in the first border area.

[0095] Figure 12 This is a partial schematic diagram of the first border region according to at least one embodiment of the present invention. In some examples, such as... Figure 12 As shown, the first border area may include a signal access area 2031 and an encapsulation area 2032 located on the side of the signal access area 2031 closer to the display area 201. The encapsulation area 2032 may be an area coated or printed with encapsulating adhesive. In some examples, the encapsulation area 2032 may be an annular area surrounding the display area 201, thereby improving the encapsulation effect.

[0096] In some examples, the first bezel area is also provided with power lines, such as a first power line 711 and second power lines 712a and 712b. The first power line 711 can be connected to a high-potential power line within the display area 201 and configured to transmit a first power signal; the second power lines 712a and 712b can extend to the second bezel area and be connected in a single structure within the second bezel area, configured to transmit a second power signal, such as being connected to the second electrode of the light-emitting element.

[0097] In some examples, the second power lines 712a and 712b may be located on opposite sides of the first power line 711 in the second direction D2. The first power line 711 may extend to the signal access area 2031 and connect to the signal contact pad 51c that transmits the first power signal within the signal access area 2031. The second power lines 712a and 712b may both extend to the signal access area 2031 and connect to the signal contact pad 51d that transmits the second power signal within the signal access area 2031. In some examples, the first power line 711 and the second power lines 712a and 712b may be in the same layer, for example, located in the first source / drain metal layer or the second source / drain metal layer.

[0098] In some examples, the first border area may also be provided with multiple data fan-out lines, which can be connected to multiple signal contact pads (such as signal contact pad 51b) within the signal access area 2031 for transmitting data signals and test data signals. The multiple data fan-out lines may be located on the side of the first power line 711 and the second power lines 712a and 712b near the substrate, for example, they may be located in the gate metal layer.

[0099] In some examples, such as Figure 12 As shown, at least a portion of the first power line 711 and the second power lines 712a and 712b can be located in the encapsulation region 2032. The first power line 711 located in the encapsulation region 2032 can serve as a first encapsulant substrate, and the second power lines 712a and 712b located in the encapsulation region 2032 can serve as a second encapsulant substrate. The first power line 711 and the second power lines 712a and 712b can have multiple openings. By providing multiple openings in the power lines serving as encapsulant substrates, when encapsulant is applied to the encapsulant substrate, the encapsulant will leak into the openings, which is equivalent to having encapsulant both on top of and inside the encapsulant substrate. When the encapsulant is melted by laser, the adhesive strength of the encapsulant can be further improved, the bonding force between the substrate and the encapsulation cover can be enhanced, thereby improving the product yield.

[0100] Figure 13 This is an example diagram of the first border area of ​​at least one embodiment of the present invention. Figure 14 for Figure 13 A partial cross-sectional view along the VV' direction. In some examples, such as... Figure 13 and Figure 14As shown, taking the signal contact pad 51d transmitting the second power signal within the signal access area 2031 as an example, the signal contact pad 51d may include: a first pad layer and a second pad layer 512. The first pad layer 511 may include a first sub-pad layer 511-1, a second sub-pad layer 511-2, and a third sub-pad layer 511-3. The first pad layer may be located on the side of the second pad layer 512 away from the substrate 100. The second pad layer 512 may, for example, be located in the first gate metal layer. The first pad layer may be located in the first source / drain metal layer. The materials of the first sub-pad layer 511-1 and the third sub-pad layer 511-3 may be Ti, and the material of the second sub-pad layer 511-2 may be Al. The first pad layer and the second pad layer 512 may be connected through vias formed in the third insulating layer 103 and the second insulating layer 102.

[0101] In some examples, such as Figure 14 As shown, an auxiliary conductive layer 75 is also provided in the first border area. The orthographic projection of the auxiliary conductive layer 75 onto the substrate can cover the orthographic projection of the pad furthest from the substrate (e.g., the first pad) of the signal contact pad 51 onto the substrate 100. The orthographic projection of the auxiliary conductive layer 75 onto the substrate and the orthographic projection of the second pad onto the substrate can at least partially overlap. The auxiliary conductive layer 75 can be in direct contact with the first pad of the signal contact pad 51. The orthographic projection of the auxiliary conductive layer 75 onto the substrate can cover the orthographic projection of the first pads of multiple signal contact pads 51 onto the substrate and cover the edge of the first pad. The minimum distance W1 between the edge of the auxiliary conductive layer 75 protruding from the first pad and the edge of the first pad can be greater than or equal to 1 micrometer, for example, it can be about 1.5 micrometers.

[0102] In some examples, such as Figure 13 As shown, the auxiliary conductive layer 75 can directly contact the first power line 711, the second power lines 712a and 712b. The orthographic projection of the auxiliary conductive layer 75 onto the substrate can cover the orthographic projections of the first power line 711, the second power lines 712a and 712b onto the substrate, and also cover the edges of the first power line 711, the second power lines 712a and 712b.

[0103] In some examples, the auxiliary conductive layer 75 can be co-layered with the first electrode of the light-emitting element. This example utilizes the co-layered auxiliary conductive layer 75 to provide full coverage protection for the exposed contact pads and traces located in the source / drain metal layers, which can improve… Figure 11 The problem shown indicates that the black line is not displaying correctly.

[0104] Figure 15 This is another example diagram of the first border region of at least one embodiment of the present invention. Figure 16 for Figure 15 A partial cross-sectional view along the UU' direction. In some examples, such as... Figure 15 and Figure 16As shown, the auxiliary conductive layer 75 can directly contact the first pad layer of the signal contact pad 51. The auxiliary conductive layer 75 can cover the edge of the first pad layer, and the orthographic projection of the auxiliary conductive layer 75 onto the substrate can overlap with the orthographic projection portion of the first pad layer of the multiple signal contact pads 51 onto the substrate. The minimum distance between the edge of the auxiliary conductive layer 75 protruding from the first pad layer and the edge of the first pad layer is W2, and the minimum distance between the edges of the first pad layer covered by the auxiliary conductive layer 75 and the first pad layer is W3. W2 can be approximately equal to W3; for example, W2 and W3 can be greater than or equal to 1 micrometer, such as approximately 1.5 micrometers.

[0105] In some examples, such as Figure 15 As shown, the auxiliary conductive layer 75 can directly contact the first power line 711, the second power lines 712a and 712b. The orthographic projection of the auxiliary conductive layer 75 onto the substrate overlaps with the orthographic projections of the first power line 711, the second power lines 712a and 712b onto the substrate, and covers the edges of the first power line 711, the second power lines 712a and 712b.

[0106] In some examples, the auxiliary conductive layer 75 can be co-layered with the first electrode of the light-emitting element. This example utilizes the auxiliary conductive layer 75, which is co-layered with the first electrode of the light-emitting element, to provide edge protection for the exposed contact pads and traces located in the source / drain metal layers, thereby improving… Figure 11 The problem shown results in poor black line display. Furthermore, compared to full coverage protection, this method improves the issues of difficult bonding and insufficient pull-out force caused by excessive resistance of the auxiliary conductive layer. Further details regarding this example can be found in the description of the foregoing embodiments and will not be repeated here.

[0107] In other examples, the auxiliary conductive layer 75 can provide full coverage protection for the signal contact pads in the signal access area and edge coverage protection for the power lines in the package area; or, the auxiliary conductive layer 75 can provide edge coverage protection for the signal contact pads in the signal access area and full coverage protection for the power lines in the package area. This embodiment is not limited in this respect.

[0108] This embodiment also provides a display panel, including: a substrate, a plurality of signal contact pads disposed on the substrate, and an auxiliary conductive layer. The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including: at least one signal access area; the plurality of signal contact pads are located in the signal access area. The auxiliary conductive layer is located on the side of the plurality of signal contact pads away from the substrate; the auxiliary conductive layer covers the edge of the pad layer of the plurality of signal contact pads furthest from the substrate, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the pad layer of the plurality of signal contact pads furthest from the substrate on the substrate.

[0109] The display panel of this embodiment can be obtained by cutting the aforementioned display motherboard. The display panel of this embodiment utilizes an auxiliary conductive layer to protect the edges of the signal contact pads, which can improve... Figure 11 The problem shown indicates that the black line is not displaying correctly.

[0110] In some exemplary embodiments, the first bezel region may further include an encapsulation region located between the display region and the signal access region. The display panel may further include: a power line located in the encapsulation region; the power line being connected to at least one signal contact pad; and an auxiliary conductive layer covering the edge of the power line, wherein the orthographic projection of the auxiliary conductive layer onto the substrate at least partially overlaps the orthographic projection of the power line onto the substrate. The display panel of this embodiment utilizes an auxiliary conductive layer to provide edge protection for the power line in the encapsulation region, which can improve… Figure 11 The problem shown indicates that the black line is not displaying correctly.

[0111] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0112] Figure 17 This is a schematic diagram of a display device according to at least one embodiment of the present invention. In some examples, such as... Figure 17 As shown, the display device 91 may include a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0113] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0114] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display motherboard, characterized in that, include: The substrate includes multiple substrate regions and a cut-out region surrounding the substrate regions. The substrate regions include a display region and a first border region located on one side of the display region along a first direction. The first border region includes at least one signal access region. Multiple signal contact pad groups are disposed on the substrate, each signal contact pad group includes multiple signal contact pads, and at least one signal contact pad group is disposed in each signal access area; Multiple sets of first-class traces are disposed on the substrate. Each set of first-class traces includes multiple first-class traces extending from the substrate region to the cut region. Each first-class trace is connected to at least one signal contact pad. At least one set of test contact pads is located in the cut area; each set of test contact pads includes a plurality of test contact pads, and each set of test contact pads is configured to provide test signals to signal contact pads in at least two substrate areas through at least two sets of first-class traces, and each set of test contact pads is located on the same side of the at least two connected substrate areas in one direction.

2. The display motherboard according to claim 1, characterized in that, The test contact pad group is located on the same side of the at least two connected substrate regions along the second direction, and a plurality of test contact pads in the test contact pad group are arranged along the first direction; the first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction intersect.

3. The display motherboard according to claim 1, characterized in that, The display motherboard further includes: a composite insulating layer located in the cutting area; the cutting area includes: a cutting channel area surrounding the substrate area, the composite insulating layer having multiple cutting grooves in the cutting channel area; in the cutting channel area, the orthographic projection of the multiple first-type traces on the substrate is located within the orthographic projection range of the composite insulating layer on the substrate.

4. The display motherboard according to claim 3, characterized in that, In the cutting channel area, the plurality of first-type traces are spaced apart from the plurality of cutting slots.

5. The display motherboard according to any one of claims 1 to 4, characterized in that, The display motherboard also includes: at least one test circuit, multiple second-class traces, and multiple third-class traces located in the cutting area; The at least one test circuit is located on one side of the substrate region along the first direction; the at least one test circuit is configured to be connected to a plurality of signal contact pads in the substrate region via the plurality of second-type traces, and is also configured to be connected to the test contact pad group via the plurality of third-type traces.

6. The display motherboard according to claim 5, characterized in that, The plurality of second-type traces and the plurality of first-type traces are in the same layer, or the film layer containing the plurality of second-type traces is located on the side of the film layer containing the plurality of first-type traces closer to the substrate.

7. The display motherboard according to claim 6, characterized in that, The multiple Type II traces are located in the gate metal layer or the source / drain metal layer.

8. The display motherboard according to claim 5, characterized in that, The display motherboard further includes: a composite insulating layer located in the cutting area; the cutting area includes: a cutting channel area surrounding the substrate area; in the cutting channel area, the orthographic projection of the plurality of second-type traces on the substrate is located within the orthographic projection range of the composite insulating layer on the substrate.

9. The display motherboard according to claim 3, characterized in that, The composite insulating layer includes at least one inorganic insulating layer and at least one organic insulating layer; the cutting groove has a first edge close to the signal access area and a second edge away from the signal access area; the maximum distance between the boundaries of adjacent stacked inorganic and organic insulating layers at the first edge is less than the maximum distance between the boundaries at the second edge.

10. The display motherboard according to claim 1, characterized in that, The display motherboard further includes: an auxiliary conductive layer located on the side of the plurality of signal contact pads away from the substrate; the signal contact pads include a plurality of pad layers stacked sequentially in a direction away from the substrate; The auxiliary conductive layer covers the edge of the pad layer furthest from the substrate of the plurality of signal contact pads, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the pad layer furthest from the substrate of the plurality of signal contact pads on the substrate.

11. The display motherboard according to claim 10, characterized in that, The first border area further includes: an encapsulation area located between the display area and the signal access area; The display motherboard further includes: a power line located in the encapsulation area; the power line being connected to at least one signal contact pad; an auxiliary conductive layer covering the edge of the power line, wherein the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps the orthographic projection of the power line on the substrate.

12. The display motherboard according to claim 10 or 11, characterized in that, The display motherboard further includes: a plurality of light-emitting elements located in the display area of ​​the substrate area, the light-emitting elements including: a first electrode, an organic light-emitting layer and a second electrode arranged in sequence; the auxiliary conductive layer and the first electrode of the light-emitting element are of the same layer structure.

13. A display panel, characterized in that, include: The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including: at least one signal access area; Multiple signal contact pads are disposed on the substrate and located in the signal access area; An auxiliary conductive layer is located on the side of the plurality of signal contact pads away from the substrate; The auxiliary conductive layer covers the edge of the pad layer furthest from the substrate of the plurality of signal contact pads, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the pad layer furthest from the substrate of the plurality of signal contact pads on the substrate.

14. The display panel according to claim 13, characterized in that, The first border area further includes: an encapsulation area located between the display area and the signal access area; The display panel further includes: a power line located in the encapsulation area; the power line being connected to at least one signal contact pad; an auxiliary conductive layer covering the edge of the power line, wherein the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps the orthographic projection of the power line on the substrate.

15. The display panel according to claim 13 or 14, characterized in that, The display panel further includes a plurality of light-emitting elements located in the display area, each light-emitting element comprising a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially; the auxiliary conductive layer is of the same layer structure as the first electrode of the light-emitting element.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 13 to 15.

Images