Sealing apparatus and gas purging device for sealing apparatus

Abstract

A sealing device includes: a wafer stage configured to hold a wafer stack on the wafer stage; and a nozzle disposed on one side of the wafer stage and configured to direct a sealant flow to a side surface of the wafer stack. The sealing device further includes a gas purger disposed on that side of the wafer stage and configured to direct a purge airflow toward a back surface of the wafer stack.

Description

Technical Field

[0001] This disclosure relates to sealing equipment and gas purging devices used in sealing equipment. Background Technology

[0002] Wafer bevel sealing is an important process for protecting wafer edges and preventing particle contamination on wafer surfaces adjacent to the edges. A sealing nozzle can be used to spray a polymer sealant onto the wafer bevel via a jet nozzle. However, polymer sealant particles can also deposit on the main surface of the wafer adjacent to the wafer bevel during the process. In particular, polymer sealant particles can deposit on the back surface of the wafer. These sealant particles increase the defect rate of wafer products during the manufacturing process. Therefore, it is desirable to prevent sealant particle contamination near the wafer edges. Therefore, improved sealing equipment and methods for reducing contaminant particles on wafer surfaces adjacent to the edges are desired. Utility Model Content

[0003] According to some embodiments of this disclosure, a sealing device is provided, comprising: a wafer stage configured to hold a wafer stack on the wafer stage; a nozzle disposed on one side of the wafer stage and configured to direct a sealant flow to a side surface of the wafer stack; and a gas purger disposed on the side of the wafer stage and configured to direct a purge airflow toward a back surface of the wafer stack.

[0004] According to some embodiments of this disclosure, a gas purging device for a sealing apparatus is provided, the gas purging device comprising: a base portion configured to attach the gas purging device to a wafer stage of the sealing apparatus; and a head portion configured to engage with the base portion, wherein the head portion includes: a gas diffusion channel disposed at a top surface of the head portion and configured to guide a purge gas flow toward a back surface of a wafer stack; and a plurality of vacuum holes disposed at a non-vertical sidewall of the head portion and configured to remove sealant particles and purge gas from the sealing apparatus. Attached Figure Description

[0005] The following detailed description, taken in conjunction with the accompanying drawings, provides the best understanding of this disclosure. It should be emphasized that, in accordance with industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 A schematic diagram illustrating a sealing device according to some embodiments of the present disclosure is shown.

[0007] Figure 2AA front view of a gas purger according to some embodiments of the present disclosure is shown.

[0008] Figure 2B A side view of a gas purger according to some embodiments of the present disclosure is shown.

[0009] Figure 2C A top view of a gas purger according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A perspective view illustrating a head portion of a gas purger according to some embodiments of the present disclosure.

[0011] Figure 4 A side view of a base portion of a gas purger according to some embodiments of the present disclosure is shown.

[0012] Figure 5 A close-up view of a portion of a sealing device according to some embodiments of the present disclosure is shown.

[0013] Figure 6 An example flow field concentration distribution diagram is shown according to some embodiments of the present disclosure.

[0014] Figure 7 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure is shown.

[0015] Figure 8A and 8B A computer system for carrying out various methods is illustrated according to some embodiments of the present disclosure. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, a first feature formed on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for the purpose of simplicity and clarity and does not, in itself, specify a relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of explanation, this document uses spatial relative terms such as “under,” “below,” “below,” “above,” “on,” and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, unless otherwise stated, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C.

[0018] A wafer bevel seal using a polymer sealant protects the wafer edges and prevents edge chipping and particle contamination. However, polymer sealant particles can deposit on the back surface of the wafer during the sealing process. Embodiments of this disclosure provide an improved apparatus and method for manufacturing semiconductor devices, thereby reducing polymer sealant particle contamination on the back surface of the wafer. In some embodiments, the improved apparatus and method include using a gas purging module to prevent polymer sealant particle deposition on the back surface of the wafer, thereby reducing contamination on the back surface of the wafer. Therefore, the defect rate of the wafer product can be reduced, and the quality of the wafer product can be improved.

[0019] Figure 1 A schematic diagram of a sealing device 100 according to some embodiments of the present disclosure is shown. In some embodiments, the sealing device 100 includes a wafer stage 102, a sealant nozzle 106, and a gas purger 108.

[0020] In some embodiments, the wafer stage 102 includes a wafer platform 102a. The wafer platform 102a is configured to hold a wafer stack 104 on the wafer platform 102a. In some examples, the wafer platform 102a is configured to hold a wafer on the wafer platform 102a. In some examples, the wafer platform 102a is configured to hold a wafer stack 104 on the wafer platform 102a. The wafer platform 102a is configured to rotate on the wafer stage 102 such that the wafer stack 104 on the wafer platform 102a can rotate along an axis 102b of the wafer stage 102, and a sealant nozzle 106 can sweep across one side surface 104c of the wafer stack 104. Although Figure 1The image shows two wafers in wafer stack 104, but wafer stack 104 may include any suitable number of wafers. In some embodiments, the stack comprises only one wafer.

[0021] In some embodiments, the wafer stack 104 includes at least two wafers stacked vertically. In some embodiments, each of the at least two wafers has the same diameter so that the at least two wafers can be stacked together.

[0022] In some embodiments, a sealant nozzle 106 is disposed on one side of the wafer stage 102. In some embodiments, the sealant nozzle 106 is horizontally aligned with the wafer stack 104 such that the sealant nozzle 106 can guide a sealant flow 106a from the sealant nozzle 106 toward the side surface 104c of the wafer stack 104. For example, the sealant nozzle 106 is aligned with the wafer stack 104 in the y-direction. In some embodiments, the sealant nozzle 106 is mounted to a fixture (not shown) of the sealing device 100 such that the sealant nozzle 106 is supported by the fixture.

[0023] In some embodiments, the sealant nozzle 106 is at the same vertical level as the wafer stack 104 to minimize the amount of sealant particles deposited on the back surface 104b and the front surface 104a of the wafer stack 104.

[0024] In some embodiments, sealant flow 106a is generated by a pump (not shown). In some embodiments, the flow rate of sealant flow 106a may be adjusted by the pump. In some embodiments, sealant flow 106a comprises a sealant mist. In some embodiments, sealant flow 106a comprises sealant droplets. In some embodiments, sealant flow 106a comprises a dielectric material for wafer bonding. In some embodiments, sealant flow 106a comprises polymer sealant particles. In some embodiments, polymer sealant particles comprise polyimide, polybenzo[a]pyrene, etc. azoles and / or epoxy resins. In some embodiments, the polymer sealant particles comprise a polysiloxane-based polymer.

[0025] In some embodiments, the sealant nozzle 106 is a spray nozzle configured to increase the flow rate of the sealant flow 106a at the nozzle opening.

[0026] In some embodiments, after sealant particles from sealant stream 106a are deposited on the side surface 104c of wafer stack 104, a sealing layer 120 is formed on the side surface 104c of wafer stack 104. In some embodiments, the sealing layer 120 seals the beveled edges of wafer stack 104 to protect the beveled edges of wafer stack 104 from edge chipping.

[0027] In some embodiments, the wafer stage 102 is driven to move toward and / or away from the sealant nozzle 106. In some embodiments, the wafer stage 102 is driven to move vertically to align the wafer stack 104 with the sealant nozzle 106. Additionally or alternatively, in some embodiments, the sealant nozzle 106 is driven to move toward and / or away from the wafer stage 102. In some embodiments, the wafer stage is driven along a track (not shown) to move horizontally and vertically.

[0028] In some embodiments, a gas purger 108 is disposed on this side of the wafer stage 102. In some embodiments, the gas purger 108 is mounted on the wafer stage 102.

[0029] In some embodiments, the gas purger 108 includes a gas diffusion channel configured to spray a purge gas flow onto the back surface 104b of the wafer stack 104 to prevent sealant particles from depositing on the back surface 104b of the wafer stack 104.

[0030] In some embodiments, the purge gas is N2. In some embodiments, the purge gas is an inert gas, such as He or Ar.

[0031] In some embodiments, the gas purger 108 further includes a plurality of orifices configured to provide a vacuum to remove sealant particles not deposited on the side surface 104c of the wafer stack 104. In some embodiments, the plurality of orifices are also configured to remove purge gas from the sealing device 100.

[0032] In some embodiments, the sealing device 100 further includes an imager 110 configured adjacent to the sealant nozzle 106, the gas purger 108, and the wafer stage 102. In some embodiments, the imager 110 is a charge-coupled device (CCD) camera configured to capture an image of the sealant nozzle 106, the gas purger 108, and the wafer stack 104 on the wafer stage 102. In some embodiments, the imager 110 is configured to monitor a state of the sealant nozzle 106, a state of the gas purger 108, and a state of the wafer stack 104 on the wafer stage 102 based on the captured images. In some embodiments, the imager 110 is configured to monitor sealant particles accumulated on the sealant nozzle 106. In some embodiments, the imager 110 is configured to monitor sealant particles accumulated on the gas purger 108. In some embodiments, the imager 110 is configured to monitor a sealing layer 120 formed on the side surface 104c of the wafer stack 104.

[0033] In some embodiments, the sealing device 100 further includes a nozzle cleaner 112. The nozzle cleaner 112 is configured to clean the sealant nozzle 106 by removing sealant particles accumulated in and around the sealant nozzle 106.

[0034] In some embodiments, a nozzle cleaner 112 is disposed near the sealant nozzle 106. In some embodiments, the nozzle cleaner 112 is configured to automatically clean the sealant nozzle 106 when sealant particles accumulated in and near the sealant nozzle 106 are detected. In some embodiments, the nozzle cleaner 112 is configured to periodically clean the sealant nozzle 106.

[0035] In some embodiments, a nozzle cleaner 112 is disposed near a gas purger 108. In some embodiments, the nozzle cleaner 112 is configured to automatically clean the plurality of orifices of the gas purger 108 when sealant particles accumulated in and near the orifices of the gas purger 108 are detected. In some embodiments, the nozzle cleaner 112 is configured to periodically clean the plurality of orifices of the gas purger 108.

[0036] In some embodiments, the sealing device 100 further includes a microbalance sensor 114 connected to and / or coupled to the wafer stage 102. In some embodiments, the microbalance sensor 114 is configured to monitor and / or detect a state of the wafer stack 104 on the wafer stage 102. In some embodiments, the microbalance sensor 114 is configured to detect a mass change in the wafer stack 104. In some examples, the microbalance sensor 114 is configured to monitor the balance of the wafer stack to determine the uniformity of the sealant layer formed on the side surface 104c of the wafer stack 104.

[0037] In some embodiments, the microbalance sensor 114 is configured to continuously monitor and / or detect the state of the wafer stack 104 on the wafer stage 102. In some embodiments, the microbalance sensor 114 is configured to periodically monitor and / or detect the state of the wafer stack 104 on the wafer stage 102.

[0038] In some embodiments, such as Figure 1 As shown, the sealing device 100 further includes a housing 101, which includes a vacuum chamber 101a for sealing the wafer stack 104. In some embodiments, the housing 101 is connected to a vacuum pump that evacuates the vacuum chamber to provide a vacuum in the vacuum chamber.

[0039] In some embodiments, the wafer stage 102, sealant nozzle 106, gas purger 108, imager 110, nozzle cleaner 112, and microbalance sensor 114 are housed within the housing 101, and a sealing procedure is performed on the wafer stack 104 within the vacuum chamber 101a. In some embodiments, the sealing procedure within the vacuum chamber 101a reduces the accumulation of contaminant particles on the wafer stage 102, sealant nozzle 106, gas purger 108, imager 110, nozzle cleaner 112, and microbalance sensor 114. In some embodiments, the housing 101 is frequently and / or periodically maintained to prevent the accumulation of contaminant particles on the inner sidewalls of the housing 101.

[0040] In some embodiments, the sealing device 100 further includes a controller 150 electrically or wirelessly connected to and / or coupled to the wafer stage 102, sealant nozzle 106, gas purger 108, imager 110, and microbalance sensor 114. The controller 150 is configured to receive and process data generated from the wafer stage 102, sealant nozzle 106, gas purger 108, imager 110, and microbalance sensor 114. In some embodiments, the controller 150 is a microcontroller configured to receive and process the generated data and adjust the setting parameters of the wafer stage 102, sealant nozzle 106, gas purger 108, imager 110, and microbalance sensor 114 based on the generated data.

[0041] In some examples, controller 150 is electrically or wirelessly connected to and / or coupled to a pump for sealant nozzle 106. Controller 150 is configured to control and / or adjust the flow rate of sealant flow 106a.

[0042] In some examples, controller 150 includes software and hardware for image storage, image comparison, and image evaluation. In one example, controller 150 includes a medium, such as a flash memory device or hard disk, for storing images of the sealant nozzle 106, the gas purger 108, and the wafer stack 104 on the wafer stage 102. In another embodiment, controller 150 includes an algorithm that processes multiple images associated with the sealant nozzle 106, the gas purger 108, and the wafer stack 104 on the wafer stage 102 to determine the state of the sealant nozzle 106, the state of the gas purger 108, and the state of the wafer stack 104 on the wafer stage 102.

[0043] It should be understood that the controller 150 may be centralized at a single site or distributed. In one embodiment, the controller 150 is embedded in the sealing device 100. In one embodiment, as... Figure 1As shown, the controller 150 is located on the outside of the housing 101. In another embodiment, the controller 150 is remotely connected to the sealing device 100 via the Internet, an intranet, or other data communication mechanism. In yet another embodiment, the controller 150 is part of a semiconductor device manufacturing system and is coupled to the sealing device 100 via a suitable data communication mechanism.

[0044] Figure 2A A front view of a gas purger 200 according to some embodiments of the present disclosure. Figure 2B This is a side view of a gas purger 200 according to some embodiments of the present disclosure. Figure 2C This is a top view of a gas purger 200 according to some embodiments of this disclosure. The components of the gas purger 200 described herein correspond to... Figure 1 The components of the gas purger 108.

[0045] In some embodiments, such as Figure 2A , Figure 2B and Figure 2C As shown, the gas purger 200 includes a base portion 202 and a head portion 204. In some embodiments, the base portion 202 is a support base and is assembled to engage with the head portion 204, such that the head portion 204 can be configured adjacent to the back surface 104b and the side surface 104c of the wafer stack 104, as shown. Figure 1 As shown.

[0046] In some embodiments, the base portion 202 is configured to attach to the wafer stage 102 so that the gas purger 200 can be attached to the wafer stage.

[0047] In some embodiments, the base portion 202 includes an airflow path for supplying purge gas to the head portion 204 and for removing purge gas from the head portion (see [link]). Figure 4 ).

[0048] In some embodiments, such as Figure 2B and Figure 2C As shown, the head portion 204 includes a gas diffusion channel 210 disposed on a top surface 204a of the head portion 204. The gas diffusion channel guides the purge gas toward the back surface 104b of the wafer stack 104.

[0049] In some embodiments, the gas diffusion channel 210 is a curved channel. In some embodiments, the gas diffusion channel 210 is an arcuate channel. In some embodiments, the gas diffusion channel 210 is formed by the sidewalls of the head portion 204. In some embodiments, the sidewalls of the head portion 204 include three vertical sidewalls and one non-vertical sidewall to form a path channel for purge gas. The vertical sidewalls are perpendicular to the back surface 104b of the wafer stack 104. In some embodiments, the non-vertical sidewall is disposed on one side of the head portion 204, closer to the sealant nozzle 106 than the three vertical sidewalls. In some embodiments, the non-vertical sidewall includes a top portion 204b and a bottom portion 204c. The top portion 204b and the bottom portion 204c meet and form an inward angle. The top portion 204b and the three vertical sidewalls are combined to guide a purge airflow 208 from the gas diffusion channel 210. In some embodiments, the purge airflow 208 is directed at an acute angle relative to the back surface 104b of the wafer stack 104 and inclined toward the sealant nozzle 106.

[0050] In some embodiments, such as Figure 2C As shown, the arcuate channel has a central angle α relative to the arc of the channel. In some embodiments, the central angle α is in the range of about 5° to about 60°. In some embodiments, the central angle α is in the range of about 10° to about 45°. In some embodiments, the central angle α is in the range of about 25° to about 35°. If the central angle α is less than 5°, there may not be enough vacuum to remove all contaminants. If the central angle α is greater than 60°, the vacuum may become inefficient.

[0051] In some embodiments, the length L of the arcuate channel ranges from about 10 mm to about 150 mm. In some embodiments, the length L of the arcuate channel ranges from about 50 mm to about 90 mm. In some embodiments, the length L of the arcuate channel ranges from about 65 mm to about 75 mm. If the length L is less than 10 mm, there may not be enough vacuum to remove all contaminants. If the length L is greater than 150 mm, the vacuum may become inefficient.

[0052] In some embodiments, the arcuate channel has a radius r. In some embodiments, the radius of the arcuate channel is equal to the radius of the wafer stack 104.

[0053] In some embodiments, such as Figure 2B As shown, the head portion 204 further includes a plurality of vacuum holes 212 disposed on the non-vertical sidewalls (204b and 204c) of the head portion 204. In some embodiments, the plurality of vacuum holes 212 are disposed at the bottom portion 204c of the non-vertical sidewalls (204b and 204c) of the head portion 204.

[0054] In some embodiments, a plurality of vacuum holes 212 are configured to remove undeposited sealant particles and to discharge purge gas from the sealing device 100.

[0055] In some embodiments, the gas purger 200 includes a plurality of lines 206. In some embodiments, the plurality of lines 206 include a purge gas pump line and a venting vacuum line. In some embodiments, the purge gas pump line is configured to couple and / or connect the head portion 204 to an external gas tank (not shown) for supplying purge gas to the sealing device. In some embodiments, the venting vacuum line is configured to couple and / or connect the head portion 204 to a vacuum pump (not shown) for removing purge gas and sealant particles from the sealing device.

[0056] In some embodiments, the airflow path of the base portion 202 includes a first airflow path coupled to and / or connected to the gas diffusion channel 210 and the external gas tank for supplying purge gas to the sealing device 100. In some embodiments, the airflow path of the base portion 202 includes a second airflow path coupled to and / or connected to a plurality of vacuum holes 212 and a vacuum pump for removing and / or discharging purge gas from the sealing device 100.

[0057] Figure 3 This is a perspective view of a head portion 300 of a gas purger according to some embodiments of the present disclosure. The components of the head portion 300 described herein correspond to... Figure 2A , Figure 2B and Figure 2C The components of the head portion 204.

[0058] In some embodiments, such as Figure 3 As shown, the head portion 300 includes a gas diffusion channel 310 disposed on a top surface 304a of the head portion 300.

[0059] In some embodiments, the gas diffusion channel 310 is a curved channel. In some embodiments, the gas diffusion channel 310 is an arc-shaped channel. In some embodiments, the gas diffusion channel 310 is formed by the sidewalls of the head portion 300. In some embodiments, the sidewalls of the head portion 300 include three vertical sidewalls 304d and one non-vertical sidewall (304b and 304c). In some embodiments, the non-vertical sidewall is configured to be closer to the sealant nozzle 106 than the three vertical sidewalls 304d. In some embodiments, the non-vertical sidewall includes a top portion 304b and a bottom portion 304c. The top portion 304b and the bottom portion 304c meet and form an inward-facing angle θ3.

[0060] In some embodiments, such as Figure 3As shown, the head portion 300 further includes a plurality of vacuum holes 312 disposed on the non-vertical sidewalls (304b and 304c) of the head portion 300. In some embodiments, the plurality of vacuum holes 312 are disposed at the bottom portion 304c of the non-vertical sidewalls (304b and 304c) of the head portion 300. In some embodiments, the plurality of vacuum holes 312 are configured to remove and / or discharge purge gas from the sealing device 100.

[0061] In some embodiments, a plurality of vacuum holes 312 are aligned and evenly distributed on the bottom portion 304c of the non-vertical sidewalls (304b and 304c).

[0062] In some embodiments, the plurality of vacuum holes 312 are spaced equally apart from each other.

[0063] In some embodiments, the plurality of vacuum holes 312 includes a first vacuum hole 312a disposed at a center of the bottom portion 304c of the non-vertical sidewalls (304b and 304c). In some embodiments, the first vacuum hole has a first area A1.

[0064] In some embodiments, the plurality of vacuum holes 312 further includes two second vacuum holes 312b respectively disposed on both sides of the first vacuum hole 312a. In some embodiments, each of the two second vacuum holes has a second area A2. In some embodiments, A2 is greater than A1 and less than 2×A1. If the second area A2 is less than the first area A1, the two second vacuum holes 312b may not be able to provide a sufficient vacuum pressure to remove contaminants from the center of the bottom portion 304c of the non-vertical sidewall. If the second area A2 is greater than 2×A1, the two second vacuum holes 312b may generate excessive local airflow interference.

[0065] In some embodiments, the plurality of vacuum holes 312 further includes two third vacuum holes 312c, which are disposed on the side of each of the two second vacuum holes 312b away from the first vacuum hole 312a. In some embodiments, each of the two third vacuum holes has a third area A3. In some embodiments, A3 is greater than 2×A1 and less than 3×A1. If the third area A3 is less than 2×A1, the two third vacuum holes 312c may not be able to provide a sufficient vacuum pressure to remove contaminants from the edge of the bottom portion 304c of the non-vertical sidewall. If the third area A3 is greater than 3×A1, the two third vacuum holes 312c may generate excessive local airflow interference.

[0066] In some embodiments, the total area of ​​the plurality of vacuum holes 312 is approximately 5 mm². 2 approximately 80mm 2Within a certain range. In some embodiments, the total area of ​​the plurality of vacuum holes 312 is approximately 10 mm². 2 Approximately 40mm 2 Within a certain range. In some embodiments, the total area of ​​the plurality of vacuum holes 312 is approximately 20 mm². 2 Approximately 30mm 2 Within a certain range. If the total area of ​​multiple vacuum pores is less than 5mm². 2 If the total area of ​​multiple vacuum holes is greater than 80 mm², then there may not be enough vacuum to remove all contaminants. 2 Vacuum may adversely affect the formation of the sealing layer on the side surface of the wafer stack.

[0067] Although Figure 3 Five vacuum holes 312 are shown, but any suitable number of vacuum holes may be included in the head portion 300. In some embodiments, there may be fewer than five vacuum holes 312 or more than five vacuum holes in the head portion 300.

[0068] In some embodiments, the area of ​​the vacuum hole increases with the increase of a distance between the vacuum hole and the first vacuum hole 312a.

[0069] In some embodiments, such as Figure 3 As shown, the bottom portion 304c of the non-vertical sidewalls (304b and 304c) of the head portion 300 has an angle θ1 relative to a plane parallel to the top surface of the wafer platform 102a. In some embodiments, see back Figure 1 The top surface of wafer platform 102a is flush with the back surface 104b of wafer stack 104. In some embodiments, angle θ1 is an acute angle to improve the efficiency of removing purge gas and / or sealant particles from the sealing device. In some embodiments, angle θ1 is in the range of about 10° to about 85°. In some embodiments, angle θ1 is in the range of about 30° to about 80°. In some embodiments, angle θ1 is in the range of about 40° to about 65°. If angle θ1 is less than 10° or greater than 85°, vacuum may become inefficient for removing all contaminants.

[0070] In some embodiments, such as Figure 3As shown, the top portion 304b of the non-vertical sidewalls (304b and 304c) of the head portion 300 has an angle θ2 relative to a plane parallel to the top surface of the wafer platform 102a. In some embodiments, angle θ2 is an acute angle such that the purge airflow is guided from the gas diffusion channel 210. In some embodiments, the purge airflow is guided at an acute angle relative to the bottom surface of the wafer stack and is inclined toward the sealant nozzle. In some embodiments, angle θ2 is in the range of about 10° to about 85°. In some embodiments, angle θ2 is in the range of about 30° to about 80°. In some embodiments, angle θ2 is in the range of about 40° to about 65°. In some embodiments, angle θ1 is equal to angle θ2. If angle θ2 is less than 10° or greater than 85°, the purge airflow may become inefficient in removing all contaminants.

[0071] Figure 4 This is a side view of a base portion 400 of a gas purger according to some embodiments of this disclosure. The components of the base portion 400 described herein correspond to, for example... Figure 2A , Figure 2B and Figure 2C The components of the base portion 202.

[0072] In some embodiments, such as Figure 4 As shown, the base portion 400 of the gas purger includes: a first airflow path 404 for supplying purge gas to the head portion 204; and a second airflow path 406 for removing purge gas and sealant particles from the sealing device 100 through the head portion.

[0073] In some embodiments, a first airflow path 404 is configured to couple and / or connect the gas diffusion channel 210 to a first pipeline of a plurality of pipelines 206 for supplying purge gas to the sealing device 100. In some embodiments, a second airflow path 406 is configured to couple and / or connect a plurality of vacuum holes 212 to a second pipeline of a plurality of pipelines 206 for removing and / or discharging purge gas and sealant particles from the sealing device 100.

[0074] In some embodiments, a first line is coupled and / or connected to a gas tank (not shown) for supplying purge gas. In some embodiments, a second line is coupled and / or connected to a vacuum pump (not shown) for removing and / or discharging purge gas and sealant particles.

[0075] In some embodiments, the base portion 400 of the gas purger includes a groove 410 configured to connect the base portion 400 and the head portion 204 by inserting a portion of the head portion 204 into the groove 410.

[0076] In some embodiments, the second airflow path 406 includes a plurality of inlet ports 412. In some embodiments, at the base portion 400 and the head portion (e.g., Figure 3 After connection, each of the plurality of inlet ports 412 is configured to couple and / or match a corresponding vacuum port among the plurality of vacuum ports 312 so that purge gas and sealant particles can be removed and / or discharged from the sealing device 100.

[0077] In some embodiments, a plurality of inlet ports 412 are evenly distributed on a central portion of the base portion 402.

[0078] In some embodiments, the plurality of ports 412 are spaced equally apart from each other.

[0079] In some embodiments, the plurality of inlet ports 412 includes a first inlet port 412a configured to engage and mate with a first vacuum aperture 312a. The first inlet port has a fourth area B1. In some embodiments, B1 = A1.

[0080] In some embodiments, the plurality of inlet ports 412 includes two second inlet ports 412b, which are disposed on both sides of the first inlet port 412a and configured to respectively connect and mate with the two second vacuum holes 312b. Each of the two second inlet ports has a fifth area B2. In some embodiments, B2 is greater than B1 and less than 2 × B1. In some embodiments, B2 = A2.

[0081] In some embodiments, the plurality of inlet ports 412 includes two third inlet ports 412c, which are disposed on the side of each of the two second inlet ports 412b away from the first inlet port 412a. The two third inlet ports are configured to engage and mate with the two third vacuum holes 312c respectively. Each of the two third inlet ports has a sixth area B3. In some embodiments, B3 is greater than 2 × B1 and less than 3 × B1. In some embodiments, B3 = A3.

[0082] Although Figure 4 Five inlet ports 412 are shown, but any suitable number of inlet ports may be included in the base portion 400 to match the number of vacuum holes 312 in the head portion 300. In some embodiments, there may be fewer than five inlet ports 412 or more than five inlet ports in the base portion 400.

[0083] Figure 5 This is a close-up view of a portion of a sealing device 500 according to some embodiments of this disclosure. The components of the sealing device 500 described herein correspond to... Figure 1 The components of the sealing device 100.

[0084] In some embodiments, such as Figure 5 As shown, the sealing device 500 includes a wafer stage 502. In some embodiments, the wafer stage 502 is configured to hold a wafer stack 504 on a wafer platform of the wafer stage 502. In some embodiments, the wafer stack 504 has a back surface 504b and a side surface 504c.

[0085] In some embodiments, such as Figure 5 As shown, the sealing device 500 further includes a gas purger 506 disposed on one side of the wafer stage 502. In some embodiments, the gas purger 506 includes a head portion 508 and a base portion 510.

[0086] In some embodiments, the base portion 510 is a support base and is assembled to engage with the head portion 508 such that the head portion 508 can be configured adjacent to a back surface 504b and a side surface 504c of the wafer stack 504.

[0087] In some embodiments, the base portion 510 is configured to attach to the wafer stage 502 such that the gas purger 506 can be attached to the wafer stage 502.

[0088] In some embodiments, a top surface 508a of the head portion 508 is spaced apart from the back surface 504b of the wafer stack 504, so that sealant particles from the sealant flow are not pushed onto the back surface 504b of the wafer stack 504. Furthermore, the space between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is controlled such that a pressure higher than ambient pressure is maintained at the back surface 504b of the wafer stack 504, further preventing sealant particles from the sealant flow from depositing on the back surface 504b of the wafer stack 504.

[0089] In some embodiments, a distance D1 between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is in the range of about 0.5 mm to about 20 mm. In some embodiments, a distance D1 between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is in the range of about 1 mm to about 10 mm. In some embodiments, a distance D1 between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is in the range of about 3 mm to about 7 mm. If the distance D1 between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is less than 0.5 mm, the sealant flow can be pushed toward the back surface 504b of the wafer stack 504. If the distance D1 between the back surface 504b of the wafer stack 504 and the top surface 508a of the head portion 508 is greater than 20 mm, the pressure at the back surface 504b of the wafer stack 504 may not be maintained above the ambient pressure.

[0090] In some embodiments, the head portion 508 is recessed away from the side surface 504c of the wafer stack 504, such that sealant particles from the sealant flow are pushed away from the back side surface 504b of the wafer stack 504. In some embodiments, a distance D2 between the side surface 504c of the wafer stack 504 and an edge 508b of the head portion 508 is in the horizontal direction (e.g., as shown in the figure). Figure 2C The gas diffusion channel 210 shown is in a radial direction 211) ranging from about 0.5 mm to about 20 mm. In some embodiments, the distance D2 between the side surface 504c of the wafer stack 504 and the edge 508b of the head portion 508 is in a horizontal direction ranging from about 1 mm to about 10 mm. In some embodiments, the distance D2 between the side surface 504c of the wafer stack 504 and the edge 508b of the head portion 508 is in a horizontal direction ranging from about 3 mm to about 7 mm. If the distance D2 between the side surface 504c of the wafer stack 504 and the edge 508b of the head portion 508 is less than 1 mm or greater than 10 mm, contaminants may not be removed efficiently.

[0091] Figure 6 A flow field concentration distribution diagram 600 is provided for some embodiments of the present disclosure.

[0092] In some embodiments, such as Figure 6 As shown, flow field concentration distribution diagram 600 illustrates the concentration distribution of sealant particles near a wafer stage 602, a wafer stack 604, a sealant nozzle 606, and a gas purger 608. The wafer stage 602, wafer stack 604, sealant nozzle 606, and gas purger 608 described herein correspond to... Figure 1The wafer stage 102, wafer stack 104, sealant nozzle 106, and gas purger 108 are described.

[0093] like Figure 6 As shown, the concentration of sealant particles is highest at the side surface 604c of the wafer stack 604. Conversely, the concentration of sealant particles is lowest at the back surface 604b of the wafer stack 604.

[0094] In some embodiments, the concentration of sealant particles at the back surface 604b of the wafer stack 604 is reduced by 1,000 to 10,000 times compared to a sealing device without a gas purger. The gas purger blows sealant particles away from the back surface of the wafer stack, thereby reducing sealant particle contamination on the back surface of the wafer stack.

[0095] Figure 7 A flowchart illustrating a method 700 for manufacturing a semiconductor device according to some embodiments of this disclosure is shown. Method 700, or a portion thereof, is controlled by a controller (e.g., Figure 1 150) is executed. In some embodiments, method 700 or a portion thereof is performed by the following description. Figure 8A and 8B The computer system 800 performs and / or controls the process. Method 700 is an example and is not intended to limit the scope of this disclosure or the claimed content. Additional operations may be provided before, during, and after method 700, and some of these operations may be substituted, eliminated, or moved in additional embodiments of method 700.

[0096] In some embodiments, method 700 includes an operation S710, such as Figure 7 As shown. In operation S710, a wafer stack 104 is provided on a wafer stage 102, as... Figure 1 As shown.

[0097] In some embodiments, the wafer stage 102 includes a wafer platform 102a, which is configured to hold a wafer stack 104 on the wafer platform 102a.

[0098] In some embodiments, the method further includes an operation S720, such as Figure 7 As shown. When operating the S720, as... Figure 1 As shown, a sealant flow 106a is directed to the side surface 104c of the wafer stack 104.

[0099] In some embodiments, such as Figure 1As shown, after sealant particles from sealant stream 106a are deposited on the side surface 104c of wafer stack 104, a sealing layer 120 is formed on the side surface 104c of wafer stack 104. In some embodiments, the sealing layer 120 seals the beveled edges of wafer stack 104 to protect the beveled edges of wafer stack 104 from edge chipping.

[0100] In some embodiments, the method further includes an operation S730, such as Figure 7 As shown. When operating the S730, as... Figure 2A As shown, a purge airflow 208 is directed to the back surface 104b of the wafer stack 104.

[0101] In some embodiments, the purge airflow 208 is directed at an acute angle relative to the back surface 104b of the wafer stack 104 and inclined toward the sealant nozzle 106.

[0102] In some embodiments, such as Figure 2A , Figure 2B and Figure 2C As shown, the purge airflow 208 is guided by the gas diffusion channel 210 of the head portion 204 of the gas purger 200.

[0103] In some embodiments, the gas purger 200 is attached to the wafer stage 102, and the head portion 204 is engaged with the base portion 202 to provide a purge gas flow 208. In some embodiments, the method further includes causing the purge gas to flow through the base portion toward the head portion.

[0104] In some embodiments, the gas diffusion channel 210 is disposed at a top surface 204a of the head portion 204. In some embodiments, the method further includes causing purge gas to flow through the gas diffusion channel 210 toward the back surface 104b of the wafer stack 104.

[0105] In some embodiments, a plurality of vacuum holes 212 are disposed on a non-vertical sidewall of the head portion. In some embodiments, the method further includes removing sealant particles and purge gas through the plurality of vacuum holes.

[0106] In some embodiments, operations S730 and S720 are executed simultaneously.

[0107] In some embodiments, the method further includes an operation S740, such as Figure 7 As shown. When operating the S740, as... Figure 1 As shown, sealant particles and purge gas are removed from the sealing device 100.

[0108] In some embodiments, undeposited sealant particles are removed through multiple orifices on the head portion 204 of the gas purger 200. In some embodiments, purge gas is also removed from the sealing device 100.

[0109] In some embodiments, operations S740 and S730 are performed simultaneously.

[0110] Figure 8A and 8B This illustration shows a computer system 800 for implementing the various methods described herein, according to some embodiments of the present disclosure. In some embodiments, the computer system 800 is configured to perform... Figure 1 The functions of controller 150 and / or Figure 7 Method 700 operation.

[0111] Figure 8A is a schematic diagram of a computer system performing the functions of a sealing device. All or part of the programs, methods, and / or operations in the foregoing embodiments can be implemented using computer hardware and the computer programs executed thereon. Figure 8A In a computer system 800, a computer 801 is provided, which includes an optical disc read-only memory (e.g., CD-ROM or DVD-ROM) drive 805 and a disk drive 806, a keyboard 802, a mouse 803 and a screen 804.

[0112] Figure 8B This is a schematic diagram showing an internal configuration of a computer system 800. Figure 8B In addition to the optical disc drive 805 and the disk drive 806, the computer 801 also includes one or more processors, such as: a microprocessor unit (MPU) 811; a read-only memory (ROM) 812 storing a program such as a boot program; a random access memory (RAM) 813 connected to the MPU 811, which temporarily stores an application program command and provides a temporary storage area; a hard disk 814 storing an application program, a system program, and data; and a bus 815 connecting the MPU 811, the ROM 812, and the like. It should be noted that the computer 801 may include a network card (not shown) for providing connectivity to a LAN.

[0113] The program for enabling the computer system 800 to perform the functions of the sealing device in the foregoing embodiments may be stored on an optical disc 821 or a disk 822 inserted into an optical disc drive 805 or a disk drive 806 and transferred to a hard disk 814. Alternatively, the program may be transferred to the computer 801 via a network (not shown) and stored in the hard disk 814. During execution, the program is loaded into RAM 813. The program may be loaded from the optical disc 821 or the disk 822 or directly from a network. The program does not necessarily need to include, for example, an operating system (OS) or a third-party program to enable the computer 801 to perform the functions of the control system for removing contaminant particles from the patterned mask of the lithography system in the foregoing embodiments. The program may simply include a command portion to call an appropriate function (module) in a controlled mode and obtain the desired result.

[0114] The novel apparatus and method disclosed herein provide an improved apparatus and method for manufacturing semiconductor devices, thereby reducing sealant particle contamination on the back surface of a wafer stack. Embodiments of this disclosure provide an apparatus and method using a gas purging module to prevent polymer sealant particles from depositing on the back surface of the wafer, thereby reducing contamination at the wafer edges. Therefore, the defect rate of wafer products can be reduced, and the quality of wafer products can be improved.

[0115] According to some embodiments of this disclosure, a sealing device is provided. The sealing device includes: a wafer stage configured to hold a wafer stack on the wafer stage; and a nozzle disposed on one side of the wafer stage and configured to direct a sealant flow to a side surface of the wafer stack. The sealing device further includes a gas purger disposed on the side of the wafer stage and configured to direct a purge airflow toward a back surface of the wafer stack. In one embodiment, the gas purger includes: a base portion configured to attach the gas purger to the wafer stage; and a head portion configured to engage with the base portion and direct the purge airflow toward the back surface of the wafer stack. In one embodiment, the head portion includes: a gas diffusion channel disposed on a top surface of the head portion and configured to guide the purge gas flow toward the back surface of the wafer stack; and a plurality of vacuum holes disposed on a non-vertical sidewall of the head portion and configured to remove sealant particles and purge gas from the sealing device. In one embodiment, the gas diffusion channel is an arc-shaped channel. The length of the gas diffusion channel is in the range of 50 mm to 90 mm. The central angle of the gas diffusion channel is in the range of 10° to 45°. In one embodiment, the gas diffusion channel is formed by three vertical sidewalls of the head portion and the non-vertical sidewall, and the non-vertical sidewall includes a top portion and a bottom portion forming an inward angle. In one embodiment, the plurality of vacuum holes are disposed on the bottom portion of the non-vertical sidewall. In one embodiment, the plurality of vacuum holes includes: a first vacuum hole disposed at the center of the bottom portion of the non-vertical sidewall, wherein the first vacuum hole has a first area A1; and two second vacuum holes disposed on either side of the first vacuum hole. Each of the two second vacuum holes has a second area A2, and A2 is greater than A1 and less than 2×A1. In one embodiment, the plurality of vacuum holes further includes two third vacuum holes disposed on the side of each of the two second vacuum holes away from the first vacuum hole. Each of the two third vacuum holes has a third area A3, and A3 is greater than 2×A1 and less than 3×A1. In one embodiment, the plurality of vacuum holes are uniformly distributed on the non-vertical sidewall of the head portion. In one embodiment, the total area of ​​the plurality of vacuum holes is 10 mm². 2 Up to 40mm 2 In some embodiments, the distance between the back surface of the wafer stack and the top surface of the head portion is in the range of 1 mm to 10 mm, and the distance between the side surface of the wafer stack and an edge of the head portion is in the range of 1 mm to 10 mm in a horizontal direction.

[0116] According to some embodiments of this disclosure, a gas purging device for a sealing apparatus is provided. The gas purging device includes: a base portion configured to attach the gas purging device to a wafer stage of the sealing apparatus; and a head portion configured to engage with the base portion. The head portion includes: a gas diffusion channel disposed on a top surface of the head portion and configured to guide a purge gas flow toward a back surface of a wafer stack; and a plurality of vacuum holes disposed on a non-vertical sidewall of the head portion and configured to remove sealant particles and purge gas from the sealing apparatus. In one embodiment, the gas diffusion channel is an arc-shaped channel, wherein: a length of the gas diffusion channel is in the range of 50 mm to 90 mm, and a central angle of the gas diffusion channel is in the range of 10° to 45°. In one embodiment, the gas diffusion channel is formed by three vertical sidewalls of the head portion and the non-vertical sidewall, and the non-vertical sidewall includes a top portion and a bottom portion forming an inward angle. In one embodiment, the plurality of vacuum holes are disposed at the bottom portion of the non-vertical sidewall. In one embodiment, the plurality of vacuum holes includes: a first vacuum hole disposed at the center of the bottom portion of the non-vertical sidewall, wherein the first vacuum hole has a first area A1; two second vacuum holes disposed on either side of the first vacuum hole, wherein each of the two second vacuum holes has a second area A2; and two third vacuum holes disposed on the side of each of the two second vacuum holes away from the first vacuum hole, wherein each of the two third vacuum holes has a third area A3, wherein: A2 is greater than A1 and less than 2×A1, and A3 is greater than 2×A1 and less than 3×A1. In one embodiment, the plurality of vacuum holes are uniformly distributed on the non-vertical sidewall of the head portion.

[0117] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes: placing a wafer stack on a wafer stage of a sealing apparatus; and guiding a sealant flow to a side surface of the wafer stack via a nozzle disposed on one side of the wafer stage. The method further includes: guiding a purge gas flow toward a back surface of the wafer stack via a gas purger disposed on the side of the wafer stage; and removing sealant particles and purge gas from the sealing apparatus. In one embodiment, the gas purger includes a base portion and a head portion, and the method further includes: flowing the purge gas through the base portion toward the head portion. In one embodiment, the method further includes: flowing the purge gas through a gas diffusion channel disposed on a top surface of the head portion toward the back surface of the wafer stack; and removing the sealant particles and the purge gas through a plurality of vacuum holes disposed on a non-vertical sidewall of the head portion.

[0118] The foregoing has outlined features of several embodiments or examples to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to perform the same purposes and / or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A sealing device, characterized in that, Include: A wafer stage, which is assembled to hold the wafer stack on the wafer stage; A nozzle, which is disposed on one side of the wafer stage and assembled to guide the sealant flow to the side surface of the wafer stack; as well as A gas purger is disposed on this side of the wafer stage and is assembled to direct the purge airflow toward the back surface of the wafer stack.

2. The sealing device as described in claim 1, characterized in that, The gas purger includes: The base portion, assembled to attach the gas purger to the wafer stage; and The head portion is assembled to connect with the base portion and guides the purge airflow toward the back surface of the wafer stack.

3. The sealing device as described in claim 2, characterized in that, The head portion includes: A gas diffusion channel, disposed on the top surface of the head portion, and configured to guide the purge gas flow toward the back surface of the wafer stack; and Multiple vacuum vents are disposed on the non-vertical sidewalls of the head portion and are assembled to remove sealant particles and purge gas from the sealing device.

4. The sealing device as described in claim 3, characterized in that, The gas diffusion channel is an arc-shaped channel, in which: The length of the gas diffusion channel ranges from 50 mm to 90 mm, and The central angle of the gas diffusion channel ranges from 10° to 45°.

5. The sealing device as described in claim 3, characterized in that, The gas diffusion channel is formed by the three vertical sidewalls of the head portion and the non-vertical sidewall, and The non-vertical sidewall includes a top portion and a bottom portion that form an inward-facing angle.

6. The sealing device as described in claim 3, characterized in that, The plurality of vacuum holes are evenly distributed on the non-vertical sidewall of the head portion.

7. A gas purging device for a sealing device, characterized in that, Include: The base portion is assembled to attach the gas purging device to the wafer stage of the sealing device; as well as The head portion, which is assembled to connect with the base portion, includes: A gas diffusion channel is disposed on the top surface of the head portion and configured to guide a purge gas flow toward a back surface of a wafer stack. as well as Multiple vacuum pores are disposed on the non-vertical sidewalls of the head portion and are assembled to remove sealant particles and purge gas from the sealing device.

8. The gas purging apparatus as described in claim 7, characterized in that, The gas diffusion channel is an arc-shaped channel, in which: The length of the gas diffusion channel ranges from 50 mm to 90 mm, and The central angle of the gas diffusion channel ranges from 10° to 45°.

9. The gas purging device as described in claim 7, characterized in that, The gas diffusion channel is formed by the three vertical sidewalls of the head portion and the non-vertical sidewall, and The non-vertical sidewall includes a top portion and a bottom portion that form an inward-facing angle.

10. The gas purging apparatus as described in claim 9, characterized in that, The multiple vacuum holes are located at the bottom portion of the non-vertical sidewall.

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