Chip package

Abstract

This invention provides a chip package. An optical engine (OE) and a fiber optic mounting unit (FMU) are mounted side-by-side on a package substrate within the chip package. The OE includes an electrical integrated circuit (EIC) die and a photonic integrated circuit (PIC) die stacked vertically. The core of the optical fiber can pass through and be held by the FMU, while being aligned with an edge coupler within the PIC die. The optical fiber can be separately supported by a fixture mounted on a printed circuit board (PCB) along with the chip package. A heat sink can be placed on top of the chip package. The vertical stacking in the OE reduces electrical losses between the EIC and PIC. An edge coupler is used instead of a grating coupler to allow space for the heat sink. The FMU enables precise alignment of the optical fiber to the edge coupler.

Description

Technical Field

[0001] This utility model relates to an integrated circuit, and more particularly to a chip package. Background Technology

[0002] As semiconductor technology continues to advance, the demand for higher-performance components and smaller form factors is constantly increasing. As part of the solution to meet these demands, multiple substrates can be vertically stacked within a chip package. Higher performance, smaller form factors, and vertical stacking all make thermal management more challenging. If not managed properly, heat can degrade the performance of integrated circuit (IC) components, shorten their lifespan, or even lead to catastrophic failures. Thermal management techniques include the use of heat sinks, heat platens, and thermal interface materials (TIMs). Utility Model Content

[0003] This invention provides a chip package. The chip package includes: a packaging substrate having a first side and a second side, wherein the packaging substrate includes a dielectric substrate or a silicon interposer; an optical engine attached to the first side, wherein the optical engine includes an electrical integrated circuit die and a photonic integrated circuit die stacked vertically, the photonic integrated circuit die including an edge coupler; and an optical fiber mounting unit attached to the first side and adjacent to the optical engine, wherein the optical fiber mounting unit holds optical fibers to align with the edge coupler.

[0004] This invention relates to a chip package. The chip package includes: a package substrate, wherein the package substrate comprises a dielectric substrate or a silicon interposer; an optical engine, including a photonic engine integrated circuit die and an electrical engine integrated circuit die, which are mounted to and electrically coupled to the package substrate, wherein the photonic engine integrated circuit die includes an edge coupler; and an optical fiber mounting unit, wherein the optical fiber mounting unit is mounted side-by-side with the optical engine to the package substrate and has a first cavity, the first cavity being positioned to hold the optical fiber for alignment with the edge coupler.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 A cross-sectional view of a system including a chip package according to some aspects of the present invention is shown.

[0007] Figures 2A-2D End views are shown according to different embodiments of the fiber optic mounting unit (FMU).

[0008] Figures 3A-3B An end view of another FMU according to various other embodiments is shown.

[0009] Figure 4-7 A cross-sectional view of a system including a chip package according to various embodiments of the present invention is shown.

[0010] Figures 7A-7C An end view of an optical engine photonic integrated circuit (OEPIC) according to various embodiments is shown.

[0011] Figure 8-14 A cross-sectional view of a system including a chip package according to various other embodiments is shown.

[0012] Figure 15-18 A series of cross-sectional views are provided to show the process of forming and using the chip package according to the present invention.

[0013] Figure 19 This is a flowchart of a process provided according to some embodiments of the present invention.

[0014] Figure 20 This is a flowchart of a process provided according to some other embodiments of the present invention. Detailed Implementation

[0015] This invention provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description may include embodiments where a first feature is formed on or above a second feature, wherein the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact.

[0016] Spatial relative terms, such as "below," "under," "lower," "above," "upper," etc., may be used herein to describe one component or feature relative to another component or feature as shown in the figures. These spatial relative terms are intended to cover different orientations of components or devices or operations in use other than those depicted in the figures. Components or devices may be oriented in other ways (rotated 90° or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly. The terms "first," "second," "third," "fourth," etc., are merely general identifiers and are therefore interchangeable in various embodiments. For example, while a component (e.g., an opening) may be referred to as a "first" component in some embodiments, it may be referred to as a "second" component in other embodiments.

[0017] Optical signals offer significant advantages over electrical signals, especially for long-distance, high-frequency, or high-data-rate transmission. Therefore, in addition to one or more electrical integrated circuit (EIC) chips, high-performance chip packages can also include photonic integrated circuit (PIC) chips. In one architecture, the chip package includes an optical engine (OE) with a PIC chip (OEPIC die) and an EIC (OEEIC die), which cooperate to transmit and / or receive signals through an optical transmission medium.

[0018] The OEEIC die includes electrical circuitry for driving or controlling photonic components within the OEPIC die and / or for processing signals from the OEPIC die. In some packages, the OEEIC die and OEPIC die are configured as a 2.5D structure. In a 2.5D structure, the OEEIC die and OEPIC die are positioned side-by-side above a package substrate and may have the same height and / or have coplanar bottom surfaces. The package substrate may be a dielectric substrate of the type containing a semiconductor substrate, or it may contain a semiconductor substrate. If the package substrate contains a semiconductor substrate, it is referred to as a silicon interposer. The package substrate delivers signals between the OEEIC die and the OEPIC die.

[0019] According to one aspect of this invention, the OEEIC die and OEPIC die are configured as a 3D structure. In the 3D structure, the OEEIC die and OEPIC die are vertically stacked. The 3D structure significantly reduces electrical transmission loss and is more advantageous than the 2.5D structure in meeting the requirements of high-performance chip packages. However, the 3D structure presents significant challenges to the thermal management of coupling the OEEIC die to the optical fiber and other EICs within the OEEIC die and chip package.

[0020] In 2.5D structures, OEPIC dies typically use grating couplers to provide the optical interface with the fiber array. Grating couplers are generally easier to align than edge couplers. Fixtures hold the fiber array to the grating coupler. Problems arise when transitioning to higher-performance components with 3D structures. If an OEPIC die is placed on top of an OEEIC die, the OEPIC die can obstruct heat dissipation from the OEEIC die and fixtures, potentially interfering with the effective placement of heat sinks, etc. If an OEEIC die is placed on top of the OEPIC die, the distance between the fiber array and the OEPIC die increases, creating more variables that can increase sensitivity misalignment and reduce coupling efficiency.

[0021] According to another aspect of the present invention, the OEPIC die includes an edge coupler for connection to an optical fiber array, and the problem of aligning the optical fiber with the edge coupler is solved using an optical fiber mounting unit (FMU) mounted side-by-side with the OE on the encapsulation substrate. The FMU holds one or more optical fibers for alignment with corresponding edge couplers in the OEPIC die. The optical fiber is aligned with a trench in the FMU. In some embodiments, the FMU also has a V-groove at the bottom of the trench for precise positioning. In some embodiments, the optical fiber is embedded in the FMU. In some embodiments, the optical fiber is stripped before being placed in or on the FMU so that the fiber cores can be closely spaced. In some embodiments, an optical fiber array unit including the optical fiber is placed in the FMU. In some embodiments, the optical fiber array unit includes multiple fiber cores embedded in a cladding.

[0022] In some embodiments, the OEPIC die has trenches that provide a base for the fiber core. These structures work in conjunction with the FMU to improve fiber core accuracy, thereby holding the fiber core in alignment with the edge coupler. If the FMU has trenches for the fiber core, the OEPIC die trenches are aligned with the FMU trenches. In some embodiments, the OEPIC die trenches have a rectangular cross-section. In some embodiments, the OEPIC die trenches have V-grooves at their bottom.

[0023] Regardless of whether the OEPIC die is located above or below the OEEIC die, the FMU can maintain the fiber at the height of the edge coupler. Therefore, in some embodiments, the OEPIC die is located above the OEEIC die. In other embodiments, the OEEIC die is located on top. Placing the OEEIC die above the OEPIC die can be advantageous because the OEEIC die can be close to heatsinks or other thermal management components configured above the OE. However, in some cases, similar advantages can be achieved when the OEPIC die is above the OEEIC die. For example, an additional EIC die can be stacked vertically side-by-side with the OEEIC, with the OEPIC die on top of the stack. The additional EIC die is located in a position to communicate with the OEEIC die with lower electrical transmission loss and is also located in a position to be effectively cooled by a heatsink on the die package.

[0024] In some embodiments, the FMU has an upper surface at the same height as the upper surface of the OE and / or is coplanar with the upper surface of the OE. In some embodiments, a heat sink is disposed above the OE and the FMU. The FMU may support the heat sink or facilitate its positioning. In some embodiments, the chip package includes additional EIC dies, one or more of which have the same height as the upper surface of the OE and / or are coplanar with the upper surface of the OE. The heat sink may extend above the upper surface of the additional EIC dies.

[0025] In some embodiments, the OE and FMU are abutted together. Abutting the FMU and OE together facilitates control over the distance between the fiber core and the edge coupler. In some embodiments, the end of the fiber core is aligned with the side of the FMU facing the OE. In some embodiments, the OEEIC die is horizontally aligned with the OEPIC die on the OE side facing the FMU. This configuration allows both the OEEIC and OEPIC dies to abut the FMU and can facilitate stable positioning of the FMU adjacent to the OE.

[0026] In some embodiments, both the OE and FMU are connected to the package substrate via the same type of connection structure. In some embodiments, the attachment structure includes solder bumps for controlled collapse chip connections (C4 solder bumps). At least some of the C4 solder bumps that hold the OE on the package substrate are coupled to the electronic circuitry within the OE. On the other hand, the FMU may not have any electronic circuitry. However, in some embodiments, bonding pads are embedded on the bottom surface of the FMU to provide attachment points for the C4 solder bumps. Using the same type of connection for the OE and FMU can help control the height of the FMU, so that for the edge coupler of the OEPIC die, the FMU can hold the fiber at the correct height.

[0027] In some embodiments, the FMU is bonded to the package substrate. The FMU may consist of a dielectric material that is most easily attached to the package substrate by adhesive. The FMU may be designed to account for the difference between the thickness of the C4 interconnect layer or similar structure used to hold the OE to the package substrate and the height of the adhesive.

[0028] In some embodiments, the FMU is directly bonded to the package substrate. In some embodiments, the bonding is dielectric-to-dielectric bonding. In some embodiments, the bonding is metal-to-metal bonding. In some embodiments, the bonding includes both dielectric-to-dielectric and metal-to-metal bonding. The FMU may be formed of metal or have embedded metal bonding pads to provide metal-to-metal bonding. Dielectric-to-dielectric bonding and metal-to-metal bonding can be a type of covalent bonding or hybrid bonding. Direct bonding eliminates the degree of variation in the height of the FMU relative to the package substrate.

[0029] In some embodiments, the packaging substrate includes a dielectric substrate. In some embodiments, the packaging substrate is a silicon interposer, which is a packaging substrate that includes a semiconductor substrate. The silicon interposer will support higher density interconnects. Dielectric substrates are cheaper and may be easier to use. In some embodiments, a ball grid array (BGA) is disposed on the side of the packaging substrate opposite to the OE and FMU. The BGA can be used to mount the chip package to a printed circuit board (PCB).

[0030] In some embodiments, the optical fiber is supported by a fixture that is attached to the same PCB as the chip package. A portion of the optical fiber and cladding is held by the fixture. The fixture provides mechanical support to the optical fiber, thereby reducing mechanical stress on the end portion where the cladding is deprived. Thus, the optical fiber is held and positioned by the fixture and the FMU. In some embodiments, the optical fiber is further held and positioned within the OEPIC die by a stage.

[0031] Some aspects of this invention relate to a process for assembling a chip package including an OE. The method includes forming an OE on a package substrate, the OE including an OEPIC die and an OEEEIC die in a stacked configuration; and mounting the OE and an FMU side-by-side on the package substrate. In some embodiments, the FMU abuts against the OE. In some embodiments, an additional EIC die is mounted on the package substrate. The package substrate is mounted on a PCB, and a fastener is attached to the PCB. An optical fiber is attached to the fastener, and the cladding is stripped from the end of the optical fiber. The end is placed in a cavity in the FMU, thereby aligning the optical fiber with an edge coupler in the OEPIC die. In some embodiments, the end extends through the FMU into the aligned cavity in the OEPIC die. In some embodiments, the cavity is filled such that the end is embedded in the FMU. This method may also include placing a heat sink on the OE. In some embodiments, the FMU serves to support the heat sink.

[0032] Figure 1 A cross-sectional view or system 100 according to some embodiments is shown. System 100 includes a chip package 101 electrically coupled and mechanically attached to a PCB 149. Chip package 101 includes a package substrate 145, a first EIC die 105, a second EIC die 107, an OE111, and an FMU135. OE111 includes an OEPIC die 118 and an OEEIC die 113 in a vertical stack, wherein the OEEIC die 113 is located above the OEPIC die 118. The first EIC die 105 and the second EIC die 107 are in another vertical stack 103. Vertical stack 103, OE111, and FMU135 are mounted on the package substrate 145. OE111 abuts against FMU135, and OEEIC die 113 and OEPIC die 118 are horizontally aligned on the side of OE111 facing FMU135.

[0033] An optical fiber 141, having a cladding 133 and a core 131, is supported by a fastener 143 attached to a PCB 149. The cladding 133 is stripped from an end portion 129 of the optical fiber 141. The end portion 129 is located in a cavity 127 within an FMU 135, thereby being held in alignment by an edge coupler 115 (i.e., part of an OEPIC die 118). The end is aligned with the edge coupler in the OEPIC die 118. The front end 151 of the end portion 129 can be aligned with the edge 153 of the OEPIC die 118.

[0034] Figure 2A An end view 200 of an FMU135 is provided according to one embodiment. In end view 200, the aperture 127 of the FMU135 is a channel having a rectangular shape. There can be multiple apertures 127. Therefore, optical fiber 141 (see...) Figure 1 () can be one of the multiple optical fibers 141 in the optical fiber array.

[0035] Figure 2B An end view 210 of an FMU135 according to another embodiment is provided. In end view 210, a V-groove 211 is provided at the bottom of the cavity 127. The V-groove 211 may help to fix the position of the core 131.

[0036] Figure 2C An end view 220 of an FMU135 according to another embodiment is provided. In end view 220, the cavity 127 is a hole through the FMU135, rather than a channel.

[0037] Figure 2D An end view 230 of the FMU135, consistent with another embodiment, is provided. In the end view 230, the cavity 127 has a V-shaped bottom 231. The V-shaped bottom 231 may help to fix the position of the core 131.

[0038] Figure 3A The FMU301A provides an end view 300, which can be used to replace Figure 1 The FMU301A differs from the FMU135 in that it does not have a hole 127 for receiving a separate core 131 (see FMU135). Figures 2A-2D Instead, it has a cavity 302 that is larger and sized to receive the fiber array unit 303. The fiber array unit 303 includes a plurality of cores 131 embedded in a cladding 307. The cladding 307 may be located inside a sheath 305. Because all the cores 131 are embedded in a single cladding 307, they can be placed more closely together than if each were individually clad. For example, the cores 131 may have a diameter in the range of about 8 micrometers to about 10 micrometers. Cladding 133 (see Figure 1The core 131 may have a diameter of approximately 125 micrometers, which is more than 10 times the diameter of the core. Furthermore, a protective layer may be present around the cladding, approximately 250 micrometers in diameter, which is more than 20 times the diameter of the core. In some embodiments, the spacing of the cores 131 in the fiber array unit 303 is approximately 10 times or less the diameter of the core 131. In some embodiments, the spacing of the cores 131 in the fiber array unit 303 is approximately 5 times or less the diameter of the core 131.

[0039] Figure 3B An end view 310 of the FMU301B is provided. The FMU301B differs from the FMU301A in that it includes a slot 315 for receiving the fiber array unit 303.

[0040] return Figure 1 A heat sink 121, including a heat sink 123, is disposed on the chip package 101. A thermal interface material 125 may be applied to the first EIC die 105, the OEEIC die 113, and an optional FMU 135 to improve heat transfer between the chip package 101 and the heat sink 121.

[0041] OEIC die 113 and OEPIC die 118 can be bonded together via contact pad 117, solder microbumps, etc., or via any other suitable structure (e.g., hybrid bonding). Similarly, first EIC die 105 and second EIC die 107 can be bonded together via contact pad 106, solder microbumps, etc., or via any other suitable structure (e.g., hybrid bonding). Vertical stack 103, OE111, and FMU135 are bonded to package substrate 145 via controlled collapsed chip connection (C4) solder bumps 119 in C4 connection structure 137, etc., or via some other structure providing electrical connection for vertical stack 103 and OE111. Chip package 101 is connected to PCB 149 via solder balls 147 in ball grid array (BGA) 109, via wires, etc., or via some other suitable structure.

[0042] Edge coupler 115 can be a silicon edge coupler, silicon nitride edge coupler, oxide nitride edge coupler, polycrystalline silicon coupler, amorphous silicon coupler, or any other type of edge coupler. In some embodiments, edge coupler 115 includes multiple polarization-independent optical core segments, enabling edge coupler 115 to operate to receive a wide range of wavelengths. In some embodiments, OE111 supports wavelength division multiplexing (WDM). WDM enables high data transmission rates.

[0043] In addition to the edge coupler 115, the OEPIC die 118 includes one or more photonic components that transmit, receive, propagate, generate, modify, or detect optical signals and components that convert optical signals into electrical signals or vice versa. Examples of photonic components include waveguides, beam splitters, multiplexers, waveguides, modulators (e.g., pin modulators or electroabsorption modulators), sensors, switches (e.g., Mach-Zehnder interferometers), amplifiers, edge couplers, ring resonators, etc. Examples of components that convert electrical signals into optical signals include laser diodes, light-emitting diodes, etc. Examples of components that convert optical signals into electrical signals include photodetectors, etc.

[0044] OEEIC die 113 is configured to receive electrical signals from OEPIC die 118. These electrical signals may correspond to optical signals received by OEPIC die 118 from optical fiber 141. OEEIC die 113 also includes circuitry that sends electrical signals to OEPIC die 118, including electrical signals that control and / or provide power to components of OEPIC die 118. The circuitry or OEEIC die 113 may enable or enable the functionality of OEPIC die 118 by providing signal processing, control, drivers, etc. Signal processing may include amplification, filtering, etc. The amplifier in OEEIC die 113 may correspond to a photodetector, etc., in OEPIC die 118. The driver in OEEIC die 113 may drive laser diodes, light-emitting diodes, modulators, etc., in OEPIC die 118. OEEIC die 113 may also provide an interface between OEPIC die 118 and the second EIC die 107. The OEEIC die 113 can also be equipped with additional features that are unrelated to the OEPIC die 118.

[0045] Each of the first EIC die 105 and the second EIC die 107 may include digital, analog, or mixed-signal circuitry, and may be or include, for example, a switching chip, a system-on-a-chip (SOC), an application-specific integrated circuit (ASIC), a central processing unit (CPU), a display adapter processing unit (GPU), a data processing unit (DPU), a memory assembly, a power management unit (PMU), etc. The first EIC die 105 and the second EIC die 107 may include semiconductor devices, such as transistors, diodes, capacitors, memory cells, gate fluids, resistors, etc., or any combination thereof. Transistors may be complementary metal-oxide-semiconductor (CMOS) transistors, planar CMOS transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors, nanosheet transistors, or any other suitable type of transistor. Memory assemblies may be high-bandwidth memory (HBM), static random-access memory (SRAM), dynamic random-access memory (DRAM), non-volatile memory (NVM), three-dimensional (3D) memory, computation in memory (CIM), some other suitable memory, or any combination thereof. Memory components may include resistive random access memory (RRAM) cells, phase change memory (PCM) cells, magnetoresistive random access memory (MRAM) cells, or some other types of memory cells.

[0046] The packaging substrate 145 includes a substrate and provides delivery of electrical signals. The packaging substrate 145 may include metal interconnect layers, through-hole layers, substrate vias (TSVs), contact pads, etc. In some embodiments, the substrate is a dielectric substrate. The dielectric substrate may be, for example, an organic polymer substrate, or some other suitable dielectric material. Examples of organic polymer substrate materials include, but are not limited to, polyimide, polytetrafluoroethylene, epoxy resin, etc. The epoxy resin may be one formed from bismaleimide triazine resin (BT-resin), some other epoxy resin, etc. The dielectric substrate may be laminated and may be reinforced with glass cloth, glass fiber, etc. In some embodiments, the substrate is a semiconductor substrate. The semiconductor may be silicon (Si), a III-V semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), higher-order semiconductor, etc., or any other suitable semiconductor.

[0047] FMU135 can be any suitable composition. In some embodiments, FMU135 is or includes a dielectric. In some embodiments, FMU135 is or includes an organic polymer. The organic polymer can be, for example, polyimide, polytetrafluoroethylene, epoxy resin, etc. The organic polymer can be rigid, and the light weight can be easily provided with a suitable shape.

[0048] Heat sink 121 is a radiator that includes heat sink 123. The heat sink can be any good thermal conductor and is located on the chip package 101. Heat sink 121 can be or includes a metal, such as aluminum, copper, nickel, cobalt, some other metals, alloys, etc., or it can be another good thermal conductor, such as graphite. In some embodiments, heat sink 121 includes fins 120.

[0049] The thermal interface material 125 can be a soft material that is a good thermal conductor and can be used to improve the thermal contact between the OEEIC die 113 and the heat sink 123. The thermal interface material 125 can be, for example, a polymer, wax, viscous silicone, a combination thereof, etc. In some embodiments, the thermal interface material 125 is a grease, gel, etc.

[0050] Figure 4 A cross-sectional view of system 400 is shown. System 400 is similar. Figure 1 System 100 is an alternative to system 400, except that system 400 includes a cold plate 401 instead of a heat sink 121. The cold plate 401 serves as both a radiator and part of a liquid cooling system. The liquid cooling system includes the cold plate 401, a cooler (not shown), and a pump (not shown). The cooler and the cold plate 401 have internal channels and can be interconnected via hoses or the like. The pump circulates fluid between the cooler and the cold plate 401, thereby transferring heat from the cold plate 401 to the cooler. The cooler can be placed in a remote location and release the heat absorbed from the cold plate 401 to the surrounding environment. A fan can be directed at the cooler to improve its efficiency.

[0051] Figure 5 A cross-sectional view of system 500 is shown. System 500 is similar. Figure 1 System 100, except that system 500 includes a cover 501 instead of heat sink 121. Cover 501 is another type of heat sink and may be or contain metal. Cover 501 can be placed on packaging substrate 145. Cover 501 may have a slot 503 so that cover 501 can be mounted on optical fiber 141. Figure 1 Heat sink 121 or Figure 4 The cold sheet material 401 can be selectively placed on top of the cover 501.

[0052] Figure 6 A cross-sectional view of system 600 is shown. System 600 can be similar. Figure 1System 100 is the same as system 600, except that system 600 replaces chip package 101 with chip package 601. Chip package 601 is similar to chip package 101, but OE111 is replaced by OE111A and FMU135 is replaced by FMU135A. In OE111A, OEPIC die 118 is stacked vertically above OEEEIC die 113. This architecture allows additional EIC dies 603 to be arranged vertically with OEEEIC die 113 near heatsink 123. Additional EIC dies 603 can implement any of the possible functions described as first EIC die 105 or second EIC die 107. Functions in OEEEIC die 113 can also be offloaded to additional EIC die 603, in which case a function with greater thermal intensity can be selected for offloading. FMU135A is similar. Figure 1 The FMU135, except that the hole 127 is shallower to align the fiber 141 with the edge coupler 115 in the OEPIC die 118 above the OEEIC die 113.

[0053] The additional EIC die 603 is coupled to the OEEIC die 113 via contact pads 117, solder microbumps, or other types of high-density connections (e.g., hybrid bonding). Vertical stacking with such connectivity can achieve higher speeds or lower communication losses between the additional EIC die 603 and the OEEIC die 113 compared to connections via the package substrate.

[0054] Figure 7 A cross-sectional view of system 700 is shown. System 700 can be similar. Figure 1 System 100, except that System 700 uses the OEPIC die 118A instead of the OEPIC die 118. The OEPIC die 118A and... Figure 1 The difference between the OEPIC die 118 and the OEPIC die 118A is that the OEPIC die 118A has a hole 701 for receiving the end portion 129 of the optical fiber 141. The hole 701 can increase the accuracy of the positioning of the optical fiber 141 relative to the edge coupler 115, and thereby improve the coupling efficiency.

[0055] Figure 7A An end view 720 of the OEPIC die 118A according to an embodiment is shown, wherein the via 701 is a rectangular trench. The rectangular trench can be formed, for example, by a dry etching process such as plasma etching.

[0056] Figure 7B An end view 740 of the OEPIC die 118A according to an embodiment is shown, wherein the cavity 701 is a channel with a V-groove 703 at its bottom. The channel and the V-groove 703 can be formed, for example, by a wet etching process. The V-groove 703 can improve the alignment of the core 131.

[0057] Figure 7C An end view 760 of an OEPIC die 118A according to an embodiment is shown, wherein a cavity 701 and a via are formed on the side of the OEPIC die 118A. The via can be etched on one side of the OEPIC die 118A by a dry etching process or the like. The via in the OEPIC die 118A can provide more precise alignment of the core 131 than a trench.

[0058] Figure 8 A cross-sectional view of system 800 is shown. System 800 can be similar. Figure 6 The System 600, except that the System 600 uses the OEPIC chip 118A instead of the OEPIC chip 118. The System 800 combines... Figure 6 The advantages of System 600 and Figure 7 The advantages of System 700.

[0059] Figure 9 A cross-sectional view of system 900 is shown. System 900 can be similar. Figure 7 The system is 700, except that the system 900 uses the FMU135B instead of the FMU135. The difference between the FMU135B and the FMU135 is that the FMU135B may lack cavity 127 (see...). Figure 7 In the FMU135B, the end portion 129 is not located in the cavity 127, but is embedded in the FMU135B. Embedding increases the security of the end portion 129 and makes the coupling between the fiber 141 and the edge coupler 115 more stable and effective under exposure to vibration or other such mechanical disturbances.

[0060] Figure 10 A cross-sectional view of system 1000 is shown. System 1000 can be similar. Figure 8 The System 800, except that the System 1000 uses the FMU135C instead of the FMU135A. The System 1000 incorporates... Figure 8 The advantages of System 800 and Figure 9 The advantages of System 900.

[0061] Figure 11 A cross-sectional view of system 1100 is shown. System 1100 can be similar. Figure 1 System 100, except that System 1100 replaces chip package 101 with chip package 101A. Chip package 101A can be similar to chip package 101 (see...) Figure 1The chip package 101A uses a silicon interposer 1101. In addition to the package substrate 145, the silicon interposer 1101 can also be used, in which case the package substrate 145 may include a dielectric substrate. The silicon interposer 1101 includes a dielectric layer 1103 over a semiconductor substrate 1105. Metal interconnect structures (not shown) may be formed in the dielectric layer 1103. The dielectric layer 1103 may include one or more layers or any suitable dielectric. In some embodiments, the dielectric layer 1103 includes a low-κ dielectric. In some embodiments, the dielectric layer 1103 includes an extremely low-κ dielectric. Examples of low-κ dielectrics include organosilicon glasses (OSGs), such as carbon-doped silicon dioxide, fluorine glass (FSG), porous silicate glasses, etc. Extremely low-κ dielectrics may be low-κ dielectrics with porosity, thereby reducing the effective dielectric constant. Vertical stack 103 and OE111 can be coupled to silicon interposer 1101 via contact pad 1107, solder microbumps, or other types of high-density connections (e.g., hybrid bonding). Silicon interposer 1101 can improve data rates and reduce communication losses between vertical stack 103 and OE111.

[0062] Figure 12 A cross-sectional view of system 1200 is shown. System 1200 can be similar. Figure 10 System 1000, except that System 1200 uses chip package 601A instead of chip package 601. Chip package 601A is similar to chip package 601 (see...). Figure 10 However, it uses a silicon interposer 1101. System 1200 incorporates... Figure 10 The advantages of System 1000 and Figure 11 The advantages of System 1100.

[0063] Figure 13 A cross-sectional view of system 1300 is shown. System 1300 may be similar to... Figure 6 In System 600, except in System 1300, the FMU135A is bonded to the packaging substrate 145 via adhesive 1301. Adhesive 1301 can be epoxy or some other suitable type of adhesive. Adhesive 1301 can provide a more secure FMU135A connection than C4 connection structure 137.

[0064] Figure 14 A cross-sectional view of system 1400 is shown. System 1400 can be similar. Figure 6The system 600 differs from system 1400 in that the FMU135A is directly bonded to the packaging substrate 145. In some embodiments, the bonding is covalent. In some embodiments, the bonding is a plasma-processed covalent bonding. The bonding may include dielectric-to-dielectric bonding, metal-to-metal bonding, or a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. Contact pads may be embedded within the FMU135A to allow metal-to-metal bonding. Coating may be applied to the bottom surface of the FMU135A and / or the top surface of the packaging substrate 145 to facilitate dielectric-to-dielectric bonding or plasma-processed covalent bonding. In some embodiments, the coating includes silicon carbide (SiCN), silicon oxynitride (SiON), combinations thereof, etc. Direct bonding can facilitate precise control of the height of the FMU135A holding the optical fiber 141.

[0065] Figure 15-18 A series of sectional views 1500-1800 are provided, illustrating the system at various manufacturing stages according to the present invention. Although Figure 15-18 This is described in relation to a series of actions; however, it should be understood that the order of the actions can be changed in some cases, and this series of actions also applies to structures other than those shown. In some embodiments, some of these actions may be omitted entirely or in part. Furthermore, Figure 15-18 It is described in relation to a series of actions; it should be understood that... Figure 15-18 The structure shown is not limited to the manufacturing method, but can be used as a separate structure from the method.

[0066] like Figure 15 As shown, the method can begin with the individual fabrication of each of the vertically stacked 103, OE111, and FMU135.

[0067] like Figure 16 As shown, vertical stack 103, OE111, and FMU135 are all mounted on packaging substrate 145 to form chip package 101. In some embodiments, OE111 and FMU135 are adjacent to each other. The alignment between via 127 and edge coupler 115 can be selectively fine-tuned during the bonding process. An index-matching material (with a refractive index close to ~1.45 for silicon dioxide) can be used to fill the gap between OE111 and FMU135.

[0068] like Figure 17As shown, chip package 101 is mounted on PCB 149. PCB 149 typically includes a dielectric substrate and metal interconnect structures. Chip package 101 can be mounted on PCB 149 via BGA 109. BGA 109 can be attached to chip package 101 before chip package 101 is placed on PCB 149. Fixing member 143 can be connected to PCB 149 before or after mounting chip package 101.

[0069] like Figure 18 As shown, cladding 133 is stripped from end portion 129 of optical fiber 141, and end portion 129 is placed in cavity 127 such that core 131 of optical fiber 141 is aligned with edge coupler 115 in OEPIC die 118. Optical fiber 141 can then be secured to fastener 143. In some embodiments, fastener 143 surrounds optical fiber 141. Cavity 127 can be selectively filled such that end portion 129 is embedded within FMU 135. Heat sink 121 can be placed on top of chip package 101 to provide... Figure 1 The structure of system 100 shown.

[0070] Figure 19 A flowchart of a method 1900 for forming a system according to some embodiments of the present invention is provided. Although method 1900 is shown and described below as a series of actions or events, it should be understood that the shown order of such actions or events should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown need to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0071] Method 1900 may begin with action 1901, assembling an OE assembly, including an OEPIC chip and an OEEIC die, in a vertical stack. In some embodiments, the OEEIC die is positioned above the OEPIC die. Figure 1 The OE111 in System 100 provides an example. In some embodiments, the OEPIC die is located above the OEEIC die. System 600 or Figure 6 The OE111A provides an example. In some embodiments, vertical stacking is formed during chip-level processing prior to dicing.

[0072] Action 1903 involves mounting the OE and FMU side-by-side on the package substrate. In some embodiments, the FMU abuts against the OE. Other chips may also be selectively mounted on the package substrate. Figure 16 The sectional view 1600 is an example.

[0073] Action 1905 involves mounting the package substrate to the PCB. The package substrate can be connected to the PCB via a BGA or some other suitable structure. Figure 17 The sectional view 1700 is an example.

[0074] Action 1907 is removing the cladding from the end portion of the optical fiber. Action 1909 is aligning the end portion of the optical fiber with the edge coupler in the OE using the FMU. Aligning the end portion using the FMU may include placing the end portion into a cavity formed in the FMU. Figure 18 The cross-sectional view 1800 is an example. In some embodiments, the end portion extends into a cavity formed in the OE. The package substrate, OE, and FMU together, and optionally with additional chip and / or component layers, form a chip package.

[0075] Action 1911 involves securing the optical fiber to the fastener so that the fiber is individually supported by the FMU. The fastener itself can be connected to the PCB. The fastener can be any type of structure that provides physical support for the optical fiber or fiber array.

[0076] Action 1913 involves placing the heatsink onto the chip package. Thermal interface material may be selectively applied to the chip package and / or the heatsink before placement onto the chip package. Figure 1 System 100 and Figure 4-14 Systems 400-1400 are examples of systems that can be manufactured using this process.

[0077] Figure 20 Provide a flowchart for Method 2000, which is Figure 19 A variation of method 1900. Method 2000 includes action 2001 (placing the fiber array unit on or inside the FMU) and action 2003 (fixing the fiber array unit to the fixture). Method 2000 is associated with fiber array units and Figures 3A-3B Use the FMU of the type shown.

[0078] Some aspects of this invention relate to a chip package including a packaging substrate having a first side and a second side. An optical engine is bonded to the first side. The optical engine includes an electrical integrated circuit die and a photonic integrated circuit die, and is vertically stacked. The photonic integrated circuit die includes an edge coupler. An optical fiber mounting unit is bonded to the first side adjacent to the optical engine. The optical fiber mounting unit secures the optical fiber in alignment via the edge coupler.

[0079] In some embodiments of the present invention, the chip package further includes a heat sink, wherein the heat sink is located above the optical engine. In some embodiments of the present invention, the electrical integrated circuit die is located above the photonic integrated circuit die. In some embodiments of the present invention, the chip package further includes a second electrical integrated circuit die, coupled to and located above the electrical integrated circuit die, wherein the photonic integrated circuit die is located above the electrical integrated circuit die. In some embodiments of the present invention, the photonic integrated circuit die defines a cavity, and the core of the optical fiber extends from the optical fiber mounting unit to the cavity. In some embodiments of the present invention, the optical fiber includes a core and a cladding surrounding the core, and the cladding is stripped from the core at the end of the optical fiber within the optical fiber mounting unit. In some embodiments of the present invention, the optical fiber is embedded in the optical fiber mounting unit. In some embodiments of the present invention, the optical fiber is within an optical fiber array unit held by the optical fiber mounting unit. In some embodiments of the present invention, the optical fiber mounting unit is soldered to the first side. In some embodiments of the present invention, the optical fiber mounting unit is adhered to the first side. In some embodiments of the present invention, the fiber optic mounting unit is bonded to the first side via dielectric-to-dielectric bonding. In some embodiments of the present invention, the fiber optic mounting unit has an optical engine at the same height as the fiber. In some embodiments of the present invention, the chip package further includes a chip stack bonded to the first side, wherein the chip stack and the optical engine extend together in height. In some embodiments of the present invention, the package substrate is a silicon interposer.

[0080] Some aspects of this invention relate to a chip package including a packaging substrate, an optical engine, and an optical fiber mounting unit. The optical engine includes a photonic integrated circuit die and an electrical integrated circuit die mounted to and electrically coupled to the packaging substrate. The photonic integrated circuit die includes an edge coupler. The optical fiber mounting unit is a structure mounted side-by-side to the packaging substrate with the optical engine and has a first cavity positioned to secure the optical fiber in alignment via the edge coupler.

[0081] In some embodiments of this invention, the photonic integrated circuit die includes a second cavity positioned to hold the optical fiber aligned with the edge coupler.

[0082] The foregoing summary of features and embodiments enables those skilled in the art to better understand various aspects of the present invention. Those skilled in the art will understand that they can readily use the present invention as a basis for designing or modifying other processes, and use the structure to achieve the same purpose and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A chip package, characterized in that, include: A packaging substrate having a first side and a second side, wherein the packaging substrate includes a dielectric substrate or a silicon interlayer; An optical engine, coupled to the first side, wherein the optical engine includes an electrical integrated circuit die and a photonic integrated circuit die stacked vertically, the photonic integrated circuit die including an edge coupler; and An optical fiber mounting unit is attached to the first side and adjacent to the optical engine, wherein the optical fiber mounting unit holds the optical fiber to align with the edge coupler.

2. The chip package according to claim 1, characterized in that, It also includes a heat sink, wherein the heat sink is on the optical engine and the electrical integrated circuit die is on the photonic integrated circuit die.

3. The chip package according to claim 1, characterized in that, It also includes an electrical integrated circuit die, coupled to the electrical integrated circuit die, and on top of the electrical integrated circuit die, wherein the photonic integrated circuit die is on top of the electrical integrated circuit die.

4. The chip package according to claim 1, characterized in that, The photonic integrated circuit die defines a cavity, and the core of the optical fiber extends from the optical fiber mounting unit to the cavity.

5. The chip package according to claim 1, characterized in that, The optical fiber includes a core and a cladding surrounding the core, and the cladding is stripped from the core at the end of the optical fiber within the optical fiber mounting unit.

6. The chip package according to claim 1, characterized in that, The optical fiber is embedded in the optical fiber mounting unit.

7. The chip package according to claim 1, characterized in that, The optical fiber is located within an optical fiber array unit held by the optical fiber mounting unit.

8. The chip package of claim 1, wherein the fiber optic mounting unit is soldered to or adhered to the first side, or is joined to the first side via dielectric-to-dielectric bonding.

9. A chip package, characterized in that, include: A packaging substrate, wherein the packaging substrate includes a dielectric substrate or a silicon interposer; An optical engine, including a photonic engine integrated circuit die and an electrical engine integrated circuit die, is mounted to and electrically coupled to the package substrate, wherein the photonic engine integrated circuit die includes an edge coupler; as well as An optical fiber mounting unit, wherein the optical fiber mounting unit is mounted side-by-side with the optical engine to the encapsulation substrate and has a first cavity positioned to hold the optical fiber for alignment with the edge coupler.

10. The chip package according to claim 9, characterized in that, The photonic engine integrated circuit die includes a second cavity positioned to hold the optical fiber in alignment with the edge coupler.

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