Chip stacking heat dissipation structure and electronic device

Abstract

This application discloses a chip stacking heat dissipation structure and electronic device, relating to the field of semiconductor technology. The chip stacking heat dissipation structure includes a substrate, at least two first chips, a second chip, a third chip, and a heat sink. The at least two first chips are mounted upright on the substrate and electrically connected to it. The heat sink covers the at least two first chips and has connection holes and receiving slots. The connection holes correspond to the positions of the first chips, and the receiving slots are located between the at least two first chips. A through hole is provided at the bottom of the receiving slot. The second chip is flip-chip mounted in the receiving slot and electrically connected to the substrate through the through hole. The third chip is mounted upright on the sidewall of the receiving slot and electrically connected to the first chips through the connection holes. A thermal adhesive layer is disposed within the receiving slot, with the top surface of the thermal adhesive layer at least flush with the top of the receiving slot. The bottom surface of the third chip contacts the thermal adhesive layer. This chip stacking heat dissipation structure can effectively improve the heat dissipation performance of the stacked chips.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a chip stacking heat dissipation structure and electronic device. Background Technology

[0002] With the rapid development of the semiconductor industry, flip-chip hybrid packaging structures have been widely used due to their significant advantages in meeting the multifunctionality and miniaturization requirements of electronic packaging products. However, as stacking density continues to increase, the operating temperature of the chips also rises sharply. This can not only cause thermal failure issues but also lead to temporary device failure or even permanent damage due to warping of the stacked chips. Utility Model Content

[0003] The purpose of this application is to provide a chip stacking heat dissipation structure and electronic device, which can effectively improve the heat dissipation performance of stacked chips, thereby avoiding thermal failure and warping problems of stacked chips, and thus improving the stability and reliability of electronic devices.

[0004] The embodiments of this application are implemented as follows: A first aspect of this application provides a chip stacking heat dissipation structure, including a substrate, at least two first chips, a second chip, a third chip, and a heat dissipation cover. The at least two first chips are mounted upright on the substrate and electrically connected to the substrate. The heat dissipation cover is disposed on the at least two first chips. The heat dissipation cover is provided with a connection hole and a receiving groove. The connection hole corresponds to the position of the first chip. The receiving groove is located between the at least two first chips. The bottom of the receiving groove is provided with a through hole. The second chip is flipped in the receiving groove and electrically connected to the substrate through the through hole. The third chip is mounted upright on the side wall of the receiving groove and electrically connected to the first chip through the connection hole. A thermal adhesive layer is provided in the receiving groove, and the top surface of the thermal adhesive layer is at least flush with the top of the receiving groove. The bottom surface of the third chip is in contact with the thermal adhesive layer.

[0005] In one possible implementation, a first gap is formed between the sidewall of the second chip and the sidewall of the receiving groove, and the first gap is filled with the thermal adhesive layer.

[0006] In one possible implementation, a second gap is provided between the bottom surface of the second chip and the bottom of the receiving groove, and the second gap is filled with the heat-dissipating adhesive layer.

[0007] As one possible implementation, along the line connecting the third chip to the substrate, the distance between the bottom of the heat sink and the top surface of the substrate is less than or equal to the distance between the bottom surface of the first chip and the top surface of the substrate.

[0008] As one possible implementation, a fixing adhesive layer is provided between the bottom of the heat sink cover and the bottom surface of the first chip and the top surface of the substrate.

[0009] As one possible implementation, a fourth chip is also included, which is flip-chip mounted on the first chip and electrically connected to the first chip. The fourth chip is located below the third chip and is arranged adjacent to the second chip.

[0010] As one possible implementation, along the line connecting the third chip to the substrate, the orthographic projection of the fourth chip on the substrate and the orthographic projection of the first chip on the substrate have overlapping and non-overlapping areas. The bottom surface of the fourth chip is provided with at least two bumps. The bumps located in the overlapping area are electrically connected to the first chip, and the bumps located in the non-overlapping area are electrically connected to the substrate.

[0011] In one possible implementation, the first chip is electrically connected to the substrate via a first wire bonding, and the third chip is electrically connected to the first chip via a second wire bonding, wherein both the first wire bonding and the second wire bonding are disposed within the connection hole.

[0012] As one possible implementation, it also includes a molding compound disposed on the substrate and covering the third chip and the heat sink.

[0013] A second aspect of this application provides an electronic device including the chip stack heat dissipation structure described above.

[0014] The beneficial effects of the embodiments of this application include: This chip stacking heat dissipation structure includes a substrate, at least two first chips, a second chip, a third chip, and a heat sink. The at least two first chips are mounted upright on the substrate and electrically connected to it. The heat sink covers the at least two first chips and has connection holes and receiving slots. The connection holes correspond to the positions of the first chips, and the receiving slots are located between the at least two first chips. A through-hole is provided at the bottom of the receiving slot. The second chip is flip-chip mounted in the receiving slot and electrically connected to the substrate through the through-hole. The third chip is mounted upright on the sidewall of the receiving slot and electrically connected to the first chips through the connection holes. A thermal adhesive layer is disposed within the receiving slot, with the top surface of the thermal adhesive layer at least flush with the top of the receiving slot, and the bottom surface of the third chip contacting the thermal adhesive layer. This chip stacking heat dissipation structure, through reasonable spatial layout and heat dissipation design, effectively solves the heat dissipation and stability problems of stacked chips while achieving efficient integration of multiple chips, significantly improving the reliability of electronic devices. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is one of the schematic diagrams of the chip stacking heat dissipation structure provided in the embodiments of this application; Figure 2 This is the second schematic diagram of the state of the chip stacking heat dissipation structure provided in the embodiments of this application.

[0017] Icons: 100 - Chip stacking heat dissipation structure; 10 - Substrate; 20 - First chip; 21 - First wire bonding; 30 - Second chip; 40 - Third chip; 41 - Second wire bonding; 50 - Heat sink cover; 51 - Connecting hole; 52 - Receiving groove; 521 - Through hole; 60 - Thermal adhesive layer; 70 - Fixing adhesive layer; 80 - Fourth chip; 81 - Bump; 90 - Molded enclosure. Detailed Implementation

[0018] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0019] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending over another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless expressly defined herein.

[0022] Please refer to the reference. Figure 1 and Figure 2 In a first aspect, a chip stack heat dissipation structure 100 is provided, including a substrate 10, at least two first chips 20, a second chip 30, a third chip 40, and a heat dissipation cover 50. At least two first chips 20 are mounted upright on the substrate 10 and electrically connected to the substrate 10. The heat dissipation cover 50 covers the at least two first chips 20. The heat dissipation cover 50 is provided with a connection hole 51 and a receiving groove 52. The connection hole 51 corresponds to the position of the first chip 20. The receiving groove 52 is located between the at least two first chips 20. A through hole 521 is provided at the bottom of the receiving groove 52. The second chip 30 is flipped in the receiving groove 52 and electrically connected to the substrate 10 through the through hole 521. The third chip 40 is mounted upright on the side wall of the receiving groove 52 and electrically connected to the first chip 20 through the connection hole 51. A heat dissipation adhesive layer 60 is provided in the receiving groove 52, and the top surface of the heat dissipation adhesive layer 60 is at least flush with the top of the receiving groove 52. The bottom surface of the third chip 40 is in contact with the heat dissipation adhesive layer 60.

[0023] It should be noted that the chip stack heat dissipation structure 100 includes a substrate 10, at least two first chips 20, a second chip 30, a third chip 40, and a heat dissipation cover 50. At least two first chips 20 are fixed to the substrate 10 in a positive mounting manner and are electrically connected to the substrate 10 to form a bottom chip array. The heat dissipation cover 50 covers the outside of all the first chips 20, serving as both a protective shell and a heat dissipation function. Specifically, the heat dissipation cover 50 has connection holes 51 and receiving grooves 52. The positions of the connection holes 51 correspond one-to-one with the first chips 20 to provide a channel for the electrical connection of the first chips 20 with other components. The receiving grooves 52 are located in the cavity between at least two first chips 20. The bottom of the receiving grooves 52 also has through holes 521 as a path for the second chip 30 to be electrically connected to the substrate 10.

[0024] The second chip 30 is mounted in the receiving groove 52 in a flip-chip manner and is electrically connected to the substrate 10 through the through hole 521 at the bottom of the groove. The third chip 40 is mounted in a forward-facing manner on the side wall of the receiving groove 52 (the side wall of the receiving groove 52 is part of the heat sink 50). The third chip 40 is electrically connected to the corresponding first chip 20 through the connection hole 51 on the heat sink 50, forming a signal path between the first chip 20 and the third chip 40. On this basis, the receiving groove 52 is filled with a heat-dissipating adhesive layer 60, and the top surface of the heat-dissipating adhesive layer 60 is at least flush with the top of the receiving groove 52 (that is, the heat-dissipating adhesive layer 60 can fill the receiving groove 52 completely or slightly higher than the opening of the receiving groove 52). At the same time, the bottom surface of the third chip 40 is in direct contact with the heat-dissipating adhesive layer 60, achieving physical bonding between the two and forming a complete heat conduction path.

[0025] The chip stacking heat dissipation structure 100 provided in this application directly covers the first chip 20 through the heat dissipation cover 50, which can quickly absorb the heat of the first chip 20 and diffuse it outward. The heat dissipation adhesive layer 60 fills the receiving groove 52 and contacts the bottom surface of the third chip 40, which can conduct the heat of the second chip 30 to the third chip 40 through the heat dissipation adhesive layer 60, and then from the third chip 40 to the side wall of the heat dissipation cover 50. At the same time, the heat of the second chip 30 can also be directly conducted to the side wall of the receiving groove 52 (i.e., the heat dissipation cover 50) through the heat dissipation adhesive layer 60, forming a multi-dimensional heat dissipation path of "third chip 40, heat dissipation adhesive layer 60 and heat dissipation cover 50", which greatly improves the heat dissipation efficiency of stacked chips, controls the temperature of each chip within a safe range, and reduces the risk of chip performance degradation or thermal failure caused by high temperature.

[0026] After the thermal adhesive layer 60 fills the receiving groove 52, it can wrap and fix the second chip 30. At the same time, through the contact between the thermal adhesive layer 60 and the bottom surface of the third chip 40, the displacement of the third chip 40 can be restricted. In conjunction with the covering effect of the heat sink 50, the loosening of the chip caused by vibration or thermal expansion and contraction is reduced, thereby reducing the risk of electrical connection failure. In addition, the thermal adhesive layer 60 has a certain degree of elasticity, which can buffer the thermal expansion and contraction stress of the chip caused by temperature changes, reduce the warping deformation of the stacked structure caused by uneven stress, and ensure the stability of the electrical connection between the chips.

[0027] The receiving slot 52 is located in the cavity between at least two first chips 20, making full use of the idle space between at least two first chips 20. The second chip 30 is placed in the receiving slot 52, and the third chip 40 is integrated on the side wall of the receiving slot 52. The second chip 30 and the third chip 40 are integrated through three-dimensional stacking, replacing the traditional planar arrangement. This achieves multi-chip integration in a limited space, saving the area of ​​the substrate 10. The heat dissipation cover 50 and the heat dissipation adhesive layer 60 design solve the heat dissipation problem caused by stacking, taking into account both miniaturization and heat dissipation requirements.

[0028] The connection hole 51 corresponds one-to-one with the position of the first chip 20, and the through hole 521 provides a dedicated connection path for the second chip 30, ensuring that the electrical connection of each chip is accurate and independent and avoiding signal interference. At the same time, the heat dissipation adhesive layer 60 does not affect the electrical connection of the pins or solder joints of the second chip 30 and the third chip 40. It enhances stability only through physical fixation and heat conduction, taking into account both electrical performance and heat dissipation performance, thereby improving the reliability of the entire electronic device.

[0029] As one possible implementation method, such as Figure 1 and Figure 2 As shown, there is a first gap between the sidewall of the second chip 30 and the sidewall of the receiving groove 52, and the first gap is filled with a heat-dissipating adhesive layer 60.

[0030] It should be noted that when the second chip 30 is flip-mounted in the receiving groove 52, a first gap is reserved between the sidewall of the second chip 30 and the sidewall of the receiving groove 52 to maintain a certain distance between them, providing filling space for the thermal adhesive layer 60. The first gap is filled with the thermal adhesive layer 60, and this thermal adhesive layer 60 and the thermal adhesive layer 60 in the receiving groove 52 (i.e., the thermal adhesive layer 60 whose top surface is at least flush with the top of the receiving groove 52 and in contact with the bottom surface of the third chip 40) are a continuous integral structure. This means that the thermal adhesive layer 60 not only fills the space between the second chip 30 and the third chip 40, but also wraps the sidewall of the second chip 30, forming an all-round thermal conductive coverage for the second chip 30.

[0031] By filling the space between the sidewall of the second chip 30 and the sidewall of the receiving groove 52 with a thermal adhesive layer 60, a new direct heat conduction path is added from the sidewall of the second chip 30 to the sidewall of the receiving groove 52 (i.e., the heat sink 50). Compared to heat dissipation only through the bottom or top of the second chip 30, the above design can more efficiently conduct heat out of the second chip 30, reduce the temperature of the second chip 30, and improve the operating stability of the second chip 30.

[0032] The elastic properties of the thermal adhesive layer 60 can buffer the stress generated by the thermal expansion and contraction of the second chip 30 during operation, reduce the hard collision between the second chip 30 and the side wall of the receiving groove 52, and prevent the edge of the second chip 30 from being damaged by mechanical stress. At the same time, the filling of the thermal adhesive layer 60 makes the second chip 30 more firmly fixed in the receiving groove 52, reduces the risk of displacement caused by vibration, and ensures the reliability of the electrical connection between the second chip 30 and the substrate 10.

[0033] The heat dissipation adhesive layer 60 in the first gap is integrated with the heat dissipation adhesive layer 60 in other areas of the receiving groove 52 to form a unified heat conduction medium. This allows the heat of the second chip 30 to be conducted to the heat dissipation cover 50 simultaneously through three directions: the bottom (direction of the through hole 521), the top (contact surface with the third chip 40), and the side wall (first gap). This significantly improves heat dissipation efficiency and reduces the overall thermal resistance of the chip stacking structure.

[0034] By reserving a first gap and filling it with a thermal adhesive layer 60, minor dimensional deviations between the second chip 30 and the receiving groove 52 during manufacturing can be compensated. Even if there are processing errors in the second chip 30 or the receiving groove 52, the fluidity and filling properties of the thermal adhesive layer 60 can still ensure good thermal contact, avoid poor heat dissipation problems caused by dimensional mismatch, and improve production yield.

[0035] As one possible implementation method, such as Figure 1 and Figure 2 As shown, there is a second gap between the bottom surface of the second chip 30 and the bottom of the receiving groove 52, and the second gap is filled with a heat-dissipating adhesive layer 60.

[0036] It should be noted that when the second chip 30 is flip-mounted in the receiving slot 52, a second gap is reserved between the bottom surface of the second chip 30 and the bottom of the receiving slot 52, so that a certain distance is maintained between the bottom surface of the second chip 30 and the bottom of the receiving slot 52, providing filling space for the thermal adhesive layer 60. The second gap is filled with the thermal adhesive layer 60, and this thermal adhesive layer 60 and the thermal adhesive layer 60 of the receiving slot 52 (including the thermal adhesive layer 60 in the first gap, and the thermal adhesive layer 60 whose top surface is at least flush with the top of the receiving slot 52 and in contact with the bottom surface of the third chip 40) are a continuous integral structure. This means that the thermal adhesive layer 60 not only fills the space between the second chip 30 and the third chip 40, but also wraps the sidewall of the second chip 30, and fills the space between the bottom surface of the chip and the bottom of the receiving slot 52, forming an all-round heat conduction coverage for the second chip 30.

[0037] By filling the space between the bottom surface of the second chip 30 and the bottom of the receiving slot 52 with a thermal adhesive layer 60, a new direct heat conduction path is created from the bottom of the second chip 30 to the bottom of the receiving slot 52 (i.e., the heat sink 50). The heat generated by the second chip 30 can be quickly transferred to the bottom of the receiving slot 52 through the thermal adhesive layer 60, and then dissipated through the heat sink 50, effectively reducing the temperature of the second chip 30 and improving its operational stability.

[0038] After the thermal adhesive layer 60 fills the second gap, it can provide additional support for the second chip 30, reducing the risk of displacement of the second chip 30 due to vibration or external impact. At the same time, the elastic properties of the thermal adhesive layer 60 can buffer the stress generated by thermal expansion and contraction of the second chip 30 during operation, avoid damage caused by hard contact between the second chip 30 and the bottom of the receiving groove 52, and extend the service life of the second chip 30.

[0039] The heat dissipation adhesive layer 60 in the second gap is integrated with the heat dissipation adhesive layer 60 in other areas of the first gap and the receiving groove 52 to form a complete heat conduction network surrounding the second chip 30. This allows the heat from all parts of the second chip 30 to be evenly conducted to the heat dissipation cover 50, avoiding the generation of local hot spots and further improving the overall heat dissipation efficiency.

[0040] The second gap, filled with a thermal adhesive layer 60, compensates for dimensional deviations in the depth of the second chip 30 and the receiving groove 52 during manufacturing. Even if there are processing errors in the thickness of the second chip 30 or the depth of the receiving groove 52, the fluidity and filling properties of the thermal adhesive layer 60 can still ensure good thermal contact, avoid poor heat dissipation problems caused by dimensional mismatch, and improve production yield.

[0041] As one possible implementation method, such as Figure 1 and Figure 2 As shown, along the line connecting the third chip 40 to the substrate 10, the distance between the bottom of the heat sink 50 and the top surface of the substrate 10 is less than or equal to the distance between the bottom surface of the first chip 20 and the top surface of the substrate 10.

[0042] It should be noted that, along the line connecting the third chip 40 to the substrate 10 (i.e., the vertical direction perpendicular to the substrate 10), the distance between the bottom of the heat sink 50 and the top surface of the substrate 10 is less than or equal to the distance between the bottom surface of the first chip 20 and the top surface of the substrate 10. Here, the bottom of the heat sink 50 refers to the edge of the heat sink 50 facing the substrate 10 (the part close to the substrate 10). This means that the sidewall of the heat sink 50 can at least cover the sidewall of the first chip 20, forming a full-range heat conduction coverage for the first chip 20, thereby ensuring that the heat of the first chip 20 can be dissipated through the heat sink 50, reducing the temperature of the first chip 20 and improving its working stability.

[0043] As one possible implementation method, such as Figure 1 and Figure 2 As shown, a fixing adhesive layer 70 is provided between the bottom of the heat sink 50 and the bottom surface of the first chip 20 and the top surface of the substrate 10.

[0044] It should be noted that a fixing adhesive layer 70 is provided between the bottom of the heat sink 50 and the top surface of the substrate 10, and between the bottom surface of the first chip 20 and the top surface of the substrate 10. Specifically, the fixing adhesive layer 70 for the first chip 20 is located on the mating surface of the first chip 20 (i.e., between the bottom surface of the first chip 20 and the top surface of the substrate 10), and is used to fix the first chip 20 to the substrate 10; the fixing adhesive layer 70 for the heat sink 50 is located between the bottom of the heat sink 50 (near the edge of the substrate 10) and the top surface of the substrate 10, and is used to connect and fix the heat sink 50 to the substrate 10.

[0045] If the fixing adhesive layer 70 is made of thermally conductive adhesive (which has both fixing and thermal conductivity properties), it can also serve as a heat dissipation medium. The heat of the first chip 20 is conducted to the substrate 10 through its bottom fixing adhesive layer 70, and the heat of the heat dissipation cover 50 is transferred to the substrate 10 through its bottom fixing adhesive layer 70, so as to assist in heat dissipation through the substrate 10, forming a supplementary heat dissipation path of "first chip 20, fixing adhesive layer 70 and substrate 10", which further improves the overall heat dissipation efficiency of the stacked structure.

[0046] As one possible implementation method, such as Figure 2 As shown, the chip stack heat dissipation structure 100 also includes a fourth chip 80, which is flip-mounted on the first chip 20 and electrically connected to the first chip 20. The fourth chip 80 is located below the third chip 40 and is arranged adjacent to the second chip 30.

[0047] It should be noted that the chip stack heat dissipation structure 100 also includes a fourth chip 80. The fourth chip 80 is flip-chip fixed to the top surface of the first chip 20 and electrically connected to the first chip 20, forming a vertical stacking structure of "first chip 20 and fourth chip 80". Along the vertical direction perpendicular to the substrate 10, the fourth chip 80 is located below the third chip 40 and is arranged adjacent to the second chip 30 in the horizontal direction (i.e., they are side by side in the same plane or approximately the same plane). It should be noted that both the fourth chip 80 and the second chip 30 are located in the unused area between the first chip 20, but are fixed to different carriers by flip-chip. The fourth chip 80 is flip-chip mounted on the first chip 20, and the second chip 30 is flip-chip mounted in the receiving groove 52 and connected to the substrate 10 through the through hole 521.

[0048] By stacking a fourth chip 80 on the first chip 20, more functional modules (such as combining processors with cache chips, control chips with sensor chips, etc.) are integrated without increasing the area occupied by the substrate 10, meeting the high-performance and multi-functional requirements of electronic devices while maintaining a compact structure. The fourth chip 80 is directly flip-chip connected to the first chip 20, shortening the signal transmission path between them. Compared with the traditional connection method through the substrate 10, it can reduce signal delay and loss, and improve data transmission speed, which is especially suitable for high-frequency and high-speed signal processing scenarios (such as the connection between the processor and the cache).

[0049] The fourth chip 80 is flip-mounted onto the first chip 20, forming a rigid integral with it, which improves the mechanical strength of the stacked structure. Simultaneously, the fourth chip 80 is located below the third chip 40 and adjacent to the second chip 30, allowing it to dissipate its heat to the heat sink 50. Furthermore, the heat from the fourth chip 80 can be conducted to the substrate 10 through the first chip 20, utilizing the substrate 10 for auxiliary heat dissipation, preventing excessive heat accumulation in the chip stacking area and reducing local temperature peaks. In summary, the addition of the fourth chip 80, through vertical stacking and a rational layout, improves functional density while simultaneously addressing signal transmission efficiency and heat dissipation requirements, further optimizing the overall performance of the chip stacking heat dissipation structure 100.

[0050] As one possible implementation method, such as Figure 2 As shown, along the line connecting the third chip 40 to the substrate 10, the orthographic projection of the fourth chip 80 on the substrate 10 and the orthographic projection of the first chip 20 on the substrate 10 have overlapping and non-overlapping areas. The bottom surface of the fourth chip 80 is provided with at least two bumps 81. The bumps 81 located in the overlapping area are electrically connected to the first chip 20, and the bumps 81 located in the non-overlapping area are electrically connected to the substrate 10.

[0051] It should be noted that along the line connecting the third chip 40 to the substrate 10 (i.e., the vertical direction perpendicular to the substrate 10), the orthographic projection of the fourth chip 80 on the substrate 10 partially overlaps with the orthographic projection of the first chip 20 on the substrate 10. The overlapping area refers to the part where the orthographic projections of the fourth chip 80 and the first chip 20 overlap in the vertical direction, while the non-overlapping area refers to the part of the fourth chip 80 that extends beyond the orthographic projection range of the first chip 20. The bottom surface of the fourth chip 80 is provided with at least two bumps 81. These bumps 81 are divided into two categories: the first category, the bumps 81 located in the overlapping area, are directly connected to the corresponding solder joints on the top surface of the first chip 20 (e.g., through soldering or metal bonding), enabling electrical signal communication between the fourth chip 80 and the first chip 20; the second category, the bumps 81 located in the non-overlapping area, are connected to the corresponding solder joints on the top surface of the substrate 10 through an extension structure (e.g., a metal pillar or a wire), allowing the fourth chip 80 to directly communicate with the circuits on the substrate 10.

[0052] By distributing the bumps 81 in overlapping and non-overlapping areas, the fourth chip 80 can communicate directly with the first chip 20 (high-speed signal transmission) and connect with other circuit modules on the substrate 10 (such as power supply and control signals). This breaks through the limitation of traditional stacked chips relying solely on the underlying chip for signal relay, forming parallel communication paths between "the fourth chip 80 and the first chip 20" and "the fourth chip 80 and the substrate 10", thus improving the flexibility and efficiency of signal transmission.

[0053] The overlapping design of the orthographic projection portion allows the fourth chip 80 to partially overlap with the first chip 20 in the vertical direction, reducing the area occupied in the horizontal direction and further improving the chip stacking density. At the same time, the bumps 81 in the non-overlapping area are directly connected to the substrate 10, avoiding the need for long-distance signal transmission through the first chip 20, reducing signal delay, and is especially suitable for scenarios where multiple chips work together (such as direct communication between the processor and the I / O module).

[0054] The fourth chip 80 is doubly connected to the first chip 20 and the substrate 10 through bumps 81. The heat generated by it can be dissipated through two paths at the same time: it is conducted to the first chip 20 through the bumps 81 in the overlapping area (and then dissipated through the heat sink 50 or the substrate 10), and it is directly conducted to the substrate 10 through the bumps 81 in the non-overlapping area, forming a dual-channel heat dissipation, reducing the temperature of the fourth chip 80 and improving its operational reliability.

[0055] The bumps 81 in the non-overlapping area allow the fourth chip 80 to communicate directly with specific circuit modules (such as power management units and external interfaces) on the substrate 10 without relying on the first chip 20 as a relay, avoiding interference or load problems caused by signal sharing, and supporting more complex circuit function integration (such as heterogeneous chip integration).

[0056] As one possible implementation method, such as Figure 1 and Figure 2 As shown, the first chip 20 is electrically connected to the substrate 10 via a first bonding wire 21, forming a current or signal transmission path between the first chip 20 and the substrate 10. The third chip 40 is electrically connected to the first chip 20 via a second bonding wire 41, forming a current or signal transmission path between the third chip 40 and the first chip 20. Both the first bonding wire 21 and the second bonding wire 41 pass through the connection hole 51. The connection hole 51 provides a passage for the bonding wires, enabling the bonding wires to achieve electrical connections between the first chip 20 and the substrate 10, and between the third chip 40 and the first chip 20, without interfering with the structure of the heat sink 50. The first bonding wire 21 and the second bonding wire 41 share the connection hole 51 (or have separate channels within the same connection hole 51), which reduces the number of openings on the heat sink 50, maintains the structural integrity of the heat sink 50, and avoids the possibility that excessive openings may reduce the rigidity and heat dissipation efficiency of the heat sink 50.

[0057] As one possible implementation method, such as Figure 1 and Figure 2 As shown, the chip stack heat dissipation structure 100 also includes a molding compound 90, which is disposed on the substrate 10 and covers the third chip 40 and the heat sink 50. Thus, the molding compound 90 provides physical protection for the chip and the heat sink 50, preventing them from being affected by factors such as dust, moisture, and mechanical impact in the external environment.

[0058] A second aspect of this application also provides an electronic device including the aforementioned chip stack heat dissipation structure 100. Since the structure and beneficial effects of the chip stack heat dissipation structure 100 have been described in detail in the foregoing embodiments, they will not be repeated here.

[0059] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0060] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A chip stacking heat dissipation structure, characterized in that, The device includes a substrate, at least two first chips, a second chip, a third chip, and a heat sink. The at least two first chips are mounted upright on the substrate and electrically connected to it. The heat sink covers the at least two first chips and has connection holes and receiving slots. The connection holes correspond to the positions of the first chips. The receiving slots are located between the at least two first chips and have through holes at the bottom. The second chip is flipped in the receiving slot and electrically connected to the substrate through the through holes. The third chip is mounted upright on the side wall of the receiving slot and electrically connected to the first chips through the connection holes. A thermal adhesive layer is disposed in the receiving slot, and the top surface of the thermal adhesive layer is at least flush with the top of the receiving slot. The bottom surface of the third chip is in contact with the thermal adhesive layer.

2. The chip stacking heat dissipation structure according to claim 1, characterized in that, There is a first gap between the sidewall of the second chip and the sidewall of the receiving groove, and the first gap is filled with the heat-dissipating adhesive layer.

3. The chip stacking heat dissipation structure according to claim 2, characterized in that, There is a second gap between the bottom surface of the second chip and the bottom of the receiving groove, and the second gap is filled with the heat dissipation adhesive layer.

4. The chip stacking heat dissipation structure according to claim 1, characterized in that, Along the line connecting the third chip to the substrate, the distance between the bottom of the heat sink and the top surface of the substrate is less than or equal to the distance between the bottom surface of the first chip and the top surface of the substrate.

5. The chip stacking heat dissipation structure according to claim 4, characterized in that, A fixing adhesive layer is provided between the bottom of the heat sink cover and the bottom surface of the first chip and the top surface of the substrate.

6. The chip stacking heat dissipation structure according to claim 1, characterized in that, It also includes a fourth chip, which is flip-chip mounted on the first chip and electrically connected to the first chip. The fourth chip is located below the third chip and is arranged adjacent to the second chip.

7. The chip stacking heat dissipation structure according to claim 6, characterized in that, Along the line connecting the third chip to the substrate, the orthographic projection of the fourth chip on the substrate and the orthographic projection of the first chip on the substrate have overlapping and non-overlapping areas. The bottom surface of the fourth chip is provided with at least two bumps. The bumps located in the overlapping area are electrically connected to the first chip, and the bumps located in the non-overlapping area are electrically connected to the substrate.

8. The chip stacking heat dissipation structure according to claim 1, characterized in that, The first chip is electrically connected to the substrate via a first wire bonding, and the third chip is electrically connected to the first chip via a second wire bonding. Both the first wire bonding and the second wire bonding are passed through the connection hole.

9. The chip stacking heat dissipation structure according to claim 1, characterized in that, It also includes a molding compound, which is disposed on the substrate and covers the third chip and the heat sink.

10. An electronic device, characterized in that, Includes the chip stacking heat dissipation structure as described in any one of claims 1 to 9.

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