Semiconductor device and electric appliance

Abstract

This application discloses a semiconductor device and an electrical device. The semiconductor device includes: a substrate; a power factor corrector and a rectifier bridge; a drive-side frame, which includes a PFC pin frame and a rectifier pin frame, the PFC pin frame including a plurality of PFC drive-side pins; a PFC driver integrated circuit disposed on the PFC pin frame; and a molding compound for encapsulating the substrate, the drive-side frame, the PFC driver integrated circuit, the power factor corrector, and the rectifier bridge. A first groove is provided in the molding compound between the PFC pin frame and the rectifier pin frame. The first groove is recessed into the molding compound from the outer peripheral side along a second direction, and extends within the molding compound to penetrate two surfaces respectively connected to the outer peripheral side.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and electrical equipment. Background Technology

[0002] The control boards of electrical appliances such as air conditioners may include independently packaged components such as rectifier bridges, power factor correction (PFC) devices, compressor IPMs, and fan IPMs. These components are discrete devices, typically with multiple pins, some of which have poor isolation performance. Therefore, how to achieve relatively stable electrical isolation performance between the pins of semiconductor devices has become an urgent problem to be solved. Utility Model Content

[0003] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To at least partially solve the above-mentioned problems, according to a first aspect of this application, a semiconductor device is provided. The semiconductor device has a first direction, a second direction, and a third direction, which are perpendicular to each other. The semiconductor device includes: a substrate; a power factor corrector (PFC) and a rectifier bridge, disposed adjacent to each other on the substrate and spaced apart in the first direction; and a drive-side frame disposed outside the substrate and spaced apart from at least a portion of the substrate in the second direction. The drive-side frame includes a PFC pin frame and a rectifier pin frame spaced apart in the first direction. The device includes multiple PFC driver-side pins, a rectifier pin frame electrically connected to a rectifier bridge, a PFC driver integrated circuit disposed on the PFC pin frame and electrically connected to a power factor corrector, and a molding compound for encapsulating the substrate, driver-side frame, PFC driver integrated circuit, power factor corrector, and rectifier bridge. The multiple PFC driver-side pins extend at least partially from the outer peripheral side of the molding compound. A first groove is provided in the molding compound between the PFC pin frame and the rectifier pin frame. The first groove is recessed into the molding compound from the outer peripheral side along a second direction and penetrates the molding compound in a third direction.

[0005] The above technical solution has the following advantages or beneficial effects: In order to ensure electrical isolation between different pins, by setting a groove in the plastic package between the PFC pin frame and the rectifier pin frame, the surface current path between adjacent pins can be lengthened, the creepage distance and clearance performance between adjacent pins can be improved, thereby improving the electrical isolation performance between pins and improving the operational stability of the integrated semiconductor device.

[0006] For example, the rectifier pin frame includes two rectifier bridge drive-side pins, at least a portion of which extends from the molding compound, wherein a second groove is provided in the molding compound between the two rectifier bridge drive-side pins, the second groove being recessed into the molding compound from the outer peripheral side along the second direction, and the second groove penetrating the molding compound in the third direction.

[0007] The above technical solution has the following advantages or beneficial effects: By setting a second groove in the plastic package between the two rectifier bridge drive side pins, the surface current path between adjacent pins can be lengthened, the creepage distance and clearance performance between adjacent pins can be improved, thereby improving the electrical isolation performance between pins and improving the operational stability of the integrated semiconductor device.

[0008] Exemplarily, it further includes: a first inverter circuit element and a second inverter circuit element disposed on the substrate. The first inverter circuit element, the second inverter circuit element, the power factor corrector, and the rectifier bridge are spaced apart from each other in a first direction. The rectifier bridge includes a rectifier chip and a rectifier bridge pad. The substrate has a first power side pad, a second power side pad, a PFC power side pad, and the rectifier bridge pad. The first inverter circuit element, the second inverter circuit element, the power factor corrector, and the rectifier chip are respectively disposed on the first power side pad, the second power side pad, the PFC power side pad, and the rectifier bridge pad. The drive-side frame further includes a first frame and a second frame. The first frame, the second frame, the PFC pin frame, and the rectifier pin frame are disposed in a first direction. The components are spaced apart from each other. The first frame and the first power-side pad are at least partially corresponding in a second direction. The second frame and the second power-side pad are at least partially corresponding in a second direction. The PFC pin frame and the PFC power-side pad are at least partially corresponding in a second direction. The rectifier pin frame and the PFC power-side pad are at least partially corresponding in a second direction. The first frame includes a first driver-side pad and a plurality of first driver-side pins. The second frame includes a second driver-side pad and a plurality of second driver-side pins. The plurality of first driver-side pins and the plurality of second driver-side pins extend at least partially from the molding compound. The portions of the plurality of first driver-side pins located outside the molding compound and the portions of the plurality of second driver-side pins located outside the molding compound have the same arrangement in the first direction.

[0009] The above technical solution has the following advantages or beneficial effects: the first inverter circuit element (e.g., fan inverter circuit element), the second inverter circuit element (e.g., compressor inverter circuit element), the PFC and the rectifier bridge are arranged at intervals on the substrate, which reduces crosstalk and electromagnetic interference. For example, the high-frequency switching noise of the compressor inverter is not easily coupled to the PFC control signal line, avoiding heat concentration and improving the heat dissipation capacity and reliability of the device.

[0010] For example, multiple first driving side pins and multiple second driving side pins each have a low-voltage pin area and a high-voltage pin area spaced apart in a first direction. Each of the multiple first driving side pins and multiple second driving side pins includes multiple connection pins and at least one pseudo-pin. The at least one pseudo-pin includes a first pseudo-ground pin, which is located in the low-voltage pin area. The first pseudo-ground pin divides the multiple connection pins within each low-voltage pin area into: a first connection pin group and a second connection pin group located on either side of the first pseudo-ground pin. The spacing between any two adjacent connection pins in the first connection pin group is 'a'; and / or the spacing between any two adjacent connection pins in the second connection pin group is 'a'; and / or the minimum spacing between any two adjacent PFC driving side pins among the multiple PFC driving side pins is 'a'; and / or the spacing between two connection pins located on either side of the first pseudo-ground pin and adjacent to the first pseudo-ground pin is greater than or equal to 2a.

[0011] The above technical solution has the following advantages or beneficial effects: The above pin spacing design can make the pin distribution of the two inverters more reasonable, the overall stress more uniform, and the structural strength higher. It can also make the pin distribution of the PFC more reasonable, the overall stress more uniform, and the structural strength higher. The pseudo-pins can increase the insulation distance between two adjacent connection pins and reduce the interference between the two pins.

[0012] For example, at least one bootstrap chip, the plurality of connection pins of the plurality of first driving side pins and the plurality of connection pins of the plurality of second driving side pins further include: a plurality of bootstrap pins, each bootstrap pin having a connection pin located outside the plastic package, the connection pins of the plurality of bootstrap pins being located within a high-voltage pin area, the plurality of bootstrap pins including at least one set of bootstrap pins, each set of bootstrap pins being electrically connected to its corresponding bootstrap chip, wherein the spacing between two adjacent connection pins in each set of bootstrap pins in a first direction is defined as 'a', the minimum spacing between the connection pins of adjacent sets of bootstrap pins in the first direction is greater than or equal to 3a; and / or in the plurality of first driving side pins and the plurality of second driving side pins, the spacing between the connection pins of their respective low-voltage pin areas located outside the plastic package and the connection pins of their adjacent high-voltage pin areas located outside the plastic package in the first direction is greater than or equal to 3a.

[0013] The above technical solution has the following advantages or beneficial effects: the above pin spacing design can make the pin distribution of the two inverter sections more reasonable, the overall stress more uniform, and the structural strength higher.

[0014] Exemplarily, it further includes: a third groove provided in the molding compound between the connection pins in the low-voltage pin area and the connection pins in the high-voltage pin area, the third groove being recessed into the molding compound from the outer peripheral side along the second direction, and the third groove penetrating the molding compound in the third direction; and / or at least one fourth groove provided on the side of the molding compound near the drive-side frame, the fourth groove being located between the bootstrap pins of adjacent groups, the fourth groove being recessed into the molding compound from the outer peripheral side along the second direction, and the fourth groove penetrating the molding compound in the third direction; and / or at least one fifth groove provided on the side of the molding compound near the drive-side frame, the fifth groove being located between the bootstrap pins of adjacent groups. Between one of the plurality of first drive-side pins and one of the plurality of second drive-side pins, a fifth groove is recessed into the molding compound from the outer peripheral side along a second direction, and the fifth groove penetrates the molding compound in a third direction; and / or, a sixth groove is further provided on the side of the molding compound near the drive-side frame, the plurality of second drive-side pins include a plurality of second connection pins, the PFC drive-side pins include a plurality of third connection pins, the sixth groove is disposed between adjacent third connection pins and second connection pins, the sixth groove is recessed into the molding compound from the outer peripheral side along a second direction, and the sixth groove penetrates the molding compound in a third direction.

[0015] The above technical solution has the following advantages or beneficial effects: by setting grooves between the connection pins in the weak current pin area and the connection pins in the strong current pin area, between the bootstrap pins, and between one of the connection pins in the first driving side pin and one of the connection pins in the second driving side pin, the surface current path between adjacent bootstrap pins can be lengthened, the creepage distance and electrical clearance performance between adjacent pins can be improved, thereby improving the electrical isolation performance between pins and improving the operational stability of the integrated semiconductor device.

[0016] For example, in the first direction, one of the first drive-side pins is adjacent to one of the second drive-side pins, and the distance between them is greater than or equal to 5a; and / or in the first direction, the second frame and the PFC pin frame are adjacent, and the portion of one of the second drive-side pins and one of the PFC drive-side pins in the PFC pin frame located outside the plastic package is adjacent, and the distance between them is greater than or equal to 5a; and / or the distance between two adjacent rectifier bridge drive-side pins is less than or equal to 5a.

[0017] The above technical solution has the following advantages or beneficial effects: The above pin spacing design can make a reasonable interval between the two inverters and between the second inverter and the PFC, ensuring electrical clearance while making the overall force more uniform and ensuring the overall structural strength.

[0018] For example, the first connection pin group includes the following pins arranged sequentially and at intervals in the first direction: over-temperature protection pin, power ground pin, over-current protection pin, fault output port pin, low-side gate drive supply voltage pin, W2 phase low-side input signal pin, V2 phase low-side input signal pin, and U2 phase low-side input signal pin; the second connection pin group includes the following pins arranged sequentially and at intervals in the first direction: high-side gate drive supply voltage pin, W2 phase high-side input signal pin, V2 phase high-side input signal pin, and U2 phase high-side input signal pin.

[0019] The above technical solution has the following advantages or beneficial effects: reasonable pin arrangement can reduce cross interference between signals, ensure the stability of drive signals, help simplify circuit design, and improve system reliability.

[0020] For example, the first inverter circuit element is a fan inverter circuit element, and the second inverter circuit element is a compressor inverter circuit element. The multiple connection pins located in the low-voltage pin area of ​​the multiple first drive-side pins include those arranged sequentially and at intervals in the first direction: fan over-temperature protection pin, fan power ground pin, fan overcurrent protection pin, fan fault output port pin, fan low-side gate drive power supply voltage pin, fan W2 phase low-side input signal pin, fan V2 phase low-side input signal pin, fan U2 phase low-side input signal pin, fan high-side gate drive power supply voltage pin, fan W2 phase high-side input signal pin, and fan V2 phase... The high-side input signal pin and the high-side input signal pin of the U2 phase of the fan; multiple connection pins located in the high-voltage pin area of ​​multiple first drive-side pins include the following arranged sequentially and at intervals in the first direction: high-side drive floating power supply voltage pin of the W2 phase of the fan, high-side drive floating power supply ground pin of the W2 phase of the fan, high-side drive floating power supply voltage pin of the V2 phase of the fan, high-side drive floating power supply ground pin of the V2 phase of the fan, high-side drive floating power supply voltage pin of the U2 phase of the fan, and high-side drive floating power supply ground pin of the U2 phase of the fan; multiple connection pins located in the low-voltage pin area of ​​multiple second drive-side pins include the following arranged sequentially and at intervals in the first direction: compression The compressor over-temperature protection pin, compressor power ground pin, compressor overcurrent protection pin, compressor fault output port pin, compressor low-side gate drive power supply voltage pin, compressor W1 phase low-side input signal pin, compressor V1 phase low-side input signal pin, compressor U1 phase low-side input signal pin, compressor high-side gate drive power supply voltage pin, compressor W1 phase high-side input signal pin, compressor V1 phase high-side input signal pin, and compressor U1 phase high-side input signal pin; multiple connection pins located in the high-voltage pin area of ​​multiple second drive side pins include those arranged sequentially and at intervals in the first direction: compressor W1 phase high-side drive... The multiple connection pins among the multiple PFC drive-side pins include the following: PFC drive IC power supply voltage pin, PFC power ground pin, I / O function enable pin, PFC input signal pin, current detection input pin, temperature sensor connector 2 pin, and temperature sensor connector 1 pin, arranged sequentially and at intervals in the first direction.

[0021] The above technical solution has the following advantages or beneficial effects: By dividing the drive side into blocks and setting the first drive side pin and the second drive side pin, wiring is facilitated and signal crosstalk between the first drive side pin and the second drive side pin is reduced. On this basis, a weak current pin area and a strong current pin area are set up. The weak current pin area (such as sensor feedback, PWM control signals, and communication interfaces) usually transmits low-amplitude, high-sensitivity signals (such as 0-5V or digital signals). If it is mixed with the strong current pins (such as rectifier bridge output and PFC bus voltage), the high-frequency switching noise or large current transients of the strong current pins will interfere with the weak current signals through crosstalk or ground bounce, resulting in control logic errors or sensor reading distortion. At the same time, the physical isolation between the weak current pin area and the strong current pin area can block the conduction path of high-frequency noise (such as common-mode current loop) and reduce radiated noise coupling.

[0022] This application also provides an electrical device that includes the aforementioned semiconductor device.

[0023] The above technical solution has the following advantages and beneficial effects: Since the electrical device includes the aforementioned semiconductor device, it has the same advantages as the aforementioned semiconductor device. Attached Figure Description

[0024] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0025] In the attached image: Figure 1 A top view of the semiconductor device in the Z direction is shown in an embodiment of this application.

[0026] Figure 2 A top view of the semiconductor device with device designations in the Z direction is shown in the embodiment of this application.

[0027] Figure 3 A top view schematic diagram of the first inverter section in the semiconductor device according to an embodiment of this application is shown.

[0028] Figure 4 A top view schematic diagram of the second inverter section in the semiconductor device according to an embodiment of this application is shown.

[0029] Figure 5 A top view of the semiconductor device in another direction in the Z direction is shown in the embodiment of this application.

[0030] Figure 6 The pin numbers of the semiconductor device driver side in the embodiments of this application are shown.

[0031] Figure 7A side view of a semiconductor device in the X direction is shown in an embodiment of this application.

[0032] Figure 8a , Figure 8b , Figure 8c Schematic diagrams are shown of the alternation of long and short pins in some embodiments of the semiconductor device in this application.

[0033] Figure 9 A schematic diagram showing the pin numbers and pseudo-pin numbers of the semiconductor device on the driving side in an embodiment of this application is shown.

[0034] Figure 10 A schematic diagram of a semiconductor device having a groove formed on one side of a plastic package in an embodiment of this application is shown.

[0035] Figure 11 The diagram shows a relative layout design of the modules in some other embodiments of the semiconductor device in this application.

[0036] Figure 12 The diagram shows a relative layout design of the modules in some other embodiments of the semiconductor device in this application.

[0037] Figure 13 The diagram shows a schematic of some embodiments of the semiconductor device in this application, which integrate only the first inverter section and the second inverter section.

[0038] Figure label: 100. Semiconductor devices; 101. First inverter unit; 102. First driver integrated circuit; 103. First inverter circuit element; 1021. First low-voltage drive integrated circuit; 1022. First high-voltage drive integrated circuit; 1031. First low-voltage inverter circuit element; 1032. First high-voltage inverter circuit element; 201. Second inverter unit; 202. Second driver integrated circuit; 203. Second inverter circuit element; 2021, Second low-voltage driver integrated circuit; 2022, Second high-voltage driver integrated circuit; 2031. Second low-voltage power-side inverter circuit element; 2032. Second high-voltage power-side inverter circuit element; 302. PFC driver integrated circuit; 303. Power factor corrector; 401, Rectifier bridge; 402, Rectifier bridge pads; 403, Rectifier chip; 500, substrate; 501, first power side pad; 502, second power side pad; 5011, First low-voltage power side pad; 5012, First high-voltage power side pad; 5021, Second low-voltage power side pad; 5022, Second high-voltage power side pad; 503, PFC power side pad; 600, Drive-side frame; 601, First drive-side pad; 602, First driver side pin; 603, Second driver side pad; 604, Second driver side pin; 605, PFC driver side pin; 606, Rectifier bridge driver side pin; 6011, First low-voltage drive side pad; 6012, First high-voltage drive side pad; 6031, Second low-voltage drive side pad; 6032, Second high-voltage drive side pad; 609, PFC driver side pad; 60a, first side; 60b, second side; 700, Molded body; 701, First side; 702, Second side; 7031, First groove; 7032, Second groove; 7033, Third groove; 7034, Fourth groove; 7035, Fifth groove; 7036, Sixth groove; P01, First pseudo-ground pin; P02, Second pseudo-ground pin; P03, Third pseudo-ground pin; P04, First high-side gate drive supply voltage pseudo-pin; P05, Second high-side gate drive supply voltage pseudo-pin; P06, Fourth pseudo-ground pin; P07, Gate jumper pad pseudo-pin. Detailed Implementation

[0039] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0044] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0045] To address the technical problems mentioned in the background section, this application provides a semiconductor device. In some embodiments, the semiconductor device may be a highly integrated intelligent power module that integrates discrete devices such as a fan inverter (or inverter), a compressor inverter, a power factor correction (PFC) unit, and a rectifier bridge. The semiconductor device includes: a substrate; a power factor corrector and a rectifier bridge disposed adjacent to each other on the substrate and spaced apart in a first direction; a drive-side frame disposed on the outer side of the substrate and spaced apart from the substrate in a second direction, the drive-side frame including a PFC pin frame and a rectifier pin frame spaced apart in the first direction, the PFC pin frame including a plurality of PFC drive-side pins, the rectifier pin frame being electrically connected to the rectifier bridge; a PFC driver integrated circuit disposed on the PFC pin frame and electrically connected to the power factor corrector; and a molding compound for encapsulating the substrate, the drive-side frame, the PFC driver integrated circuit, the power factor corrector, and the rectifier bridge, wherein at least partially, the plurality of PFC drive-side pins extend from the molding compound, wherein a first groove is provided in the molding compound between the PFC pin frame and the rectifier pin frame, the first groove being recessed into the molding compound from the side of the molding compound closer to the drive-side frame in the second direction.

[0046] In order to ensure electrical isolation between different pins, the semiconductor device provided in this application provides a groove in the molding compound between the PFC pin frame and the rectifier pin frame. This groove can lengthen the surface current path between adjacent pins, improve the creepage distance and clearance performance between adjacent pins, thereby improving the electrical isolation performance between pins and enhancing the operational stability of the integrated semiconductor device.

[0047] The following is in conjunction with the appendix Figures 1 to 13The semiconductor device proposed in the embodiments of this application will be described. To ensure clarity of view, some structural reference numerals may be omitted in some of the drawings; these can be obtained by referring to other drawings. Without conflict, the various technical features in the embodiments of this application can be combined with each other.

[0048] like Figure 1 As shown, exemplarily, in some embodiments, the semiconductor device 100 may integrate a first inverter section 101, a second inverter section 201, a power factor corrector 303, and a rectifier bridge 401. The first inverter section 101 includes a first inverter circuit element, which may be, for example, a fan inverter circuit element or a compressor inverter circuit element. The second inverter section 201 includes a second inverter circuit element, which may also be, for example, a compressor inverter circuit element or a fan inverter circuit element. It should be noted that... Figure 1 The irregularly shaped dashed boxes are only used to illustrate the relative positional distribution of the first inverter unit 101, the second inverter unit 201, the power factor corrector 303, and the rectifier bridge 401, and are not intended to limit the structural dimensions of each integrated object or the devices contained therein.

[0049] like Figure 2 As shown, the semiconductor device 100 further includes a substrate 500, a drive-side frame 600, and a molding compound 700. The substrate 500, drive-side frame 600, first inverter 101, second inverter 201, power factor corrector 303, and rectifier bridge 401 are disposed within the molding compound 700. It should be noted that "disposed within the molding compound" means that at least a portion of one or more of the substrate 500, drive-side frame 600, first inverter 101, second inverter 201, power factor corrector 303, and rectifier bridge 401 is located within the molding compound 700 (or encapsulated by the molding compound), but at least a portion may be exposed from the molding compound; for example, at least a portion of the substrate may be exposed from the molding compound.

[0050] For example, such as Figure 2 As shown, the semiconductor device has a first direction, a second direction, and a third direction, which are perpendicular to each other. Using a Cartesian coordinate system to represent the three-dimensional space, the first direction can be the X-axis direction, or it can be described as the horizontal or length direction. The second direction can be the Y-axis direction, or it can be described as the vertical or width direction. The third direction can be the Z-axis direction, or it can be described as the longitudinal direction.

[0051] In addition, such as Figure 2 The dashed line shown in the diagram, in the second direction, has the drive side and the power side on either side, respectively. In the following description, the names of various devices will be distinguished from the perspective of the power side and the drive side; these names are not intended to be necessary limitations on the structure or characteristics of the corresponding devices.

[0052] In some embodiments, the substrate 500 in the semiconductor device may be one of the following substrates: thin film ceramic substrate (TFC), thick film printed ceramic substrate (TPC), direct bonded copper ceramic substrate (DBC), direct aluminum-clad ceramic substrate (DBA), direct electroplated copper ceramic substrate (DPC), active metal-bonded ceramic substrate (AMB), direct sputtered copper ceramic substrate (DSC), and laser activated metal-ceramic substrate (LAM).

[0053] The substrate 500 may include pads and an insulating heat dissipation layer disposed below the pads. The insulating heat dissipation layer is mainly formed by sequentially stacking an insulating resin sheet and a copper layer, or by sequentially stacking an insulating resin sheet and an aluminum layer. The main material of the pads is copper or aluminum. In this case, most of the substrate 500 is encapsulated by the molding compound 700, and the outer surface of the copper layer or the outer surface of the aluminum layer in the insulating heat dissipation layer of the substrate 500 is exposed from the outer surface of the molding compound 700. Alternatively, the substrate 500 may include pads, an insulating layer, and a heat dissipation layer formed by sequentially stacking layers. The main material of the pads is a copper layer or an aluminum layer, the main material of the insulating layer is a ceramic insulating layer made of AlN, Al2O3, Si3N4, or a combination of several materials, and the main material of the heat dissipation layer is a copper layer or an aluminum layer. In this case, most of the substrate 500 is encapsulated by the molding compound 700, and the outer surface of the heat dissipation layer of the substrate 500 is exposed from the outer surface of the molding compound 700. Alternatively, the substrate 500 may include pads and an insulating layer disposed below the pads, wherein the main material of the insulating layer is an ALN ​​ceramic insulating layer, or an AL2O3 ceramic insulating layer, or a Si3N4 ceramic insulating layer. In this case, most of the substrate 500 is encapsulated by the molding compound 700, and the outer surface of the insulating layer of the substrate 500 is exposed from the outer surface of the molding compound 700. Alternatively, the substrate 500 can be formed solely of solder pads. In this case, the substrate 500 is disposed within the molding compound 700, which completely encapsulates the substrate 500. The specific structural form of the substrate 500 can be adjusted according to the specific requirements and application environment of the smart power module.

[0054] The first inverter circuit element 103, the second inverter circuit element 203, the power factor corrector 303, and the rectifier bridge 401 can be disposed on the same substrate, or there can be multiple substrates, with the first inverter circuit element 103, the second inverter circuit element 203, the power factor corrector 303, and the rectifier bridge 401 each disposed on one substrate, or at least two of them disposed on one substrate, and the others disposed on one or more other substrates.

[0055] The inverter section comprises multiple inverter power chips (i.e., inverter circuit elements) to form the inverter circuit. For example, a three-phase inverter bridge circuit can be composed of six inverter power chips. The three-phase inverter bridge circuit includes three-phase upper bridge arm inverter power chips and three-phase lower bridge arm inverter power chips. The inverter power chips can be composed of insulated-gate bipolar transistors (IGBTs) and freewheeling diodes (FRDs), or they can be metal-oxide-semiconductor field-effect transistors (MOS transistors), or they can be RC-IGBTs (reverse-conducting IGBTs that integrate the IGBT and freewheeling diode into a single chip).

[0056] In some embodiments, the semiconductor device 100 includes a power factor corrector 303 and a rectifier bridge 401, and the PFC module includes a driver integrated circuit 302 and a power factor corrector 303. The power factor corrector 303 and the rectifier bridge 401 are disposed adjacent to each other on a substrate 500 and spaced apart in a first direction. Specifically, the first direction is lateral, and the power factor corrector 303 and the rectifier bridge 401 are disposed adjacent to each other in the lateral direction of the substrate 500. Unless otherwise specified, the PFC module referred to herein is an abbreviation for the PFC driver integrated circuit 302 and the power factor corrector 303. The rectifier bridge 401 may include rectifier bridge pads 402 and rectifier chips 403.

[0057] A rectifier bridge 401 is formed by multiple rectifier diodes, for example, by combining four rectifier diodes spaced apart. The rectifier bridge composed of four rectifier diodes converts the input AC power into DC power and outputs it.

[0058] The PFC power chip on the PFC module includes a PFC power switch chip and a PFC diode. These components form part of the PFC circuit, which adjusts the power factor of the DC power supply before outputting the adjusted DC power. The PFC power switch chip can be composed of an insulated-gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT (a reverse-conducting IGBT that integrates the IGBT and freewheeling diode onto a single chip).

[0059] Specifically, the substrate 500 has a first power-side pad 501, a second power-side pad 502, a PFC power-side pad 503, and a rectifier bridge pad 402. The first power-side pad 501 is the power-side pad corresponding to the first inverter circuit element 103, the second power-side pad 502 is the power-side pad corresponding to the second inverter circuit element 203, and the PFC power-side pad 503 is the power-side pad corresponding to the power factor corrector 303. The first power-side pad 501, the second power-side pad 502, the PFC power-side pad 503, and the rectifier bridge pad 402 are spaced apart in a first direction, and the first inverter circuit element 103, the second inverter circuit element 203, the power factor corrector 303, and the rectifier bridge 401 are respectively disposed on the first power-side pad 501, the second power-side pad 502, the PFC power-side pad 503, and the rectifier bridge pad 402.

[0060] In some embodiments, such as Figure 2 As shown, the drive-side frame 600 is disposed on the outer side of the substrate 500 and is spaced apart from at least a portion of the substrate 500 in a second direction. The drive-side frame 600 includes PFC pin frames (such as...) spaced apart in the first direction. Figure 2 The portion within the dashed box A4) and the rectifier pin frame (such as...) Figure 2 (The portion within the dashed box A'). The PFC pinframe includes a PFC driver-side pad 609 and multiple PFC driver-side pins 605. A PFC driver integrated circuit 302 is disposed on the PFC driver-side pad 609 of the PFC pinframe. The PFC driver integrated circuit 302 is electrically connected to at least a portion of the multiple PFC driver-side pins 605, for example, via wires. A power factor corrector 303 is electrically connected to both the PFC driver-side pad 609 and the PFC driver integrated circuit 302. For example, the power factor corrector 303 may include a power chip. Specifically, the gate of the power chip may be electrically connected via a wire to a gate jumper pad pseudo-pin P07 between pins 4 and 5. The PFC driver integrated circuit 302 is then connected via a wire to the gate jumper pad pseudo-pin P07, thus achieving the electrical connection between the power factor corrector 303 and the PFC driver integrated circuit 302.

[0061] The substrate 500 has a PFC power side pad 503, and the PFC pin frame and the PFC power side pad 503 are at least partially corresponding in a second direction, for example, at least half of them correspond to each other.

[0062] In some embodiments, such as Figure 2As shown, a rectifier bridge pad 402 is also provided on the substrate 500. A rectifier pin frame is at least partially corresponding to the rectifier bridge pad 402 in a second direction, for example, at least half of it corresponds to the pad. The rectifier pin frame extends at least partially to the rectifier bridge pad 402. A rectifier chip 403 is provided on the rectifier bridge pad 402. Exemplarily, the rectifier pin frame is electrically connected to the rectifier chip 403 of the rectifier bridge 401. For example, the rectifier pin frame includes rectifier bridge driver-side pins 606, which are electrically connected to the rectifier bridge pad 402, while the rectifier chip 403 is disposed on the rectifier bridge pad 402 and electrically connected to the rectifier bridge driver-side pins 606 via the pad 402. For example, the rectifier pin frame includes two rectifier bridge driver-side pins 606. In other embodiments, the number of rectifier bridge driver-side pins 606 is not limited to two.

[0063] In some embodiments, such as Figure 2 As shown, the semiconductor device 100 includes a molding compound 700. The molding compound 700 is used to encapsulate various integrated objects, such as a substrate 500, a drive-side frame 600, a power factor corrector 303, and a rectifier bridge 401, wherein the rectifier bridge 401 includes a rectifier chip 403 and rectifier bridge pads 402. In other words, the substrate 500, the drive-side frame 600, the power factor corrector 303, and the rectifier bridge 401 are disposed within the molding compound 700. It should be noted that "located within the molding compound" means that at least a portion of one or more of the substrate 500, drive-side frame 600, power factor corrector 303, and rectifier bridge 401 is located within the molding compound 700 (or encapsulated by the molding compound), and at least a portion may be exposed from the molding compound. For example, at least a portion of the substrate may be exposed from the molding compound 700, and at least a portion of, for example, of the plurality of PFC drive-side pins 605 and the two rectifier bridge drive-side pins 606 may extend from the molding compound 700.

[0064] The molded package 700 is obtained by mold encapsulation, which can be formed, for example, using a thermosetting resin through transfer molding. The molded package can be epoxy resin or other resin materials suitable for semiconductor module encapsulation. The two opposite sides of the molded package in the second direction are the drive side and the power side (described in detail later). The molded package can provide physical and electrical protection for at least part of the substrate, the first inverter section, the second inverter section, etc. encapsulated therein, to prevent damage to at least part of the heat dissipation substrate, RC-IGBT, and driver integrated circuit caused by external environmental impacts, and to ensure the normal operation of the semiconductor device 100.

[0065] In some embodiments, the semiconductor device 100 further includes a first inverter circuit element 103 and a second inverter circuit element 203, which are respectively disposed on a first power side pad 501 and a second power side pad 502 of the substrate 500. The first inverter circuit element 103, the second inverter circuit element 203, the power factor corrector 303, and the rectifier bridge 401 are spaced apart from each other in a first direction.

[0066] For example, the drive-side frame 600 further includes a first frame and a second frame, the first frame, the second frame, the PFC pin frame, and the rectifier pin frame being arranged at intervals in a first direction. For example, as Figure 2 As shown, dashed box A1 indicates the basic range corresponding to the driver-side frame 600, dashed box A2 indicates the basic range corresponding to the first frame, dashed box A3 indicates the basic range corresponding to the second frame, and dashed box A4 indicates the basic range corresponding to the PFC pin frame. Dashed box A' indicates the basic range corresponding to the rectifier pin frame. It should be noted that since integrated circuits are often irregularly shaped... Figure 2 The dashed boxes A1, A2, A3, A4, etc., and other dashed boxes mentioned later are only used to indicate the general location and are not intended to limit the corresponding frame structure or shape.

[0067] The first frame and the first power-side pad 501 are at least partially corresponding in a second direction. For example, the first frame is a fan drive-side frame, and the first power-side pad 501 is a fan power-side pad. The fan drive-side frame and the fan power-side pad are at least partially corresponding in a second direction. Furthermore, the second frame and the second power-side pad 502 are at least partially corresponding in a second direction. For example, the second frame is a compressor drive-side frame, and the second power-side pad 502 is a compressor power-side pad. The compressor drive-side frame and the compressor power-side pad are at least half corresponding to each other in a second direction. It is worth noting that in this embodiment, the correspondence between the frame and the power-side pad is at least partial.

[0068] In some embodiments, the first frame may include a first driver-side pad 601 and a plurality of first driver-side pins 602. For example, Figure 2 As shown, the first driver-side pad 601 can be two, namely a first low-voltage driver-side pad 6011 and a first high-voltage driver-side pad 6012. The second frame includes a second driver-side pad 603 and multiple second driver-side pins 604. Figure 2 As shown, there can be two second drive side pads 603, namely a second low-voltage drive side pad 6031 and a second high-voltage drive side pad 6032.

[0069] In some embodiments, the molding compound 700 is also used to encapsulate the first inverter section 101 and the second inverter section 201, etc. In other words, the substrate 500, the drive-side frame 600, the first inverter section 101, the second inverter section 201, the power factor corrector 303, and the rectifier bridge 401 are disposed within the molding compound 700. It should be noted that "disposed within the molding compound" means that at least a portion of one or more of the substrate 500, the drive-side frame 600, the first inverter section 101, the second inverter section 201, the power factor corrector 303, and the rectifier bridge 401 is located within the molding compound 700 (or is encapsulated by the molding compound), and at least a portion may be exposed from the molding compound. For example, at least a portion of the substrate may be exposed from the molding compound 700, and at least a portion of, for example, of the plurality of first drive-side pins 602, the plurality of second drive-side pins 604, the plurality of PFC drive-side pins 605, and the two rectifier bridge drive-side pins 606 may extend from the molding compound 700. Furthermore, the portions of multiple first drive-side pins 602 located outside the molding compound 700 and the portions of multiple second drive-side pins 604 located outside the molding compound 700 have the same arrangement in the first direction, that is, the pin order of the two is consistent. For example, they are both divided into a low-voltage pin area and a high-voltage pin area. The low-voltage pin area is arranged in the following order: over-temperature protection pin, power ground pin, over-current protection pin, fault output pin, low-side power supply pin, and PWM input signal pin. The high-voltage area is arranged as follows: high-side floating power supply voltage pin, high-side floating power supply ground, and PWM input signal pin.

[0070] By using the driver-side frame 600 to house the driver integrated circuit and integrate the driver-side pins, high integration can be achieved, the number of components can be reduced, the overall size can be minimized, and the semiconductor device structure can be made more compact. Furthermore, heat dissipation can be enhanced, improving the stability and reliability of the semiconductor device. The identical arrangement of the driver-side pins for the two inverter sections reduces hardware design complexity, facilitates module assembly and installation, and improves manufacturing efficiency. The identical arrangement also improves layout symmetry, avoiding high-frequency noise problems caused by layout asymmetry.

[0071] It should be noted that in other embodiments, a PCB board can be used instead of the driver-side frame 600. The PCB board (i.e., printed circuit board) is encapsulated in a plastic package. The PCB board has driver-side pads, and driver-side pins are electrically connected to the PCB board (e.g., by soldering or other suitable methods). Driver integrated circuits are disposed on the driver-side pads, and the driver integrated circuits are electrically connected to the driver-side pins. The side of the PCB board used to house the driver integrated circuits can have various wiring and pad areas for placing the driver integrated circuits. The wiring can realize the electrical connection between each pad area and the corresponding driver-side pin or structure. Specifically, the structure of the PCB board can be reasonably selected according to actual needs, and no specific limitation is made here. The PCB board can realize the wiring and support of the driver integrated circuits, and the PCB board structure is simple and more friendly to packaging. In some examples, the driver-side pins and the corresponding driver-side pads on the PCB board can be electrically connected by means such as soldering, connector connection, bonding wire, or spring connection, and no specific limitation is made here.

[0072] A PCB board can be a substrate formed by patterning conductive copper foil on the surface of an insulating material (such as fiberglass, epoxy resin, etc.) to create electrical connections between electronic components. The PCB board uses these copper foil lines to achieve electrical connections between electronic components and to support and fix the components on the board. Optionally, the PCB board can be a single-sided, double-sided, or multi-sided PCB board.

[0073] Specifically, in some embodiments, such as Figure 3 As shown, the first inverter unit 101 may include a first driver integrated circuit 102 and a first inverter circuit element 103.

[0074] The substrate 500 generally has a first side and a second side arranged opposite to each other. The first inverter circuit element 103 (e.g., RC-IGBT) can be disposed on the first side of the heat dissipation substrate 500, which is the side of the heat dissipation substrate 500 with power side pads. The RC-IGBT can be disposed on the power side pads.

[0075] The substrate 500 supports the first inverter circuit element 103 (e.g., RC-IGBT), and its good thermal conductivity improves the heat dissipation of the RC-IGBT, thus enhancing its reliability. The power-side pads on the first side of the heat-dissipating substrate allow the RC-IGBT to be led out for electrical connection with other components. Furthermore, directly placing the RC-IGBT on the power-side pads enables direct electrical connection, optimizing the wiring of the semiconductor device.

[0076] For example, combined Figure 2 and Figure 3 As shown, the first inverter circuit element 103 can be disposed on the first power side pad 501. The first inverter circuit element 103 may include a first low-voltage inverter circuit element 1031 and a first high-voltage inverter circuit element 1032. The first power side pad 501 may include a first low-voltage power side pad 5011 and a first high-voltage power side pad 5012. Correspondingly, the first low-voltage inverter circuit element 1031 may be disposed on the first low-voltage power side pad 5011, and the first high-voltage inverter circuit element 1032 may be disposed on the first high-voltage power side pad 5012.

[0077] For example, a first driver integrated circuit 102 is disposed on a first driver-side pad 601. The first driver integrated circuit 102 may include a first low-voltage driver integrated circuit 1021 and a first high-voltage driver integrated circuit 1022. Correspondingly, the first low-voltage driver integrated circuit 1021 may be disposed on the first low-voltage driver-side pad 6011, and the first high-voltage driver integrated circuit 1022 may be disposed on a second high-voltage driver-side pad.

[0078] In some embodiments, the number of first low-voltage inverter circuit elements 1031 can be multiple, and the number of first high-voltage inverter circuit elements 1032 can also be multiple. The number of first low-voltage power side pads 5011 can be multiple, for example, three. The number of first high-voltage power side pads 5012 is at least one, for example, one.

[0079] For example, the inverter circuit elements can be reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) or IGBTs. For instance, taking RC-IGBTs as the inverter circuit elements, the number of RC-IGBTs can be multiple, such as including three high-voltage power-side RC-IGBTs and three low-voltage power-side RC-IGBTs constituting the inverter. Specifically, the number of RC-IGBTs can be reasonably set according to actual needs.

[0080] A reverse-conducting IGBT can be a basically rectangular semiconductor switching element, comprising an IGBT mounted on a single semiconductor substrate and a freewheeling diode. Since individual IGBT chips or freewheeling diodes mounted on different semiconductor substrates each contain a termination region and an active region, the termination portion can be shared when two devices are combined into a single chip, thereby reducing the area of ​​the termination portion. Therefore, the size of an RC IGBT is typically smaller than the size of a structure where the IGBT and freewheeling diode are mounted on different semiconductor substrates. Thus, using an RC IGBT as the power chip in a semiconductor device can reduce the size of the power chip and even the size of the entire semiconductor device. Reverse-conducting insulated-gate bipolar transistors are single-chip power devices, which reduces the number of chips on the semiconductor device 100 and the number of bonding wires.

[0081] In some embodiments, the RC-IGBT may include a termination structure, which may employ a lateral variable doping structure. Employing a lateral variable doping structure offers the following advantages and benefits: compared to a field-limiting ring or a field-limiting ring plus a field plate termination structure, the lateral variable doping structure of the RC-IGBT can further reduce the chip area of ​​the RC-IGBT, thereby facilitating module miniaturization.

[0082] Lateral doping refers to the formation of a region with a gradual change in impurity doping concentration in the terminal region of a device through methods such as ion implantation. Typically, ion implantation is performed on the substrate region near the heavily doped main junction to form a lateral doping structure. The doping concentration is higher in the region closer to the main junction and lower in the region farther away.

[0083] In the first inverter unit 101, the first driver integrated circuit 102 is electrically connected to the first inverter circuit element 103. The first inverter circuit element 103 may be, for example, an RC-IGBT or an IGBT. Taking an RC-IGBT as an example, the driver integrated circuit and the RC-IGBT are electrically connected for controlling the RC-IGBT. For example, the driver integrated circuit and the RC-IGBT are electrically connected via an electrical connector, such as a wire. The driver integrated circuit controls the RC-IGBT, for example, by driving the RC-IGBT to turn it on or off, or by protecting the RC-IGBT in case of abnormalities (e.g., overvoltage protection and / or overtemperature protection and / or electrostatic discharge protection, etc.).

[0084] It should be noted that the number of driving integrated circuits in the first inverter unit 101 or the second inverter unit 201 can be reasonably set according to the RC-IGBTs that need to be driven. For example, the number of driving integrated circuits can be one or more. When the number is multiple, it can include one high-voltage driving integrated circuit and one low-voltage driving integrated circuit, or it can include three high-voltage driving integrated circuits and one low-voltage driving integrated circuit, or other suitable cases. The high-voltage driving integrated circuit drives the high-voltage power-side RC-IGBT to turn on or off, while the low-voltage driving integrated circuit drives the low-voltage power-side RC-IGBT to turn on or off. Optionally, the driving integrated circuit can integrate multiple electronic components, such as transistors, diodes, triodes, resistors, or capacitors.

[0085] Specifically, such as Figure 2 or Figure 3 As shown, the first low-voltage drive integrated circuit 1021 and the first low-voltage inverter circuit element 1031 in the first inverter section 101 are electrically connected by wires. Correspondingly, the first high-voltage drive integrated circuit 1022 is electrically connected to the first high-voltage inverter circuit element 1032, and the first low-voltage drive integrated circuit 1021 is electrically connected to the first low-voltage inverter circuit element 1031.

[0086] Furthermore, the first driver integrated circuit 102 is electrically connected to some pins of a plurality of first driver-side pins 602. For example... Figure 3 As shown in the figure, the multiple pins shown within the dashed box A5 are multiple first drive-side pins 602. Specifically, the first high-voltage drive integrated circuit 1022 and the first low-voltage drive integrated circuit 1021 may be connected to at least one of the first drive-side pins 602 via wires.

[0087] like Figure 4 As shown, similar to the first inverter section, the second inverter section 201 includes a second driver integrated circuit 202 and a second inverter circuit element 203. The second driver integrated circuit 202 may include a second low-voltage driver integrated circuit 2021 and a second high-voltage driver integrated circuit 2022. The second inverter circuit element 203 may include a second low-voltage inverter circuit element 2031 and a second high-voltage inverter circuit element 2032.

[0088] The second driver integrated circuit 202 can be disposed on the second driver-side pad 603. Correspondingly, the second low-voltage driver integrated circuit 2021 can be disposed on the second low-voltage driver-side pad 6031, and the second high-voltage driver integrated circuit 2022 can be disposed on the second high-voltage driver-side pad 6032. The second inverter circuit element 203 can be disposed on the second power-side pad 502. The second power-side pad 502 includes a second low-voltage power-side pad 5021 and a second high-voltage power-side pad 5022. Specifically, the second low-voltage inverter circuit element 2031 can be disposed on the second low-voltage power-side pad 5021, and the second high-voltage inverter circuit element 2032 can be disposed on the second high-voltage power-side pad 5022.

[0089] In some embodiments, the number of second low-voltage inverter circuit elements 2031 can be multiple, and the number of second high-voltage inverter circuit elements 2032 can also be multiple. The number of second low-voltage power side pads 5021 can be multiple, for example, three. The number of second high-voltage power side pads 5022 is at least one, for example, one.

[0090] The second driver integrated circuit 202 is electrically connected to the second inverter circuit element 203, for example, via a jumper. The second driver integrated circuit 202 is also electrically connected to at least a portion of a plurality of second driver-side pins 604. Figure 4 As shown in the dashed box A6, the multiple pins within the dashed box A6 are the second driver-side pins 604.

[0091] Furthermore, in some embodiments, the multiple pins corresponding to the high-voltage drive side and the multiple pins corresponding to the low-voltage drive side in the first inverter unit 101 are independently and spaced apart from each other in a first direction. For example, the multiple pins corresponding to the low-voltage drive side may specifically be multiple pins corresponding to the first low-voltage drive integrated circuit 1021 and / or the first low-voltage drive side pad 6011, and multiple pins corresponding to the first high-voltage drive integrated circuit 1022 and / or the first high-voltage drive side pad 6012. The term "corresponding" may refer to a corresponding distribution in a second direction or an electrical connection between the pins and the drive integrated circuit.

[0092] In some embodiments, the plurality of pins corresponding to the high-voltage drive side and the plurality of pins corresponding to the low-voltage drive side in the second inverter unit 201 are independently and spaced apart from each other in a first direction. For example, the plurality of pins corresponding to the low-voltage drive side may specifically be the plurality of pins corresponding to the second low-voltage drive integrated circuit 2021 and / or the second low-voltage drive side pad 6031, and the plurality of pins corresponding to the second high-voltage drive integrated circuit 2022 and / or the second high-voltage drive side pad 6032. The term "corresponding" may refer to a corresponding distribution in the second direction or an electrical connection between the pins and the drive integrated circuit.

[0093] On the driver side, multiple corresponding pins are included in the first frame, the second frame, and the PFC pin frame, including long pins and short pins exposed by the self-molding body 700, as well as dummy pins.

[0094] In some embodiments, such as Figure 2 As shown, in the first frame, multiple first driver-side pins 602 are spaced apart in a first direction to form a low-voltage pin area and a high-voltage pin area. Each first driver-side pin 602 includes multiple connection pins (designated as first connection pins for distinction) and at least one pseudo-pin (designated as first pseudo-pin for distinction). The connection pins can be the portion of the driver-side pins located outside the molding compound 700. The first pseudo-pin includes a first pseudo-ground pin P01. The multiple first connection pins include multiple long pins and multiple short pins. Long and short pins refer to pins extending from the molding compound 700 of different lengths in a second direction. The multiple first driver-side pins 602 have a first low-voltage pin area, and the first pseudo-pin is located within this first low-voltage pin area. Notably, the first low-voltage pin area is used for low-voltage (e.g., 12V logic power supply) and low-current signal transmission pin partitioning. Furthermore, the first pseudo-ground pin P01 divides the multiple connection pins within each low-voltage pin area into a first connection pin group and a second connection pin group, respectively located on either side of the first pseudo-ground pin. The pseudo-pins (such as the first pseudo-pin) do not serve as actual electrical connections and are not connected to any external objects. They serve as structural support components to better support the driver chip, frame, or substrate. The function of pseudo-pins in other frames will be discussed later in the same way, and will not be repeated below.

[0095] like Figure 9 As shown, the first pseudo-ground pin P01 has a first side and a second side opposite to each other in a first direction. The two first connection pins located on either side of the first pseudo-ground pin P01 and adjacent to it are both long pins. Long pins can typically carry larger currents and can be used to connect critical signals. The long pins on either side of the first pseudo-ground pin P01 form a current isolation band, blocking electromagnetic coupling between short pins (such as low-speed signals and feedback signals). Multiple long pins and multiple short pins are alternately distributed among the multiple first connection pins located outside the first side of the first pseudo-ground pin P01, and multiple long pins and multiple short pins are also alternately distributed among the multiple first connection pins located outside the second side of the first pseudo-ground pin P01.

[0096] Similarly, as Figure 2As shown, in the second frame, multiple second drive-side pins 604 are spaced apart in the first direction to form a low-voltage pin area and a high-voltage pin area. The multiple second drive-side pins 604 include multiple connection pins (designated as second connection pins for distinction) and at least one pseudo-pin (designated as a first pseudo-pin for distinction). The first pseudo-pin in the second frame includes a second pseudo-ground pin P02. The multiple second connection pins include multiple long pins and multiple short pins, where long and short pins refer to the different lengths of the pins extending from the self-molding body 700 in the second direction. The multiple second drive-side pins 604 have a second low-voltage pin area, and the second pseudo-pin is located within this second low-voltage pin area. It is worth noting that the second low-voltage pin area is used for pin partitioning for low-voltage (e.g., 12V logic power supply) and low-current signal transmission.

[0097] The second pseudo-ground pin P02 has a first side and a second side opposite to each other in a first direction. Two second connection pins located on either side of the second pseudo-ground pin P02 and adjacent to it are both long pins. Furthermore, multiple long pins and multiple short pins are alternately distributed among the multiple second connection pins located outside the first side of the second pseudo-ground pin P02, and multiple long pins and multiple short pins are alternately distributed among the multiple second connection pins located outside the second side of the second pseudo-ground pin P02. The functions of the multiple second drive-side pins 604 are similar to those of the first drive-side pin 602, as described above, and will not be repeated here.

[0098] In some examples, such as Figure 9 As shown, the drive-side frame 600 also includes at least one second pseudo-pin, which is disposed between a plurality of first drive-side pins 602 and a plurality of second drive-side pins 604. Specifically, the first frame also includes two second pseudo-pins, which are distributed between adjacent first connection pins and second connection pins in a first direction. The two second pseudo-pins include a third pseudo-ground pin P03 and a first high-side gate drive supply voltage pseudo-pin P04. In a specific example, the two second pseudo-pins may be arranged in the boundary region between the first inverter section and the second inverter section.

[0099] Continue as Figure 9As shown, in the first direction, adjacent first and second connection pins are short pins, such as first connection pin 28 and second connection pin 27. In a specific example, first connection pin 28 is a pin on the drive side of the fan inverter section, and second connection pin 27 is a pin on the drive side of the compressor inverter section. Typically, the compressor inverter section and the fan inverter section use high-frequency switches, and their operating frequencies may be different. Short pins reduce parasitic capacitance coupling between the two by shortening the signal path, thus avoiding crosstalk between high-frequency harmonics. For example, if the pin at the junction is too long, the dV / dt noise of the compressor IPM may interfere with the drive signal of the fan IPM through pin coupling, causing the fan speed to fluctuate.

[0100] Continue as Figure 2 As shown, the PFC pin frame, similar to the setup in the first and second frames, also includes multiple PFC driver-side pins 605. The PFC driver-side pins include multiple third connection pins composed of multiple long pins and multiple short pins. The long pins and short pins extending from the molding compound 700 have different lengths in the second direction. The long pins and short pins in the multiple third connection pins are alternately distributed in the first direction. The setup and function of the third connection pins in the first PFC pin frame are similar to the setup and function of the first connection pins in the first frame and the second connection pins in the second frame, and will not be elaborated here. Please refer to the previous description for details.

[0101] In some examples, the second frame also includes two third pseudo-pins, whose distribution and function are similar to the two second pseudo-pins in the first frame. Depending on the location of the PFC module, in the first direction, the two third pseudo-pins can be distributed between adjacent third and second connection pins, or between adjacent third and first connection pins. Similar to the arrangement of the two pseudo-pins, such as... Figure 9 As shown, the third pseudo-pin includes a fourth pseudo-ground pin P06 and a second high-side gate drive supply voltage pseudo-pin P05.

[0102] In some examples, depending on the location of the PFC module, in the first direction, one of the adjacent third and second connection pins may be a short pin and the other a long pin, or one of the adjacent third and first connection pins may be a short pin and the other a long pin. Specifically, in the boundary area between the first inverter unit and the PFC module, or in the boundary area between the second inverter unit and the PFC module, adjacent connection pins may have one short pin and one long pin, such as... Figure 9 As shown, the second connection pin 10 is a short pin, and the third connection pin 9 is a long pin.

[0103] In some embodiments, the aforementioned first connection pin group includes, in a first direction, the following pins are arranged at intervals: an over-temperature protection pin, a PFC power ground pin, an over-current protection pin, a fault output port pin, a low-side gate drive supply voltage pin, and low-side input signal pins (e.g., W2 phase low-side input signal pin, V2 phase low-side input signal pin, and U2 phase low-side input signal pin); the second connection pin group includes, in a first direction, the following pins are arranged at intervals: a high-side gate drive supply voltage pin, a W2 phase high-side input signal pin, a V2 phase high-side input signal pin, and a U2 phase high-side input signal pin.

[0104] In some embodiments, the first inverter circuit element 103 is a fan inverter section, and the second inverter circuit element 203 is a compressor inverter section, wherein... The multiple connection pins located in the low-voltage pin area of ​​the multiple first drive side pins 602 include the following pins arranged sequentially and at intervals in the first direction: fan over-temperature protection pin, fan power ground pin, fan overcurrent protection pin, fan fault output port pin, fan low-side gate drive power supply voltage pin, fan W2 phase low-side input signal pin, fan V2 phase low-side input signal pin, fan U2 phase low-side input signal pin, fan high-side gate drive power supply voltage pin, fan W2 phase high-side input signal pin, fan V2 phase high-side input signal pin, and fan U2 phase high-side input signal pin; The multiple connection pins located in the high-voltage pin area of ​​the multiple first drive side pins 602 include the following pins arranged sequentially and at intervals in the first direction: the high-side drive floating power supply voltage pin of the W2 phase of the wind turbine, the high-side drive floating power supply ground pin of the W2 phase of the wind turbine, the high-side drive floating power supply voltage pin of the V2 phase of the wind turbine, the high-side drive floating power supply ground pin of the V2 phase of the wind turbine, the high-side drive floating power supply voltage pin of the U2 phase of the wind turbine, and the high-side drive floating power supply ground pin of the U2 phase of the wind turbine. The multiple connection pins located in the low-voltage pin area of ​​the multiple second drive side pins 604 include the following pins arranged sequentially and at intervals in the first direction: compressor over-temperature protection pin, compressor power ground pin, compressor overcurrent protection pin, compressor fault output port pin, compressor low-side gate drive power supply voltage pin, compressor W1 phase low-side input signal pin, compressor V1 phase low-side input signal pin, compressor U1 phase low-side input signal pin, compressor high-side gate drive power supply voltage pin, compressor W1 phase high-side input signal pin, compressor V1 phase high-side input signal pin, and compressor U1 phase high-side input signal pin; The multiple connection pins located in the high-voltage pin area of ​​the multiple second drive side pins (604) include the following pins arranged sequentially and at intervals in the first direction: compressor W1 phase high-side drive floating power supply voltage pin, compressor W1 phase high-side drive floating power supply ground pin, compressor V1 phase high-side drive floating power supply voltage pin, compressor V1 phase high-side drive floating power supply ground pin, compressor U1 phase high-side drive floating power supply voltage pin, and compressor U1 phase high-side drive floating power supply ground pin; The multiple connection pins in the multiple PFC driver side pins (605) include the following pins arranged sequentially and at intervals in the first direction: PFC driver IC power supply voltage pin, PFC power ground pin, enable I / O function pin, PFC input signal pin, current detection input pin, temperature sensor connector 2 pin, and temperature sensor connector 1 pin.

[0105] The pins on the driver side will be described in more detail below.

[0106] like Figure 6 As shown, for example, the pin numbers and definitions of the semiconductor device on the driving side are as shown in Table 1: Table 1 Pins numbered 28-45 are the first driver-side pins 602, corresponding to multiple pins of the first inverter section. Pins numbered 27-10 are the second driver-side pins 604, corresponding to multiple pins of the second inverter section. Pins numbered 9-3 are the PFC driver-side pins 605, corresponding to multiple pins of the PFC section. Pins numbered 1-2 are the two rectifier bridge driver-side pins 606 corresponding to the rectifier bridge. In some examples, pins 45-34 constitute the first low-voltage pin area, pins 33-28 constitute the first high-voltage pin area, pins 27-16 constitute the second low-voltage pin area, and pins 15-10 constitute the second high-voltage pin area. By setting up low-voltage and high-voltage pin areas, the low-voltage pin area (such as sensor feedback, PWM control signals, and communication interfaces) typically transmits low-amplitude, high-sensitivity signals (such as 0-5V or digital signals). If the layout is mixed with high-voltage pins (such as rectifier bridge output, PFC bus voltage), the high-frequency switching noise or large current transients of the high-voltage pins will interfere with the low-voltage signals through crosstalk or ground bounce, resulting in control logic errors or sensor reading distortion. At the same time, physical isolation between the low-voltage pin area and the high-voltage pin area can block the conduction path of high-frequency noise (such as common-mode current loop) and reduce radiated noise coupling.

[0107] The following is a combination of Table 1 and... Figure 5 , Figure 6The accompanying drawings provide a detailed exemplary description of the pin designs in semiconductor devices proposed in some embodiments of this application.

[0108] like Figure 5 As shown, on the driving side, in the first direction, there are multiple pins extending from the self-encapsulation body, which have two specifications: one is long pins and the other is short pins, and the long pins and short pins are alternately distributed in the first direction.

[0109] For example, in some embodiments, the long pins and short pins of at least a portion of the plurality of first drive-side pins 602 corresponding to the first inverter section and the plurality of second drive-side pins 604 corresponding to the second inverter section are alternately distributed in a first direction.

[0110] Optionally, in some embodiments, the multiple PFC driver-side pins 605 corresponding to the PFC module include multiple pins extending from the self-molding body 700, which may have long pins and short pins, or may be distributed with alternating long and short pins in the first direction. In other embodiments, the pins corresponding to the PFC module may not distinguish between long and short pins, that is, the design does not use an alternating long and short pin method.

[0111] It should be noted that long leads and short leads refer to the fact that the long and short leads extending from the self-encapsulated body are different in length in the second direction, but can be the same in other directions.

[0112] For example, in some embodiments, such as Figure 7 As shown, taking pin 602 as an example, a pin 602 has a chip holder 6021 and a curved portion 6022 that bends from the chip holder 6021 in a third direction, as well as an external pin portion 6023 connected to the curved portion. The difference between long pins and short pins is that the length of the chip holder 6021 is significantly different in the second direction, while the height in the third direction can be the same. The third direction is the Z-axis direction, or the height direction and thickness direction.

[0113] It should be noted that, Figure 5 , Figure 6 or Figure 7 The pins shown are for illustrative purposes only. Multiple long pins have the same size specifications, multiple short pins have the same size specifications, and the difference in length between the long and short pins in the second direction is fixed.

[0114] In other embodiments, the long pins can be further designed into various different size specifications, or the short pins can be further designed into various different size specifications. For example, a length threshold can be set, where pins with a length greater than or equal to the threshold in the second direction are defined as long pins, and pins with a length less than the threshold are defined as short pins. The difference between the lengths of the long pins and the short pins in the second direction is not unique and can have multiple values.

[0115] Furthermore, it should be noted that there are several ways to alternate between long and short pins, for example, as shown below. Figure 8a The diagram shows alternating long and short pins, meaning that in two adjacent pins, one is a long pin and the other is a short pin. Or, as shown... Figure 8b The alternating pattern of two long and two short lines shown, or it could be as follows: Figure 8c The alternation of two long and one short lines shown are just a few examples, not all of which will be listed individually.

[0116] The pins on the driver side of the semiconductor device can be used in one or more combinations of the exemplary alternation methods described above. In some embodiments, such as... Figure 2 , Figure 5 As shown, the multiple pins on the drive side all use an alternating pattern of one long and one short. In other embodiments, other alternating patterns or combinations of different alternating patterns can be used. For example, the multiple first drive-side pins 602 corresponding to the first inverter unit can use an alternating pattern of one long and one short, while the multiple pins 605 corresponding to the PFC module can use other alternating patterns such as two long and two short.

[0117] The driving side adopts an alternating design of long and short pins. By lengthening the distance between two adjacent pins in the vertical direction (second direction) and shortening the lateral distance between two adjacent pins in the horizontal direction (first direction), sufficient insulation distance can still be achieved between the two pins, enabling module miniaturization. Compared with multiple discrete devices, this integrated semiconductor device can reduce the area occupied on the control board and eliminates the need for multiple insertions.

[0118] Among them, adopt Figure 8a The alternation pattern shown, which uses an alternation of adjacent long and short pins, can save the space occupied by pins to the greatest extent while ensuring the insulation distance. For example, if there are more pins on the driver side, applying this design on the driver side can significantly affect the product size.

[0119] In some embodiments, dummy pins are used in the multiple pin designs on the driver side. A dummy pin is one that is generally not used for electrical connection to external circuitry; that is, it is not connected to any external device. Dummy pins protrude from the outer surface of the plastic package, for example... Figure 5 As shown, the dummy lead protrudes from the outer surface of the molded body 700 because it is flush with or slightly protrudes from the outer surface of the molded body in the second direction. Alternatively, a small portion of the dummy lead protrudes from the molded body, and the exposed portion is shorter than that of the short lead, for example... Figure 6 As shown, pins that protrude from the plastic package without being labeled with pin numbers are dummy pins. Connection pins refer to pins used for connecting to external devices, such as processors (e.g., MCUs) or power supplies, and are the portion of the drive-side pins located outside the plastic package 700.

[0120] In some embodiments, in conjunction with Figure 8 and Figure 6 As shown, in the first direction, the spacing between two adjacent pins of the plurality of first drive-side pins 602 corresponding to the first inverter section is equal, defined as 'a'. For example, as shown in Figure 8, the spacing between two adjacent or closest pins is 'a', such as the distance between pin 41 and pin 40 is 'a'. It is worth mentioning that the distance of the interval, also called the spacing, refers to the center-to-center distance between the pins.

[0121] Furthermore, in some embodiments, among the plurality of first driving-side pins 602, there is a pseudo-ground pin, namely a first pseudo-ground pin, and the two pins located on both sides of the first pseudo-ground pin and adjacent to the first pseudo-ground pin are two long pins. The pseudo-ground pin is one type of pseudo-pin.

[0122] For example, such as Figure 9 As shown, a first pseudo-ground pin P01 exists between pins 37 and 38. Both pins 37 and 38 are long pins. The first pseudo-ground pin divides the multiple connection pins within each low-voltage pin area into a first connection pin group and a second connection pin group, located on either side of the first pseudo-ground pin. The distance between any two adjacent connection pins in the first connection pin group is 'a', for example, the distance between pins 41 and 40 is 'a'. The distance between any two adjacent connection pins in the second connection pin group is 'a', for example, the distance between pins 36 and 35 is 'a'. Furthermore, the minimum distance between any two adjacent PFC driver-side pins 605 among the multiple PFC driver-side pins 605 is 'a', for example, the minimum distance between pins 4 and 3 is 'a'.

[0123] like Figure 9 As shown, the plurality of first drive-side pins 602 include a first pseudo-ground pin, and the spacing between two first drive-side pins located on both sides of the first pseudo-ground pin P01 and adjacent to the pseudo-ground pin is greater than or equal to 2a. For example, Figure 9 The pin between pins 37 and 38 is the first pseudo-ground pin P01, and the pins on either side of the first pseudo-ground pin P01 are pins 37 and 38, with a spacing of 2a between pins 37 and 38. In other embodiments, the spacing between pins 37 and 38 may be greater than 2a.

[0124] Similar to the pin design corresponding to the first inverter section, in the first direction, the spacing between any two adjacent pins of the plurality of second drive-side pins 604 is 'a'. The plurality of second drive-side pins includes a second pseudo-ground pin P02, a first connection pin group and a second connection pin group located on both sides of the pseudo-ground pin. The spacing between any two adjacent connection pins within the first connection pin group is 'a', for example, the distance between pin 20 and pin 21 is 'a'; the spacing between any two adjacent connection pins within the second connection pin group is 'a', for example, the distance between pin 19 and pin 18 is 'a'. Simultaneously, the spacing between any two second drive-side pins located on both sides of the second pseudo-ground pin and adjacent to the pseudo-ground pin is greater than or equal to 2a, for example, ... Figure 9 The pin between pins 20 and 19 is the second pseudo-ground pin P02. The pins on either side of the second pseudo-ground pin P02 are pins 20 and 19, and the distance between pins 20 and 19 is 2a. In other embodiments, the distance between pins 20 and 19 may be greater than 2a.

[0125] Similar to the pin design corresponding to the first inverter section and / or the second inverter section, in the first direction, the spacing between two adjacent pins of the plurality of PFC drive-side pins 605 can also be equal, and 'a'. For example... Figure 9 As shown, the plurality of PFC drive-side pins 605 include a gate jumper pad pseudo-pin P07; the spacing between two PFC drive-side pins (e.g., pin 5 and pin 4) located on both sides of the gate jumper pad pseudo-pin and adjacent to the gate jumper pad pseudo-pin is greater than or equal to 2a.

[0126] The use of dummy pins can reduce the number of pins, help maintain soldering consistency, increase insulation distance, and improve the reliability of the integrated semiconductor device.

[0127] Exemplarily, the system also includes at least one bootstrap chip. The first frame includes at least one bootstrap pad, with each bootstrap chip corresponding to one bootstrap pad. The plurality of first driver-side pins 602 further include a plurality of bootstrap pins (e.g., pins 32 and 33). Each bootstrap pin has a connection pin located outside the molding compound 700, and the connection pin of the bootstrap pin is located within the high-voltage pin area. The plurality of bootstrap pins include at least one group of bootstrap pins, each group of bootstrap pins being electrically connected to its corresponding chip. The spacing between two adjacent connection pins in each group of bootstrap pins in a first direction is 'a', for example, the lateral spacing between pins 32 and 33 is 'a'. The minimum spacing between the connection pins of adjacent groups of bootstrap pins in the first direction is greater than or equal to 3a, for example, the spacing between pins 31 and 32 in the first direction is greater than or equal to 3a.

[0128] Similar to the first frame, the second frame also includes at least one bootstrap pad, with each bootstrap chip corresponding to one bootstrap pad. The multiple second driver-side pins 604 also include multiple bootstrap pins, each bootstrap pin having a connection pin located outside the molding compound 700. The spacing between two adjacent connection pins in each group of bootstrap pins in the first direction is 'a', for example, pin 15 and pin 14 have a spacing of 'a' in the first direction. The spacing between the connection pins of adjacent groups of bootstrap pins in the first direction is greater than or equal to 3'a, for example, pin 14 and pin 13 have a spacing of greater than or equal to 3'a in the first direction.

[0129] Specifically, each set of bootstrap pins includes a first bootstrap pin and a second bootstrap pin. The first bootstrap pin has a bootstrap pad and a connection pin connected to the bootstrap pad, with the connection pin connecting to the side of the bootstrap pad away from the substrate 500. The second bootstrap pin is located outside the first bootstrap pin and extends along a second direction to protrude from the outer surface of the molding compound 700. The first bootstrap pin is a high-side drive floating supply voltage, and the second bootstrap pin is a high-side drive floating supply ground. In some specific examples, each of the multiple first drive-side pins and multiple second drive-side pins includes three sets of bootstrap pins, each set corresponding to the high-side drive floating supply voltage and high-side drive floating supply ground for the U-phase, V-phase, and W-phase, respectively.

[0130] Optionally, among the plurality of first driving side pins and the plurality of second driving side pins, the spacing in the first direction between the connection pins whose respective low-voltage pin areas are located outside the molding compound 700 and the connection pins whose adjacent high-voltage pin areas are located outside the molding compound 700 is greater than or equal to 3a. For example, the spacing between the low-voltage pin areas and high-voltage pin areas of the plurality of first driving side pins is greater than or equal to 3a, that is, the spacing between pins 34 and 33 in the lateral direction is greater than or equal to 3a; the spacing between the low-voltage pin areas and high-voltage pin areas of the plurality of second driving side pins is greater than or equal to 3a, that is, the spacing between pins 16 and 15 in the lateral direction is greater than or equal to 3a.

[0131] In some embodiments, the first frame includes a first driving-side pad 601, and the second frame includes a second driving-side pad 603. Both the first driving-side pad 601 and the second driving-side pad 603 include a low-voltage driving-side pad and a high-voltage driving-side pad. In the first frame, a plurality of bootstrap pads are disposed on the side of the high-voltage driving-side pad 601 away from the substrate. In the second frame, a plurality of bootstrap pads are disposed on the side of the high-voltage driving-side pad 603 away from the substrate. Specifically, the plurality of bootstrap pads in the first frame are disposed on the side of the first high-voltage driving-side pad 6012 away from the substrate, and the plurality of bootstrap pads in the second frame are disposed on the side of the second high-voltage driving-side pad 6032 away from the substrate.

[0132] In one embodiment, one of the multiple first drive-side pins 602 is arranged adjacent to one of the multiple second drive-side pins 604, and the distance between them is greater than or equal to 5a. Further, the pin spacing used at the junction of the multiple first drive-side pins corresponding to the first inverter and the multiple second drive-side pins corresponding to the second inverter can be 5a or greater than 5a.

[0133] In one embodiment, the second frame and the PFC pin frame are arranged adjacent to each other, and a connection pin of one of the plurality of second drive-side pins 604 and a PFC drive-side pin 605 of one of the PFC pin frames are arranged adjacent to each other on the portion outside the plastic package (i.e., the connection pin of the PFC drive-side pin 605), and the distance between them is greater than or equal to 5a. Further, in the first direction, the distance between the connection pins at the junction of the second inverter section and the PFC pins is 5a, or greater than 5a.

[0134] In other words, in the first direction, the distance between the connection pin closest to the plurality of second drive side pins among the plurality of first drive side pins and the connection pin closest to the plurality of first drive side pins among the plurality of second drive side pins is greater than or equal to 5a. Similarly, in the first direction, the distance between the connection pin closest to the plurality of PFC drive side pins among the plurality of second drive side pins and the connection pin closest to the plurality of second drive side pins among the plurality of PFC drive side pins is greater than or equal to 5a.

[0135] Furthermore, regarding the pin spacing design of the rectifier bridge, in some embodiments, the spacing between the two rectifier bridge driver-side pins is 5 times or more the spacing of other functional circuit pins. For example, when the spacing between two adjacent pins in a plurality of first driver-side pins, a plurality of second driver-side pins, and a plurality of PFC driver-side pins is equal and 'a', the spacing between the two rectifier bridge driver-side pins is less than or equal to 5a.

[0136] The above spacing design allows for more uniform stress distribution across the entire module, resulting in higher structural strength.

[0137] As can be seen from the attached figures, the first and second frames, as well as the PFC pin frame, in the drive-side frame can adopt an integrated architecture, reducing the number of solder joints between different frames and the structural strength reduction caused by component splicing. The two pins corresponding to the rectifier bridge are independently distributed compared to the integrated architecture of the first and second frames and the PFC pin frame. Therefore, the structural strength of the pin area corresponding to the rectifier bridge is relatively weaker than that of the areas of the first and second frames and the PFC pin frame. Increasing the pin width can enhance the structural strength in this area, making the stress distribution of the entire drive-side frame more uniform.

[0138] Furthermore, to ensure electrical isolation between different pins, a groove design is employed on the molding compound 700. By placing grooves between some adjacent pins, the surface current path between adjacent pins is lengthened, improving the creepage distance and clearance performance between adjacent pins, thereby enhancing the electrical isolation performance between pins. Specifically, for example... Figure 2 and Figure 10 As shown, the molding compound 700 has a first side 701 and a second side 702 that are disposed opposite to each other in the second direction. The first side 701 is the side that is closer to the drive side frame. A groove is provided on the first side 701 of the molding compound 700.

[0139] In some embodiments, a first groove 7031 is provided in the molding compound 700 between the PFC pin frame and the rectifier pin frame. The first groove 7031 is recessed into the molding compound 700 from the outer peripheral side along a second direction, and the first groove 7031 penetrates the molding compound 700 in a third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. The outer peripheral side and the upper and lower opposing surfaces enclose the molding compound 700. The first groove 7031 is provided in the molding compound 700 between the PFC pin frame and the rectifier pin frame, that is, the first groove 7031 is located between the adjacent third connection pin and the rectifier bridge drive side pin 606. Providing the first groove 7031 in the molding compound between the PFC pin frame and the rectifier pin frame can lengthen the surface current path between adjacent pins, improve the creepage distance and clearance performance between adjacent pins, thereby improving the electrical isolation performance between pins and improving the operational stability of the integrated semiconductor device.

[0140] In some embodiments, a second groove 7032 is provided in the molding compound 700 between the two rectifier bridge drive-side pins 606. The second groove 7032 is recessed into the molding compound 700 from the outer peripheral side along a second direction, and the second groove 7032 penetrates the molding compound 700 in a third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. Figure 10 As shown, the groove between pin 1 and pin 2.

[0141] In some embodiments, a third groove 7033 is provided in the molding compound 700 between the connection pins in the low-voltage pin area and the connection pins in the high-voltage pin area. The third groove 7033 is recessed into the molding compound 700 from the outer peripheral side along a second direction, and the third groove 7033 penetrates the molding compound 700 in a third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. For example, the third groove 7033 is the groove between pin 34 and pin 33, and the third groove 7033 is the groove between pin 16 and pin 15.

[0142] In some embodiments, at least one fourth groove 7034 is further provided on the side of the molding compound near the drive-side frame. The fourth groove 7034 is located between the bootstrap pins of adjacent groups. The fourth groove 7034 is recessed into the molding compound 700 from the outer peripheral side along a second direction, and the fourth groove 7034 penetrates the molding compound 700 in a third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. Examples include the groove between pin 13 and pin 14, the groove between pin 11 and pin 12, the groove between pin 31 and pin 32, and the groove between pin 29 and pin 30.

[0143] In some embodiments, at least one fifth groove 7035 is further provided on the side of the molding compound 700 near the drive-side frame. The fifth groove 7035 is located between one of the plurality of adjacent first drive-side pins 602 and one of the plurality of second drive-side pins 604. The fifth groove 7035 is recessed into the molding compound 700 from the outer peripheral side along a second direction, and the fifth groove 7035 penetrates the molding compound 700 in a third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. For example, a fifth groove is provided on the first side 701 between adjacent first and second connecting pins, and in the first direction, the fifth groove is spaced apart from at least one first dummy pin. For example, combined with Figure 10 and Figure 9 As shown, the fifth groove 7035 between pins 27 and 28 is offset or spaced from the third pseudo-ground pin P03 and the first high-side gate drive supply voltage pseudo-pin P04 in the first direction. It is worth mentioning that the grooves are all formed by the side of the molding compound 700 closer to the drive-side frame in the second direction, that is, by recessing from the first side edge 701 into the molding compound 700.

[0144] In one example, such as Figure 2 and Figure 9 As shown, a sixth groove 7036 is also provided on the side of the molding compound 700 near the drive-side frame. The sixth groove 7036 is located between adjacent third and second connection pins. The sixth groove 7036 is recessed into the molding compound 700 from the outer peripheral side along the second direction, and the sixth groove 7036 penetrates the molding compound 700 in the third direction, that is, it extends and penetrates in a direction parallel to the outer peripheral side. In one example, the sixth groove 7036 may also be located between adjacent third and second connection pins, that is, the groove between pin 10 and pin 9, spaced apart or offset from the second high-side gate drive supply voltage pseudo pin P05 and the fourth pseudo ground pin P06 in the first direction, and the sixth groove 7036 is closer to the second connection pin in the first direction than the second high-side gate drive supply voltage pseudo pin P05 and the fourth pseudo ground pin P06.

[0145] Optional, such as Figure 9 As shown, in some embodiments, the location where the groove needs to be formed may also include one or more of the following locations: between pin 34 and pin 33; between pin 32 and pin 31; between pin 30 and pin 29; between pin 16 and pin 15; between pin 14 and pin 13; between pin 12 and pin 11; between pin 3 and pin 2.

[0146] Figure 9 The groove shown is merely an exemplary solution, and those skilled in the art can adapt the number of grooves to suit actual needs. The groove design can further increase the electrical clearance between pins or other components or elements on both sides of the groove location, ensuring insulation and improving stability.

[0147] Furthermore, the semiconductor device proposed in some embodiments of this application is designed in terms of the pin width and pin spacing of the rectifier bridge 401 relative to other regions. It is worth noting that the pin width refers to the maximum width of the portion of the pin located outside the molding compound 700 in a first direction.

[0148] For example, in terms of pin width design, the width of each of the multiple first drive-side pins 602 and multiple second drive-side pins 604 is equal and is b1; the width of the rectifier bridge drive-side pin 606 is b2, and b2≥2b1.

[0149] For example, combined Figure 2 , Figure 5 and Figure 9 The rectifier bridge 401 corresponds to two rectifier bridge driver side pins 606, namely pin 2 and pin 1. For example, if the width of each of the multiple first driver side pins 602 (pins 45-28), multiple second driver side pins 604 (pins 27-10), and multiple PFC driver side pins 605 is equal, and the pin width is defined as b1, then the width of pin 2 and pin 1 is equal, and the width of pin 2 or pin 1 is defined as b2, where b2 ≥ 2b1. Figure 9 as well as Figure 2 In the example shown, b2 = 2b1; in other embodiments, b2 > 2b1.

[0150] Optionally, in some embodiments, the pin width of the multiple pins (pins 9-3) corresponding to the PFC module can be b1. In other embodiments, the pin width of pins 9-3 may not be equal to b1.

[0151] The design of the pin width and spacing of the rectifier bridge, compared to other areas, can enhance the stability of the overall semiconductor structure.

[0152] It should be noted that the embodiments listed above are merely illustrative examples, and various other implementation schemes can be obtained based on the above description. For example, the first inverter unit 101 can be applied to equipment such as a fan, and the second inverter unit can be applied to equipment such as a compressor. In other embodiments, an integrated scheme in which the first inverter unit 101 is applied to the compressor and the second inverter unit is applied to the fan can be obtained through adaptive modifications, and the positions of the inverter units of the fan and the compressor can be interchanged. In the embodiments listed above, the semiconductor device can sequentially integrate a power module consisting of a fan inverter unit, a compressor inverter unit, a PFC, and a rectifier bridge. In other embodiments, a power module can also sequentially integrate a compressor inverter unit, a fan inverter unit, a PFC, and a rectifier bridge. In this layout, the relative positions of the functional circuits are distributed as follows: Figure 11 As shown, the first inverter unit 101 is a compressor inverter unit, and the second inverter unit 201 is a fan inverter unit.

[0153] Or, such as Figure 12 As shown, in some other embodiments, the PFC may also be disposed between the first inverter section and the second inverter section.

[0154] Furthermore, it should be noted that the above embodiment is based on the integration of four parts: the first inverter section, the second inverter section, the power factor corrector 303, and the rectifier bridge 401. In practice, the integrated object can be at least two of the four parts. For example, as... Figure 13 As shown, at least the first inverter section 101 and the second inverter section 201 can be integrated. The power factor corrector 303 and the rectifier bridge 401 still use discrete devices, which is also a feasible solution. Compared with the design scheme in which all four parts use discrete devices, this solution still reduces the area occupied on the control board and the number of plug-in connections is also relatively reduced.

[0155] By adopting the above integration scheme, the long and short pins are distributed alternately, which can shorten the distance between two adjacent pins in the horizontal direction (first direction). At the same time, by lengthening the distance between two pins in the vertical direction (second direction), a certain electrical clearance distance can be provided between two adjacent pins. While shortening the horizontal distance, the electrical insulation effect between the pins can also be guaranteed, which is conducive to the miniaturization of the module and saves the occupied area.

[0156] In another aspect of this application, an electrical device is also provided, which includes the aforementioned semiconductor device. This electrical device can include household appliances such as electric fans, air conditioners, kitchen range hoods, high-speed hair dryers, washing machines, etc., and the semiconductor device can be used in the motor drive system of these household appliances. The electrical device can also be a new energy vehicle, industrial automation equipment, switching power supply, etc.

[0157] Semiconductor device 100 can be used in equipment such as air conditioners, taking air conditioners as an example.

[0158] The function of the rectifier bridge 401 in an air conditioner is to convert alternating current (AC) to direct current (DC). It is typically used in the power supply section to provide DC voltage to subsequent circuits such as power factor correction (PFC) and inverter sections. It includes diodes and other auxiliary components. For example, the rectifier bridge 401 includes four diodes. The input of the rectifier bridge is connected to the AC power supply, and its output is connected to the input of the power factor correction (PFC) unit.

[0159] A power factor corrector (PFC) is used to improve the power factor by bringing the current and voltage closer together in phase, reducing inefficient power. It includes power switching devices, such as insulated-gate bipolar transistors (IGBTs), to control the current waveform, and PFC diodes for rectification. It receives the DC voltage output from the rectifier bridge and, by controlling the current waveform, ensures that the input current and voltage are in phase, thereby improving the power factor and reducing inefficient power and harmonic interference. The DC voltage output by the PFC is typically boosted to a higher stable value (e.g., 400V DC) to supply power to the subsequent inverter section. The input of the PFC is connected to the output of the rectifier bridge, and the output is connected to the DC bus of the fan inverter and compressor inverter sections.

[0160] The fan inverter section is typically used to drive the indoor and outdoor fan motors of an air conditioner. It includes multiple power switching devices, such as IGBT modules or metal-oxide-semiconductor field-effect transistors (MOSFETs). The input of the fan inverter is connected to the DC bus (shared with the output of the PFC and the compressor inverter section). The output of the fan inverter is connected to the fan motor. The fan inverter converts DC power into variable-frequency AC power to drive the indoor and outdoor fan motors of the air conditioner, thereby controlling the fan speed.

[0161] The compressor inverter section drives the air conditioner compressor and has a relatively high power rating. It includes power switching devices, such as IGBT modules, which integrate multiple IGBTs and freewheeling diodes, or IGBT modules comprising multiple RC-IGBTs. The compressor inverter section is connected in parallel with the fan inverter section and also draws power from the DC bus. The input terminal of the compressor inverter section is connected to the DC bus, and the output terminal is connected to the compressor motor. The compressor inverter section converts DC power into AC power of a variable frequency to drive the air conditioner compressor motor. By controlling the power switching devices (such as IGBT modules) in the inverter section, the frequency and voltage of the output AC power are adjusted, thereby controlling the compressor speed and cooling / heating capacity. Since the electrical device of this application incorporates the aforementioned semiconductor device, it also possesses the advantages of such a semiconductor device.

[0162] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0163] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0164] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0165] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0166] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0167] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a first direction, a second direction, and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other, and the semiconductor device includes: substrate; The power factor corrector and the rectifier bridge are disposed adjacent to each other on the substrate and spaced apart in the first direction; A drive-side frame is disposed on the outside of the substrate and spaced apart from at least a portion of the substrate in the second direction. The drive-side frame includes a PFC pin frame and a rectifier pin frame spaced apart in the first direction. The PFC pin frame includes a plurality of PFC drive-side pins. The rectifier pin frame is electrically connected to the rectifier bridge. The PFC driver integrated circuit is disposed on the PFC pin frame and electrically connected to the power factor corrector; A molding compound is provided for encapsulating the substrate, the drive-side frame, the PFC driver integrated circuit, the power factor corrector, and the rectifier bridge, wherein at least partially, the plurality of PFC drive-side pins extend from the outer peripheral side of the molding compound. in, A first groove is provided in the molding compound between the PFC pin frame and the rectifier pin frame. The first groove is recessed into the molding compound from the outer peripheral side along the second direction, and the first groove penetrates the molding compound in the third direction.

2. The semiconductor device according to claim 1, characterized in that, The rectifier pin frame includes two rectifier bridge driver-side pins, at least a portion of which extends from the molding compound. A second groove is provided in the molding compound between the two rectifier bridge drive-side pins. The second groove is recessed into the molding compound from the outer peripheral side along the second direction, and the second groove penetrates the molding compound in the third direction.

3. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: A first inverter circuit element and a second inverter circuit element are disposed on the substrate. The first inverter circuit element, the second inverter circuit element, the power factor correction (PFC) converter, and the rectifier bridge are spaced apart from each other in a first direction. The rectifier bridge includes a rectifier chip and a rectifier bridge pad. The substrate has a first power side pad, a second power side pad, a PFC power side pad, and the rectifier bridge pad. The first inverter circuit element, the second inverter circuit element, the power factor correction (PFC) converter, and the rectifier chip are respectively disposed on the first power side pad, the second power side pad, the PFC power side pad, and the rectifier bridge pad. The drive-side frame also includes a first frame and a second frame. The first frame, the second frame, the PFC pin frame, and the rectifier pin frame are spaced apart from each other in a first direction. The first frame and the first power-side pad are at least partially corresponding in a second direction, the second frame and the second power-side pad are at least partially corresponding in a second direction, the PFC pin frame and the PFC power-side pad are at least partially corresponding in a second direction, the rectifier pin frame and the PFC power-side pad are at least partially corresponding in a second direction, the first frame includes a first driver-side pad and a plurality of first driver-side pins, the second frame includes a second driver-side pad and a plurality of second driver-side pins, the plurality of first driver-side pins and the plurality of second driver-side pins at least partially extend from the molding compound, and the portions of the plurality of first driver-side pins located outside the molding compound and the portions of the plurality of second driver-side pins located outside the molding compound have the same arrangement in the first direction.

4. The semiconductor device according to claim 3, characterized in that, Each of the plurality of first driving-side pins and the plurality of second driving-side pins has a low-voltage pin area and a high-voltage pin area spaced apart in a first direction. Each of the plurality of first driving-side pins and the plurality of second driving-side pins includes a plurality of connection pins and at least one pseudo-pin. The at least one pseudo-pin includes a first pseudo-ground pin, which is located in the low-voltage pin area. The first pseudo-ground pin divides the plurality of connection pins within each low-voltage pin area into: a first connection pin group and a second connection pin group located on either side of the first pseudo-ground pin, respectively. The spacing between any two adjacent connection pins within the first connection pin group is 'a'; and / or The spacing between any two adjacent connection pins within the second connection pin group is 'a'; and / or The minimum spacing between any two adjacent PFC driver-side pins in a plurality of PFC driver-side pins is a; and / or The spacing between two connection pins located on both sides of the first pseudo-ground pin and adjacent to the first pseudo-ground pin is greater than or equal to 2a.

5. The semiconductor device according to claim 4, characterized in that, Also includes: At least one bootstrap chip, The plurality of connection pins of the plurality of first driving side pins and the plurality of connection pins of the plurality of second driving side pins further include: a plurality of bootstrap pins, each of the bootstrap pins having a connection pin located outside the plastic package, the connection pins of the plurality of bootstrap pins being located within the high-voltage pin area, the plurality of bootstrap pins including at least one group of bootstrap pins, each group of bootstrap pins being electrically connected to its corresponding bootstrap chip, wherein the spacing between two adjacent connection pins in each group of bootstrap pins in the first direction is defined as 'a', and the minimum spacing between the connection pins of adjacent groups of bootstrap pins in the first direction is greater than or equal to 3a; and / or In the plurality of first driving side pins and the plurality of second driving side pins, the distance between the connection pin of the weak current pin area located outside the molded body and the connection pin of the strong current pin area located outside the molded body adjacent to it in the first direction is greater than or equal to 3a.

6. The semiconductor device according to claim 5, characterized in that, Also includes: A third groove is provided in the molding compound between the connection pins in the low-voltage pin area and the connection pins in the high-voltage pin area. The third groove is recessed into the molding compound from the outer peripheral side along the second direction, and the third groove penetrates the molding compound in the third direction; and / or At least one fourth groove is also provided on the side of the molding compound near the drive-side frame. The fourth groove is located between adjacent sets of bootstrap pins. The fourth groove is recessed into the molding compound from the outer peripheral side along the second direction, and penetrates the molding compound in the third direction; and / or At least one fifth groove is also provided on the side of the molding compound near the drive-side frame. The fifth groove is located between one of the connecting pins of a plurality of adjacent first drive-side pins and one of the connecting pins of a plurality of second drive-side pins. The fifth groove is recessed into the molding compound from the outer peripheral side along the second direction, and the fifth groove penetrates the molding compound in the third direction; and / or A sixth groove is provided on the side of the molding compound near the drive-side frame. The plurality of second drive-side pins include a plurality of second connection pins. The PFC drive-side pins include a plurality of third connection pins. The sixth groove is disposed between adjacent third connection pins and second connection pins. The sixth groove is recessed into the molding compound from the outer peripheral side along the second direction, and the sixth groove penetrates the molding compound in the third direction.

7. The semiconductor device according to claim 6, characterized in that, In the first direction, one of the plurality of first driving side pins is arranged adjacent to one of the plurality of second driving side pins, and the distance between them is greater than or equal to 5a; and / or In the first direction, the second frame and the PFC pin frame are arranged adjacent to each other, and a connection pin of one of the plurality of second drive side pins and a PFC drive side pin of the PFC pin frame are arranged adjacent to each other in the portion outside the plastic package, and the distance between them is greater than or equal to 5a.

8. The semiconductor device according to claim 7, characterized in that, The first connection pin group includes the following pins arranged sequentially and at intervals in the first direction: over-temperature protection pin, power ground pin, over-current protection pin, fault output port pin, low-side gate drive supply voltage pin, W2 phase low-side input signal pin, V2 phase low-side input signal pin and U2 phase low-side input signal pin; The second connection pin group includes the following pins arranged sequentially at intervals in the first direction: high-side gate drive power supply voltage pin, W2 phase high-side input signal pin, V2 phase high-side input signal pin, and U2 phase high-side input signal pin.

9. The semiconductor device according to claim 8, characterized in that, The first inverter circuit element is a fan inverter circuit element, and the second inverter circuit element is a compressor inverter circuit element. The plurality of connection pins located in the low-voltage pin area of ​​the plurality of first drive side pins include the following pins arranged sequentially and at intervals in the first direction: fan over-temperature protection pin, fan power ground pin, fan overcurrent protection pin, fan fault output port pin, fan low-side gate drive power supply voltage pin, fan W2 phase low-side input signal pin, fan V2 phase low-side input signal pin, fan U2 phase low-side input signal pin, fan high-side gate drive power supply voltage pin, fan W2 phase high-side input signal pin, fan V2 phase high-side input signal pin, and fan U2 phase high-side input signal pin; The multiple connection pins located in the high-voltage pin area among the multiple first drive side pins include the following pins arranged sequentially and at intervals in the first direction: wind turbine W2 phase high-side drive floating power supply voltage pin, wind turbine W2 phase high-side drive floating power supply ground pin, wind turbine V2 phase high-side drive floating power supply voltage pin, wind turbine V2 phase high-side drive floating power supply ground pin, wind turbine U2 phase high-side drive floating power supply voltage pin, and wind turbine U2 phase high-side drive floating power supply ground pin; The multiple connection pins located in the low-voltage pin area among the multiple second drive-side pins include the following pins arranged sequentially and at intervals in the first direction: compressor over-temperature protection pin, compressor power ground pin, compressor overcurrent protection pin, compressor fault output port pin, compressor low-side gate drive power supply voltage pin, compressor W1 phase low-side input signal pin, compressor V1 phase low-side input signal pin, compressor U1 phase low-side input signal pin, compressor high-side gate drive power supply voltage pin, compressor W1 phase high-side input signal pin, compressor V1 phase high-side input signal pin, and compressor U1 phase high-side input signal pin; The plurality of connection pins located in the high-voltage pin area of ​​the plurality of second drive side pins include the following pins arranged sequentially and at intervals in the first direction: compressor W1 phase high-side drive floating power supply voltage pin, compressor W1 phase high-side drive floating power supply ground pin, compressor V1 phase high-side drive floating power supply voltage pin, compressor V1 phase high-side drive floating power supply ground pin, compressor U1 phase high-side drive floating power supply voltage pin, and compressor U1 phase high-side drive floating power supply ground pin; The multiple connection pins among the multiple PFC driver side pins include the following pins arranged sequentially and at intervals in the first direction: PFC driver IC power supply voltage pin, PFC power ground pin, enable I / O function pin, PFC input signal pin, current detection input pin, temperature sensor connector 2 pin, and temperature sensor connector 1 pin.

10. An electrical appliance, characterized in that, The semiconductor device includes any one of claims 1-9.

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