Semiconductor structure including bonding conductors with protrusions

Abstract

This invention provides a semiconductor structure including a semiconductor substrate, an interconnect structure, and a bonding structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes interconnect wiring distributed on the top surface of the interconnect structure. The bonding structure is disposed on and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor. The bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor is located on the top surface of the interconnect wiring and a first sidewall of the interconnect wiring.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor structure including a bonding conductor with protrusions. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integrated density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, these improvements in integrated density stem from iterative reductions in the smallest feature size, allowing more components to be integrated into a given area. Recent growth in demands for miniaturization, higher speeds and bandwidths, as well as lower power consumption and latency, has created a need for smaller and more innovative semiconductor die packaging technologies. Currently, System-on-Integrated-Circuit (SoIC) components are becoming increasingly popular due to their versatility and compactness. However, SoIC components present reliability challenges. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor substrate, an interconnect structure, and a bonding structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes interconnect wiring distributed on a top surface of the interconnect structure. The bonding structure is disposed on the interconnect structure and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor. The bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor sits on the top surface of the interconnect wiring and a first sidewall of the interconnect wiring.

[0004] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor die and a bonding structure. The semiconductor die includes interconnect wiring of an interconnect structure. The bonding structure is disposed on and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor embedded in the bonding dielectric structure. The bonding dielectric structure is disposed on a top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor sits on the top surface of the interconnect wiring and on a first inclined sidewall of the interconnect wiring, and the bonding dielectric structure contacts a second inclined sidewall of the interconnect wiring, the first inclined sidewall of the interconnect wiring extending from the top surface of the interconnect wiring to the second inclined sidewall of the interconnect wiring, and the second inclined sidewall of the interconnect wiring being steeper than the first inclined sidewall of the interconnect wiring.

[0005] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor die and a bonding structure. The semiconductor die includes interconnect wiring. The bonding structure is disposed on the interconnect wiring and electrically connected to the interconnect wiring. The bonding structure includes a bonding dielectric structure disposed on the top surface of the semiconductor die and covering the interconnect wiring; and a bonding conductor embedded in the bonding dielectric structure, wherein the bonding conductor sits on the top surface of the interconnect wiring, and the bonding conductor includes a first protrusion that laterally covers a first sidewall of the interconnect wiring. Attached Figure Description

[0006] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic cross-sectional view of the semiconductor structure of the SoIC component according to the first embodiment of this disclosure is shown.

[0008] Figure 2 A cross-sectional view of a semiconductor structure according to a second embodiment of this disclosure is schematically illustrated.

[0009] Figures 3A to 3D A top view of interconnecting wiring and bonding conductors according to an embodiment of this disclosure is schematically illustrated.

[0010] Figure 4 A cross-sectional view of a semiconductor structure according to a third embodiment of this disclosure is schematically illustrated.

[0011] Figures 5A to 5D A top view of interconnecting wiring and bonding conductors is schematically illustrated according to other embodiments of this disclosure.

[0012] Figures 6A to 6D A top view of interconnecting wiring and bonding conductors is schematically illustrated according to another embodiment of this disclosure.

[0013] Figures 7A to 7D A top view of interconnect wiring and bonding conductors according to an alternative embodiment of this disclosure is schematically illustrated.

[0014] Figure 8 A cross-sectional view of a semiconductor structure according to a fourth embodiment of this disclosure is schematically illustrated.

[0015] Figure 9 A cross-sectional view of a semiconductor structure according to a fifth embodiment of this disclosure is schematically illustrated.

[0016] Figure 10 A cross-sectional view of a semiconductor structure according to a sixth embodiment of this disclosure is schematically illustrated.

[0017] Figure 11 A cross-sectional view of a semiconductor structure according to a seventh embodiment of this disclosure is schematically illustrated.

[0018] Figure 12 A cross-sectional view of a semiconductor structure according to the eighth embodiment of this disclosure is schematically illustrated.

[0019] Figure 13 A cross-sectional view of a semiconductor structure according to the ninth embodiment of this disclosure is schematically illustrated.

[0020] Figure 14 A cross-sectional view of a semiconductor structure according to the tenth embodiment of this disclosure is schematically illustrated.

[0021] Figure 15 A cross-sectional view of a semiconductor structure according to the eleventh embodiment of this disclosure is schematically illustrated. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are provided to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, or embodiments where other features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters are repeated in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or architectures discussed.

[0023] Furthermore, for ease of explanation, spatially relative terms such as “benefit,” “below,” “lower,” “above,” and “upper” are used throughout this document to indicate the relationship between one component or feature and another. These spatially relative terms are intended to cover different orientations of components in use, or operations other than those depicted in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative terms used herein will be interpreted accordingly.

[0024] Numerical values ​​in this disclosure and claims should be understood to include values ​​that remain the same when reduced to the same number of significant figures, as well as values ​​that differ from those determined by experimental errors less than those determined by conventional measurement techniques of the type described in this disclosure. All scopes of this disclosure include the endpoints of the numerical values.

[0025] Figure 1 A schematic cross-sectional view of the semiconductor structure of the SoIC component according to the first embodiment of this disclosure is shown.

[0026] Reference Figure 1 The upper half of the diagram illustrates a SoIC component 100. This SoIC component 100 includes a semiconductor structure 110A, an insulating encapsulation 120, a semiconductor die 130, an insulating encapsulation 140, a bonding structure 150, a redistribution circuit structure 160, and conductive terminals 170. The semiconductor structure 110A is laterally encapsulated by the insulating encapsulation 120, wherein the top surface of the semiconductor structure 110A is substantially flush with the top surface of the insulating encapsulation 120, and the bottom surface of the semiconductor structure 110A is substantially flush with the bottom surface of the insulating encapsulation 120. The insulating encapsulation 120 may be a gap-filling dielectric material (e.g., an oxide material formed from tetraethoxysilane (TEOS) or other suitable dielectric material) formed by a deposition process (e.g., chemical vapor deposition, physical vapor deposition, or other suitable deposition process), followed by a planarization process (e.g., mechanical polishing, chemical mechanical polishing, combinations thereof, or other suitable removal processes). Alternatively, the insulating encapsulation 120 may be a molding compound formed by a molding process or other suitable process. The semiconductor die 130 is laterally encapsulated by the insulating encapsulation 140, wherein the top surface of the semiconductor die 130 is substantially flush with the top surface of the insulating encapsulation 140, and the bottom surface of the semiconductor die 130 is substantially flush with the bottom surface of the insulating encapsulation 140. A bonding structure 150 is disposed on the bottom surface of the semiconductor die 130 and the bottom surface of the insulating encapsulation 140, and the bonding structure 150 is electrically connected to the semiconductor die 130. For example, the bonding structure 150 is electrically connected to a semiconductor via (TSV) 132 in the semiconductor die 130. The semiconductor die 130 is electrically connected to the semiconductor structure 110A via the bonding structure 150. A redistribution circuit structure 160 is disposed on and electrically connected to the semiconductor die 130, and a conductive terminal 170 is disposed on and electrically connected to the redistribution circuit structure 160. In other words, the conductive terminal 170 is electrically connected to the semiconductor die 130 via the redistribution circuit structure 160.

[0027] like Figure 1As shown in the upper portion, the sidewalls of the insulating encapsulation 120 are substantially aligned with the sidewalls of the insulating encapsulation 140, the sidewalls of the bonding structure 150, and the sidewalls of the redistribution circuit structure 160. The insulating encapsulation 120 is spaced apart from the insulating encapsulation 140 by the bonding structure 150. The bonding structure 150 may include a bonding dielectric structure 152 and a bonding conductor 154 embedded in the bonding dielectric structure 152. In some embodiments, the bonding dielectric structure 152 is a single-layer dielectric structure. In some alternative embodiments, the bonding dielectric structure 152 is a multilayer structure including stacked dielectric layers. Furthermore, the bonding conductor 154 may be or include a bonding conductive via embedded in the bonding dielectric structure 152.

[0028] In some alternative embodiments not shown in the figures, the insulating encapsulation 140 may be omitted. In other words, the sidewalls of the semiconductor die 130 may be substantially aligned with the sidewalls of the insulating encapsulation 120, the sidewalls of the bonding structure 150, and the sidewalls of the redistribution circuit structure 160.

[0029] In the first embodiment disclosed herein, the semiconductor structure 110A includes a semiconductor substrate 112, an interconnect structure 114, and a bonding structure 116. Here, the semiconductor substrate 112 and the interconnect structure 114 are referred to as semiconductor grains. Figure 1 As shown in the upper portion, an interconnect structure 114 is disposed on a semiconductor substrate 112. The interconnect structure 114 includes interconnect wiring 114A distributed on its top surface 114B. The semiconductor substrate 112 may include a silicon substrate in which active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors, or the like) are formed. The active and passive components are formed in the semiconductor substrate 112 by a front-end semiconductor wafer process (FEOL) step. The interconnect structure 114 may include alternating stacks of multilayer interconnect wiring 114A (e.g., copper interconnect wiring) and multilayer dielectric layers, wherein the interconnect wiring 114A of the interconnect structure 114 is electrically connected to the active and / or passive components in the semiconductor substrate 112. The interconnect structure 114 is formed by a back-end semiconductor wafer process (BEOL) step. The topmost interconnect wiring 114A may be or include conductive pads. Figure 1 In the embodiment shown, the interconnect wiring 114A is an aluminum interconnect wiring or a copper-doped aluminum pad.

[0030] A bonding structure 116 is disposed on and electrically connected to an interconnect structure 114. The bonding structure 116 includes a bonding dielectric structure 116A and a bonding conductor 116B. The bonding dielectric structure 116A is disposed on the top surface 114B of the interconnect structure 114 and covers the interconnect wiring 114A of the interconnect structure 114. The bonding conductor 116B of the bonding structure 116 is embedded in the bonding dielectric structure 116A of the bonding structure 116, wherein the bonding conductor 116B sits on the top surface 114A2 of the interconnect wiring 114A and the first sidewall 114A1 of the interconnect wiring 114A. Figure 1 As shown, the bonding conductor 116B is disposed on the top surface 114A2 and the first sidewall 114A1 of the interconnect wiring 114A, and the bonding conductor 116B is in contact with the top surface 114A2 and the first sidewall 114A1 of the interconnect wiring 114A. The material of the bonding dielectric structure 116A may be silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic dielectric materials. The material of the bonding conductor 116B may be copper or other suitable conductive materials.

[0031] like Figure 1 As shown, the bonding conductor 116B in the semiconductor structure 110A includes a body portion 116B1 and a first protrusion 116B2. The body portion 116B1 is embedded in the bonding dielectric structure 116A, and the first protrusion 116B2 is embedded in the bonding dielectric structure 116A. The protrusion 116B2 extends downward from the bottom of the body portion 116B1 to cover the upper part of the first sidewall 114A1 of the interconnect wiring 114A. In other words, the protrusion 116B2 laterally covers and contacts the first sidewall 114A1 of the interconnect wiring 114A. Furthermore, the first protrusion 116B2 is spaced apart from the top surface 114B of the interconnect structure 114 by a distance D2.

[0032] In semiconductor structure 110A, bonding conductor 116B contacts and bonds with bonding conductor 154 of bonding structure 150. The bonding interface between bonding structure 116A and bonding structure 150 includes a metal-to-metal bonding interface and a dielectric-to-dielectric bonding interface, wherein the metal-to-metal bonding interface is located between bonding conductor 116B and bonding conductor 154, and the dielectric-to-dielectric bonding interface is located between bonding dielectric structure 116A and bonding dielectric structure 152, and between insulating encapsulator 120 and bonding dielectric structure 152.

[0033] like Figure 1As shown, the thickness D1 of the interconnect wiring 114A ranges from about 0.1 micrometers to about 100 micrometers, the remaining thickness D2 of the bonding dielectric structure 116A below the first protrusion 116B2 ranges from about 0.1 micrometers to about 100 micrometers, the bottom dimension D3 of the body portion 116B1 ranges from about 0.1 micrometers to about 100 micrometers, and the lateral dimension D4 of the recessed portion of the top surface 114A2 covered by the body portion 116B1 ranges from about 0.1 micrometers to about 100 micrometers. The thickness D1 of the interconnect wiring 114A is greater than the remaining thickness D2 of the bonding dielectric structure 116A, and the bottom dimension D3 of the body portion 116B1 is greater than the lateral dimension D4 of the recessed portion of the top surface 114A2 covered by the body portion 116B1.

[0034] In some embodiments, the thickness D1 of the interconnect wiring 114A may be about 28 micrometers, and the remaining thickness D2 of the bonding dielectric structure 116A may be greater than about 0.01 micrometers. The difference between the thickness D1 of the interconnect wiring 114A and the remaining thickness D2 of the bonding dielectric structure 116A may be greater than about 1 angstrom. The ratio of the remaining thickness D2 of the bonding dielectric structure 116A to the thickness D1 of the interconnect wiring 114A may range from about 0.01 to about 0.99, preferably about 0.05. The difference between the bottom dimension D3 of the body portion 116B1 and the lateral dimension D4 of the recessed portion of the top surface 114A2 (i.e., the maximum lateral dimension or top dimension of the first protrusion 116B2) may be greater than about 0.1 micrometers. The ratio of the lateral dimension D4 of the portion of the top surface 114A2 to the bottom dimension D3 of the body portion 116B1 may range from about 0.11 to about 0.99, preferably from about 0.11 to about 0.70.

[0035] like Figure 1 As shown, a deliberate offset (i.e., offset (D4-D3)) is obtained between the body portion 116B1 and the interconnect wiring 114A according to design rules, thereby increasing the contact area between the body portion 116B1 and the interconnect wiring 114A. In other words, due to the contact between the body portion 116B1 and the recessed portion of the top surface 114A2 and the first sidewall 114A1 of the interconnect wiring 114A, the contact area between the body portion 116B1 and the interconnect wiring 114A can be increased without significantly increasing the overall layout area of ​​the body portion 116B1 and the interconnect wiring 114A. Therefore, due to the increased contact area between the body portion 116B1 and the interconnect wiring 114A, the contact resistance between the body portion 116B1 and the interconnect wiring 114A can be minimized.

[0036] Figure 2 A schematic cross-sectional view illustrating a semiconductor structure according to a second embodiment of this disclosure.

[0037] Reference Figure 1 and Figure 2 , Figure 2 The semiconductor structure 110B shown is... Figure 1 Similar to the semiconductor structure 110A shown, except... Figure 2 The bonding dielectric structure 116A of the bonding structure 116 shown is a multilayer dielectric structure. In the second embodiment disclosed herein, the bonding dielectric structure 116A includes a first dielectric layer 116A1, a second dielectric layer 116A2, and an etch stop layer 116A3. The first dielectric layer 116A1 is disposed on the top surface 114B of the interconnect structure 114, and the first dielectric layer 116A1 covers the interconnect wiring 114A. The second dielectric layer 116A2 is disposed above the first dielectric layer 116A1. The etch stop layer 116A3 is disposed between the first dielectric layer 116A1 and the second dielectric layer 116A2. The bonding conductor 116B is embedded in and passes through the first dielectric layer 116A1, the etch stop layer 116A3, and the second dielectric layer 116A2.

[0038] Due to the etch stop layer 116A3 formed between the first dielectric layer 116A1 and the second dielectric layer 116A2, the bonding conductor 116B includes a bottom portion 116B1', a first protrusion 116B2, and a top portion 116B3. The top portion 116B3 is wider than the bottom portion 116B1'. Figure 2 As shown, the bottom portion 116B1' of the bonding conductor 116B is embedded and contacts the first dielectric layer 116A1 and the etch stop layer 116A3. The first protrusion 116B2 of the bonding conductor 116B is embedded and contacts the first dielectric layer 116A1. The top portion 116B3 of the bonding conductor 116B is embedded and contacts the second dielectric layer 116A2. The top portion 116B3 covers the top surface of the etch stop layer 116A3. The first protrusion 116B2 extends from the bottom of the bottom portion 116B1' to cover the first sidewall 114A1 of the interconnect wiring 114A.

[0039] In some embodiments, the bottom portion 116B1' includes a first bottom dimension D3 and a first top dimension D5, and the top portion 116B3 includes a second bottom dimension D6 and a second top dimension D7. The first top dimension D5 of the bottom portion 116B1' is greater than the first bottom dimension D3 of the bottom portion 116B1', the second top dimension D7 of the top portion 116B3 is greater than the second bottom dimension D6 of the top portion 116B3, and the second bottom dimension D6 of the top portion 116B3 is greater than the first top dimension D5 of the bottom portion 116B1'.

[0040] Figures 3A to 3D A schematic top view illustrating interconnect wiring and bonding conductors according to an embodiment of this disclosure.

[0041] Reference Figures 3A to 3D Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B sits on and overlaps with the interconnect wiring 114A, and the first protrusion 116B2 of the bonding conductor 116B leans against the first sidewall 114A1 of the interconnect wiring 114A. Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B has a circular outline (as shown in the image). Figure 3A As shown), elliptical outline (as shown) Figure 3B (as shown), a rectangular or square outline with or without rounded corners (e.g.) Figure 3C (as shown) or hexagonal outline (such as) Figure 3D (As shown).

[0042] Figure 4 A schematic cross-sectional view illustrating a semiconductor structure according to a third embodiment of this disclosure. Figures 5A to 5D A schematic top view illustrating interconnect wiring and bonding conductors according to other embodiments of this disclosure.

[0043] Reference Figure 4 In the third embodiment disclosed herein, the semiconductor structure 110C includes a semiconductor substrate 112, an interconnect structure 114, and a bonding structure 116. Here, the semiconductor substrate 112 and the interconnect structure 114 are referred to as semiconductor dies. The interconnect structure 114 is disposed on the semiconductor substrate 112, such as... Figure 1 The upper part is shown. Interconnect structure 114 includes interconnect wiring 114A distributed on the top surface 114B of interconnect structure 114. Semiconductor substrate 112 may be a silicon substrate in which active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors or the like) are formed. Active and passive components are formed in semiconductor substrate 112 by front-end process (FEOL) steps of semiconductor wafer. Interconnect structure 114 may include multiple layers of interconnect wiring (e.g., copper interconnect wiring) and multiple layers of dielectric layers stacked alternately, wherein the interconnect wiring of interconnect structure 114 is electrically connected to active and / or passive components in semiconductor substrate 112. Interconnect structure 114 is formed by back-end process (BEOL) steps of semiconductor wafer. The topmost interconnect wiring 114A may be or include conductive pads. Figure 1 In the embodiment shown, the interconnect wiring 114A is an aluminum interconnect wiring or a copper-doped aluminum pad.

[0044] A bonding structure 116 is disposed on and electrically connected to an interconnect structure 114. The bonding structure 116 includes a bonding dielectric structure 116A and a bonding conductor 116B. The bonding dielectric structure 116A is disposed on the top surface 114B of the interconnect structure 114 and covers the interconnect wiring 114A of the interconnect structure 114. The bonding conductor 116B of the bonding structure 116 is embedded in the bonding dielectric structure 116A of the bonding structure 116, wherein the bonding conductor 116B is located on a first sidewall 114A1, a top surface 114A2, and a second sidewall 114A3 of the interconnect wiring 114A. Figure 4 As shown, the bonding conductor 116B is disposed on the top surface 114A2, the first sidewall 114A1, and the second sidewall 114A3 of the interconnect wiring 114A, and the bonding conductor 116B is in contact with the top surface 114A2, the first sidewall 114A1, and the second sidewall 114A3 of the interconnect wiring 114A. The material of the bonding dielectric structure 116A may be or include silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic dielectric materials. The material of the bonding conductor 116B may be or include copper or other suitable conductive materials.

[0045] like Figure 4As shown, the bonding conductor 116B includes a bottom portion 116B1', a first protrusion 116B2, a top portion 116B3, and a second protrusion 116B4. The top portion 116B3 is wider than the bottom portion 116B1'. The bottom portion 116B1' of the bonding conductor 116B is embedded in and in contact with the first dielectric layer 116A1 and the etch stop layer 116A3. The first protrusion 116B2 of the bonding conductor 116B is embedded in and in contact with the first dielectric layer 116A1. The top portion 116B3 of the bonding conductor 116B is embedded in and in contact with the second dielectric layer 116A2. The second protrusion 116B4 of the bonding conductor 116B is embedded in and in contact with the first dielectric layer 116A1. The second sidewall 114A3 is opposite to the first sidewall 114A1. The first protrusion 116B2 and the second protrusion 116B4 are located on opposite sides of the interconnect wiring 114A. The top portion 116B3 covers the top surface of the etch stop layer 116A3. The first protrusion 116B2 extends downward from the bottom of the bottom portion 116B1' to cover the upper portion of the first sidewall 114A1 of the interconnect wiring 114A. The second protrusion 116B4 extends downward from the bottom of the bottom portion 116B1' to cover the upper portion of the second sidewall 114A3 of the interconnect wiring 114A. Furthermore, both the first protrusion 116B2 and the second protrusion 116B4 are spaced apart from the top surface 114B of the interconnect structure 114.

[0046] like Figure 4 As shown, the thickness D1 of the interconnect wiring 114A can range from about 0.1 micrometers to about 100 micrometers; the remaining thickness D2 of the bonding dielectric structure 116A located below the first protrusion 116B2 or the second protrusion 116B4 can range from about 0.1 micrometers to about 100 micrometers; the bottom dimension D3 of the body portion 116B1 can range from about 0.1 micrometers to about 100 micrometers; and the lateral dimension D4 of the top surface 114A2 covered by the body portion 116B1 can range from about 0.1 micrometers to about 100 micrometers. The thickness D1 of the interconnect wiring 114A is greater than the remaining thickness D2 of the bonding dielectric structure 116A, and the bottom dimension D3 of the body portion 116B1 is greater than the lateral dimension D4 of the top surface 114A2 covered by the body portion 116B1.

[0047] In some embodiments, the thickness D1 of the interconnect wiring 114A may be about 28 micrometers, and the remaining thickness D2 of the bonding dielectric structure 116A may be greater than about 0.01 micrometers. The difference between the thickness D1 of the interconnect wiring 114A and the remaining thickness D2 of the bonding dielectric structure 116A may be greater than about 1 angstrom. The ratio of the remaining thickness D2 of the bonding dielectric structure 116A to the thickness D1 of the interconnect wiring 114A may be in the range of about 0.01 to about 0.99, preferably about 0.05. Half of the difference between the bottom dimension D3 of the body portion 116B1 and the lateral dimension D4 of the top surface 114A2 (i.e., the maximum lateral dimension or top dimension of the first protrusion 116B2 or the second protrusion 116B4) may be greater than about 0.1 micrometers. The ratio of the lateral dimension D4 of the top surface 114A2 to the bottom dimension D3 of the body portion 116B1 can be in the range of about 0.11 to about 0.99, preferably from about 0.11 to about 0.70.

[0048] like Figure 4 As shown, the deliberate overlap between the body portion 116B1 and the interconnect wiring 114A is based on design rules that allow for an increase in the contact area between them. In other words, because the body portion 116B1 is in actual contact with the top surface 114A2, the first sidewall 114A1 of the interconnect wiring 114A, and the second sidewall 114A3, the contact area between the body portion 116B1 and the interconnect wiring 114A can be increased without significantly increasing the overall layout area of ​​the body portion 116B1 and the interconnect wiring 114A. Therefore, due to the increased contact area between the body portion 116B1 and the interconnect wiring 114A, the contact resistance between them can be minimized.

[0049] like Figure 4 As shown, the bonding dielectric structure 116A is a multilayer dielectric structure, with a bonding conductor 116B having two protrusions 116B2 and 116B4 embedded within the bonding dielectric structure 116A. In some alternative embodiments, not shown in the figures, the bonding dielectric structure is a single-layer dielectric structure, similar to... Figure 1 The bonding dielectric structure shown has a bonding conductor with two protrusions embedded in a single-layer bonding dielectric structure.

[0050] Reference Figures 5A to 5DViewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B sits on and overlaps with the branch portion of the interconnect wiring 114A. The first protrusion 116B2 of the bonding conductor 116B rests against the first sidewall 114A1 of the branch portion of the interconnect wiring 114A, and the second protrusion 116B4 of the bonding conductor 116B rests against the third sidewall 114A2' of the branch portion of the interconnect wiring 114A. Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B has a circular outline (e.g., ...). Figure 5A As shown), elliptical outline (as shown) Figure 5B (as shown), rectangular or square outlines with or without rounded corners (e.g.) Figure 5C (as shown) or hexagonal outline (such as) Figure 5D (As shown). For example, the linewidth D8 of the branch portion of interconnect wiring 114A is greater than 0.01 micrometers. In some embodiments, the linewidth D8 of the branch portion of interconnect wiring 114A is approximately 50% of the bottom dimension D3 of the body portion 116B1 (e.g. Figure 4 (As shown).

[0051] Figures 6A to 6D A top view schematically illustrating an interconnect wiring and bonding conductor according to another embodiment of this disclosure.

[0052] Reference Figures 6A to 6D Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B sits on the end of the interconnect wiring 114A and overlaps with it. The protrusion 116B2 of the bonding conductor 116B rests against the first sidewall 114A1, the third sidewall 114A2', and the second sidewall 114A3 of the branch portion of the interconnect wiring 114A. The third sidewall 114A2' is adjacent to the first sidewall 114A1 and the second sidewall 114A3, and the second sidewall 114A3 is opposite to the first sidewall 114A1. The bonding conductor 116B sits on two adjacent corners of the branch portion of the interconnect wiring 114A. Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B has a circular outline (e.g., ...). Figure 6A As shown), elliptical outline (as shown) Figure 6B (as shown), rectangular or square outlines with or without rounded corners (e.g.) Figure 6C (as shown) or hexagonal outline (such as) Figure 6D (As shown). For example, the linewidth D8 of the branch portion of interconnect wiring 114A is greater than 0.01 micrometers. In some embodiments, the linewidth D8 of the branch portion of interconnect wiring 114A is approximately 50% of the bottom dimension D3 of the body portion 116B1 (e.g. Figure 4 (As shown).

[0053] Figures 7A to 7D A top view schematically illustrating an alternative embodiment of the interconnect wiring and bonding conductors according to this disclosure.

[0054] Reference Figures 7A to 7D Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B is situated at a corner of the interconnect wiring 114A and overlaps with the interconnect wiring 114A. The protrusion 116B2 of the bonding conductor 116B rests against the first sidewall 114A1 and the third sidewall 114A2' of the interconnect wiring 114A. The third sidewall 114A2' is adjacent to the first sidewall 114A1, and the third sidewall 114A2' intersects the first sidewall 114A1 at a corner. Viewed from the top of the bonding conductor 116B and the interconnect wiring 114A, the bonding conductor 116B has a circular outline (e.g., ...). Figure 7A As shown), elliptical outline (as shown) Figure 7B (as shown), rectangular or square outlines with or without rounded corners (e.g.) Figure 7C (as shown) or hexagonal outline (such as) Figure 7D (As shown).

[0055] Figure 8 A cross-sectional view of a semiconductor structure according to a fourth embodiment of the present disclosure is shown schematically.

[0056] Reference Figure 2 and Figure 8 , Figure 8 The semiconductor structure 110D shown is... Figure 2 Similar to the semiconductor structure 110B shown, except that the bonding conductor 116B is located on the top surface 114A2 of the interconnect wiring 114A and the first inclined sidewall 114A1 of the interconnect wiring 114A, the first dielectric layer 116A1 of the bonding dielectric structure 116A is in solid contact with the second inclined sidewall 114A5 of the interconnect wiring 114A, the first inclined sidewall 114A1 of the interconnect wiring 114A extends from the top surface 114A2 of the interconnect wiring 114A to the second inclined sidewall 114A5 of the interconnect wiring 114A, and the second inclined sidewall 114A5 of the interconnect wiring 114A is steeper than the first inclined sidewall 114A1 of the interconnect wiring 114A. For example, the angle T1 between the normal of the top surface 114B of the interconnect structure 114 and the second inclined sidewall 114A5 ranges from about 0.01 degrees to about 80 degrees, and the angle T2 between the normal of the top surface 114B of the interconnect structure 114 and the first inclined sidewall 114A1 ranges from about 0.01 degrees to about 80 degrees, and the angle T2 is greater than the angle T1.

[0057] Furthermore, at least one barrier layer 118 may be selectively formed on the top surface 114A2 of the interconnect wiring 114A, and at least one barrier layer 118 may be selectively formed between the top surface 114A2 of the interconnect wiring 114A and the first dielectric layer 116A1 of the bonding dielectric structure 116A. For example, the material of the barrier layer 118 may be or include tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0058] It should be noted that, Figures 3A to 3D , Figures 5A to 5D , Figures 6A to 6D as well as Figures 7A to 7D The shape of the bonding conductor 116B shown and the overlap between the bonding conductor 116B and the interconnect wiring 114A can be applied to the fourth embodiment of this disclosure.

[0059] Figure 9 A cross-sectional view of a semiconductor structure according to a fifth embodiment of this disclosure is shown schematically.

[0060] Reference Figure 2 and Figure 9 , Figure 9 The semiconductor structure 110E shown is... Figure 2 Similar to the semiconductor structure 110B shown, except that the bonding conductor 116B is situated on the top surface 114A2, the first inclined sidewall 114A1, and the inclined surface 114A6 of the interconnect wiring 114A, and the first dielectric layer 116A1 of the bonding dielectric structure 116A is in solid contact with the second inclined sidewall 114A5 of the interconnect wiring 114A. In this embodiment, the inclined surface 114A6 of the interconnect wiring 114A extends from the top surface 114A2 of the interconnect wiring 114A to the first inclined sidewall 114A1 of the interconnect wiring 114A, and the first inclined sidewall 114A1 of the interconnect wiring 114A is steeper than the inclined surface 114A6 of the interconnect wiring 114A. For example, the angle T1 between the normal of the top surface 114B of the interconnect structure 114 and the second inclined sidewall 114A5 ranges from about 0.01 degrees to about 80 degrees, the angle T2 between the normal of the top surface 114B of the interconnect structure 114 and the first inclined sidewall 114A1 ranges from about 0.01 degrees to about 80 degrees, and the angle T3 between the normal of the top surface 114B of the interconnect structure 114 and the inclined surface 114A6 ranges from about 0.01 degrees to about 80 degrees, wherein the angle T3 is greater than the angle T2, and the angle T2 is greater than the angle T1.

[0061] Furthermore, at least one barrier layer 118 may be selectively formed on the top surface 114A2 of the interconnect wiring 114A, and at least one barrier layer 118 may be selectively formed between the top surface 114A2 of the interconnect wiring 114A and the first dielectric layer 116A1 of the bonding dielectric structure 116A. For example, the material of the barrier layer 118 may be or include tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0062] It should be noted that Figures 3A to 3D , Figures 5A to 5D , Figures 6A to 6D and Figures 7A to 7D The shape of the bonding conductor 116B shown and the overlap between the bonding conductor 116B and the interconnect wiring 114A can be applied to the fifth embodiment of this disclosure.

[0063] Figure 10 A cross-sectional view of a semiconductor structure according to a sixth embodiment of this disclosure is shown schematically.

[0064] Reference Figure 1 and Figure 10 , Figure 10 The semiconductor structure 110F shown is... Figure 1 The semiconductor structure 110A shown is similar, except that the topmost interconnect wiring 114A of the interconnect structure 114 is a copper interconnect wiring or a copper pad.

[0065] Figure 11 A cross-sectional view of a semiconductor structure according to the seventh embodiment of this disclosure is shown schematically.

[0066] Reference Figure 2 and Figure 11 , Figure 11 The semiconductor structure 110G shown is... Figure 2 The semiconductor structure 110B shown is similar, except that the topmost interconnect wiring 114A of the interconnect structure 114 is a copper interconnect wiring or a copper pad.

[0067] Figure 12 A cross-sectional view of a semiconductor structure according to the eighth embodiment of this disclosure is shown schematically.

[0068] Reference Figure 1 and Figure 12 , Figure 12 The semiconductor structure 110H shown is... Figure 1Similar to the semiconductor structure 110A shown, except that the topmost interconnect 114A of the interconnect structure 114 is a copper interconnect or copper pad, a top barrier layer 118 and a bottom barrier layer 119 are also formed to protect the interconnect 114A. The top barrier layer 118 is formed to cover the top surface 114A2 of the interconnect 114A, and the bottom barrier layer 119 is formed to cover the top surface 114B of the interconnect structure 114. The top barrier layer 118 is formed between the bonding dielectric structure 116A and the top surface 114A2 of the interconnect 114A. The bottom barrier layer 119 is formed between the passivation layer 114C of the interconnect structure 114 and the interconnect 114A. Furthermore, the materials of the top barrier layer 118 and the bottom barrier layer 119 may be tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0069] Figure 13 A cross-sectional view of a semiconductor structure according to the ninth embodiment of this disclosure is schematically illustrated.

[0070] Reference Figure 2 and Figure 13 , Figure 13 The semiconductor structure 110I shown is... Figure 2 Similar to the semiconductor structure 110B shown, except that the topmost interconnect 114A of the interconnect structure 114 is a copper interconnect or copper pad, a top barrier layer 118 and a bottom barrier layer 119 are also formed to protect the interconnect 114A. The top barrier layer 118 is formed to cover the top surface 114A2 of the interconnect 114A, and the bottom barrier layer 119 is formed to cover the top surface 114B of the interconnect structure 114. The top barrier layer 118 is formed between the first dielectric layer 116A1 of the bonding dielectric structure 116A and the top surface 114A2 of the interconnect 114A. The bottom barrier layer 119 is formed between the passivation layer 114C of the interconnect structure 114 and the interconnect 114A. Furthermore, the materials of the top barrier layer 118 and the bottom barrier layer 119 may be tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0071] Figure 14 A cross-sectional view of a semiconductor structure according to the tenth embodiment of this disclosure is shown schematically.

[0072] Reference Figure 8 and Figure 14 , Figure 14 The semiconductor structure 110J shown is... Figure 8Similar to the semiconductor structure 110D shown, except that the topmost interconnect 114A of the interconnect structure 114 is a copper interconnect or copper pad, a top barrier layer 118 and a bottom barrier layer 119 are also formed to protect the interconnect 114A. The top barrier layer 118 is formed to cover the top surface 114A2 of the interconnect 114A, and the bottom barrier layer 119 is formed to cover the top surface 114B of the interconnect structure 114. The top barrier layer 118 is formed between the first dielectric layer 116A1 of the bonding dielectric structure 116A and the top surface 114A2 of the interconnect 114A. The bottom barrier layer 119 is formed between the passivation layer 114C of the interconnect structure 114 and the interconnect 114A. Furthermore, the materials of the top barrier layer 118 and the bottom barrier layer 119 may be tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0073] Figure 15 A cross-sectional view of a semiconductor structure according to the eleventh embodiment of this disclosure is shown schematically.

[0074] Reference Figure 9 and Figure 15 , Figure 15 The semiconductor structure 110K shown is... Figure 9 Similar to the semiconductor structure 110E shown, except that the topmost interconnect 114A of the interconnect structure 114 is a copper interconnect or copper pad, a top barrier layer 118 and a bottom barrier layer 119 are also formed to protect the interconnect 114A. The top barrier layer 118 is formed to cover the top surface 114A2 of the interconnect 114A, and the bottom barrier layer 119 is formed to cover the top surface 114B of the interconnect structure 114. The top barrier layer 118 is formed between the first dielectric layer 116A1 of the bonding dielectric structure 116A and the top surface 114A2 of the interconnect 114A. The bottom barrier layer 119 is formed between the passivation layer 114C of the interconnect structure 114 and the interconnect 114A. Furthermore, the materials of the top barrier layer 118 and the bottom barrier layer 119 may be tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials.

[0075] To minimize the contact resistance between the bonding conductor and the interconnect without significantly increasing the layout area of ​​the bonding conductor and the interconnect, the embodiments disclosed above utilize a deliberate overlap design between the body portion and the interconnect to increase the contact surface between the bonding conductor and the interconnect. This structure reduces over-etching and stripping defects, thereby improving yield.

[0076] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor substrate, an interconnect structure, and a bonding structure. The interconnect structure is disposed on the semiconductor substrate. The interconnect structure includes interconnect wiring distributed on a top surface of the interconnect structure. The bonding structure is disposed on the interconnect structure and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor. The bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor sits on the top surface of the interconnect wiring and a first sidewall of the interconnect wiring. In some embodiments, the bonding dielectric structure includes a first dielectric layer disposed on the top surface of the interconnect structure and covering the interconnect wiring; a second dielectric layer disposed on the first dielectric layer; and an etch stop layer disposed between the first dielectric layer and the second dielectric layer, wherein the bonding conductor penetrates the first dielectric layer, the etch stop layer, and the second dielectric layer. In some embodiments, the bonding conductor includes a bottom portion embedded in the first dielectric layer and the etch stop layer; a first protrusion embedded in the first dielectric layer, wherein the first protrusion extends from the bottom of the bottom portion to cover the first sidewall of the interconnect wiring; and a top portion embedded in the second dielectric layer. In some embodiments, the bottom portion includes a first bottom dimension and a first top dimension, and the top portion includes a second bottom dimension and a second bottom dimension, wherein the first top dimension is larger than the first bottom dimension, the second top dimension is larger than the second bottom dimension, and the second bottom dimension is larger than the first top dimension. In some embodiments, the semiconductor structure further includes a second protrusion extending from the bottom of the bottom portion to cover a second sidewall of the interconnect wiring, the second sidewall being opposite to the first sidewall, and the first protrusion and the second protrusion being located on opposite sides of the interconnect wiring. In some embodiments, a bonding conductor is situated at a corner of the interconnect wiring, the first protrusion further covering the second sidewall of the interconnect wiring, and the second sidewall being adjacent to the first sidewall. In some embodiments, a bonding conductor is situated at an end of the interconnect wiring, the first protrusion further covering the second sidewall and a third sidewall of the interconnect wiring, the second sidewall being adjacent to the first sidewall, and the third sidewall being opposite to the first sidewall. In some embodiments, the bonding conductor includes a body portion embedded in a bonding dielectric structure; and a first protrusion embedded in the bonding dielectric structure, wherein the protrusion extends from the bottom of the body portion to cover the first sidewall of the interconnect wiring. In some embodiments, the bonding conductor further includes a second protrusion extending from the bottom of the body portion to cover a second sidewall of the interconnect wiring, the second sidewall being opposite to the first sidewall, and the first and second protrusions being located on opposite sides of the interconnect wiring. In some embodiments, the bonding conductor is situated at a corner of the interconnect wiring, the first protrusion further covering the second sidewall of the interconnect wiring, the second sidewall being adjacent to the first sidewall. In some embodiments, the bonding conductor is situated at an end of the interconnect wiring, the first protrusion further covering the second and third sidewalls of the interconnect wiring, the second sidewall being adjacent to the first sidewall, and the third sidewall being opposite to the first sidewall.

[0077] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor die and a bonding structure. The semiconductor die includes interconnect wiring of an interconnect structure. The bonding structure is disposed on and electrically connected to the interconnect structure. The bonding structure includes a bonding dielectric structure and a bonding conductor embedded in the bonding dielectric structure. The bonding dielectric structure is disposed on a top surface of the interconnect structure and covers the interconnect wiring. The bonding conductor sits on the top surface of the interconnect wiring and on a first inclined sidewall of the interconnect wiring, the bonding dielectric structure contacting a second inclined sidewall of the interconnect wiring, the first inclined sidewall of the interconnect wiring extending from the top surface of the interconnect wiring to the second inclined sidewall of the interconnect wiring, and the second inclined sidewall of the interconnect wiring being steeper than the first inclined sidewall of the interconnect wiring. In some embodiments, the interconnect wiring further includes an inclined surface, the bonding conductor sitting on the inclined surface, the inclined surface extending from the top surface of the interconnect wiring to the first inclined sidewall of the interconnect wiring, and the first inclined sidewall of the interconnect wiring being steeper than the inclined surface of the interconnect wiring. In some embodiments, the bonding conductor includes a body portion embedded in the bonding dielectric structure; and a first protrusion embedded in the bonding dielectric structure, wherein the first protrusion extends from the bottom of the body portion to cover the first inclined sidewall of the interconnect wiring. In some embodiments, the bonding conductor further includes a second protrusion extending from the bottom of the body portion to cover a third inclined sidewall of the interconnect wiring, the third inclined sidewall being opposite to a first inclined sidewall, and the first and second protrusions being located on opposite sides of the interconnect wiring. In some embodiments, the bonding conductor is situated at a corner of the interconnect wiring, the first protrusion further covering the third inclined sidewall of the interconnect wiring, and the third inclined sidewall being adjacent to the first inclined sidewall. In some embodiments, the bonding conductor is situated at an end of the interconnect wiring, the first protrusion further covering the third and fourth inclined sidewalls of the interconnect wiring, the third inclined sidewall being adjacent to the first inclined sidewall, and the fourth inclined sidewall being opposite to the first inclined sidewall.

[0078] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising a semiconductor die and a bonding structure. The semiconductor die includes interconnect wiring. The bonding structure is disposed on the interconnect wiring and electrically connected to the interconnect wiring. The bonding structure includes a bonding dielectric structure disposed on a top surface of the semiconductor die and covering the interconnect wiring; and a bonding conductor embedded in the bonding dielectric structure, wherein the bonding conductor sits on the top surface of the interconnect wiring, and the bonding conductor includes a first protrusion that laterally covers a first sidewall of the interconnect wiring. In some embodiments, the bonding conductor further includes a second protrusion that laterally covers a second sidewall of the interconnect wiring, the second sidewall being opposite to the first sidewall, and the first protrusion and the second protrusion being located on opposite sides of the interconnect wiring. In some embodiments, the bonding conductor is located at a corner or end of the interconnect wiring.

[0079] The foregoing summary of the features of several embodiments enables those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and / or obtaining the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; An interconnect structure is disposed on the semiconductor substrate, the interconnect structure including interconnect wiring distributed on the top surface of the interconnect structure; A bonding structure is disposed on the interconnect structure and electrically connected to the interconnect structure, the bonding structure comprising: A bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring; as well as A bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor is located on the top surface of the interconnect wiring and on the first sidewall of the interconnect wiring.

2. The semiconductor structure as described in claim 1, characterized in that, The bonding dielectric structure includes: A first dielectric layer is disposed on the top surface of the interconnect structure and covers the interconnect wiring; A second dielectric layer is disposed above the first dielectric layer; and An etch stop layer is disposed between the first dielectric layer and the second dielectric layer, wherein the bonding conductor extends through the first dielectric layer, the etch stop layer, and the second dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, The bonding conductor includes: The bottom portion is embedded in the first dielectric layer and the etch stop layer; A first protrusion, embedded in the first dielectric layer, wherein the first protrusion extends from the bottom of the bottom portion to cover the first sidewall of the interconnect wiring; and The top portion is embedded in the second dielectric layer.

4. The semiconductor structure as described in claim 3, characterized in that, It further includes a second protrusion, wherein the second protrusion extends from the bottom of the bottom portion to cover a second sidewall of the interconnect wiring, the second sidewall being opposite to the first sidewall, and the first protrusion and the second protrusion being located on opposite sides of the interconnect wiring.

5. The semiconductor structure as described in claim 3, characterized in that, The bonding conductor is located at the corner of the interconnect wiring, the first protrusion further covers the second sidewall of the interconnect wiring, and the second sidewall is adjacent to the first sidewall.

6. The semiconductor structure as described in claim 3, characterized in that, The bonding conductor is located at the end of the interconnect wiring, and the first protrusion further covers the second sidewall and the third sidewall of the interconnect wiring, the second sidewall being adjacent to the first sidewall and the third sidewall being opposite to the first sidewall.

7. The semiconductor structure as described in claim 1, characterized in that, The bonding conductor includes: The body portion is embedded in the bonding dielectric structure; and A first protrusion is embedded in the bonding dielectric structure, wherein the protrusion extends from the bottom of the body portion to cover the first sidewall of the interconnect wiring.

8. The semiconductor structure as described in claim 7, characterized in that, The bonding conductor further includes a second protrusion extending from the bottom of the body portion to cover a second sidewall of the interconnect wiring, the second sidewall being opposite to the first sidewall, and the first protrusion and the second protrusion being located on opposite sides of the interconnect wiring.

9. A semiconductor structure, characterized in that, include: Semiconductor die, including interconnect wiring of interconnect structures; A bonding structure, disposed on and electrically connected to the interconnect structure, the bonding structure comprising: A bonding dielectric structure is disposed on the top surface of the interconnect structure and covers the interconnect wiring; as well as A bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor is located on the top surface of the interconnect wiring and on a first inclined sidewall of the interconnect wiring, the bonding dielectric structure is in contact with a second inclined sidewall of the interconnect wiring, the first inclined sidewall of the interconnect wiring extending from the top surface of the interconnect wiring to the second inclined sidewall of the interconnect wiring, and the second inclined sidewall of the interconnect wiring is steeper than the first inclined sidewall of the interconnect wiring.

10. A semiconductor structure, characterized in that, include: Semiconductor chips, including interconnect wiring; A bonding structure, configured on the interconnect wiring and electrically connected to the interconnect wiring, the bonding structure comprising: A bonding dielectric structure is disposed on the top surface of the semiconductor die and covers the interconnect wiring; as well as A bonding conductor is embedded in the bonding dielectric structure, wherein the bonding conductor is situated on the top surface of the interconnect wiring, and the bonding conductor includes a first protrusion that laterally covers a first sidewall of the interconnect wiring.

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