A detection circuit and detection system for a type I three-level inverter

Abstract

This utility model discloses a detection circuit and detection system for a Type I three-level inverter. The detection circuit for the Type I three-level inverter includes: a test power supply module, a control module, a detection branch group corresponding one-to-one with the inverter branches in the Type I three-level inverter, and a current detection module corresponding one-to-one with the inverter branches. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected in series between the first polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the first detection branch. The second detection branch is connected in series between the second polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the second detection branch. The current detection module is configured to detect the current of the inverter branch corresponding to the current detection module. The detection circuit is connected to three ports: the first polarity terminal of the photovoltaic input, the second polarity terminal of the photovoltaic input, and the grid-connected output terminal, without disassembling the inverter casing, thus ensuring the integrity of the casing protection.

Description

Technical Field

[0001] This utility model relates to the field of inverter testing technology, and in particular to a testing circuit and testing system for a type I three-level inverter. Background Technology

[0002] A Static Var Generator (SVG) is a grid-connected inverter device that addresses reactive power, harmonics, and low power factor issues on the low-voltage side by injecting current into the grid through parallel connection with low-voltage lines. The Type I three-level inverter is a common topology. The switching transistors are the core circuitry of the inverter; timely detection of abnormalities in the inverter's switching transistors can prevent further damage to the inverter.

[0003] Therefore, the control and testing of the switching transistors are quite strict during the production process of Type I three-level inverters. Furthermore, after the Type I three-level inverter is manufactured, the casing is generally fully installed, and the sealing strip between the casing and the cover is tightened. If the switching transistors were tested using traditional methods, the casing of the Type I three-level inverter would need to be opened, and the testing device would need to be manually connected to the circuit board containing the switching transistors inside the inverter. This would result in problems such as damaging the sealing strip and excessively long operation time, affecting production efficiency. Utility Model Content

[0004] This invention provides a detection circuit and detection system for a Type I three-level inverter to solve the problems of damaging the sealing strip and excessive operation time affecting production efficiency when detecting the switching transistors in a Type I three-level inverter.

[0005] According to one aspect of the present invention, a detection circuit for a type I three-level inverter is provided, which is applied to a type I three-level inverter. The type I three-level inverter includes a photovoltaic input first polarity terminal, a photovoltaic input second polarity terminal, at least one phase grid-connected output terminal, and an inverter branch corresponding to the grid-connected output terminal. The inverter branch is connected between the internal node of the type I three-level inverter and the grid-connected output terminal corresponding to the inverter branch.

[0006] The detection circuit of the type I three-level inverter includes: a test power supply module, a control module, a detection branch group corresponding to each inverter branch, and a current detection module corresponding to each inverter branch. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected in series between the first polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the first detection branch. The second detection branch is connected in series between the second polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the second detection branch.

[0007] The first end of the test power supply module is connected to the first polarity terminal of the photovoltaic input, the second end of the test power supply module is connected to the second polarity terminal of the photovoltaic input, and the control terminal of the test power supply module is connected to the control module;

[0008] The current detection module is configured to detect the current of the inverter branch corresponding to the current detection module;

[0009] The inverter branch includes at least one switching transistor. The control module is connected to the control terminal of each switching transistor, the control terminal of the first detection branch, and the control terminal of the second detection branch. The inverter branch is configured to control one of the first detection branch and the second detection branch corresponding to the inverter branch to which the switching transistor under test belongs to conduct according to the switching transistor under test.

[0010] Optionally, the test power supply module includes a DC power supply and a power control switch;

[0011] The first terminal of the power control switch is connected to the first electrode of the DC power supply, the second terminal of the power control switch is connected to the first polarity terminal of the photovoltaic input, and the control terminal of the power control switch is connected to the control module.

[0012] The second terminal of the DC power supply is connected to the second polarity terminal of the photovoltaic input.

[0013] Optionally, the power control switch is a contactor.

[0014] Optionally, the first detection branch includes a first detection switch, a first terminal of the first detection switch is connected to the first polarity terminal of the photovoltaic input, a second terminal of the first detection switch is connected to the grid-connected output terminal of the inverter branch corresponding to the first detection switch, and a control terminal of the first detection switch is connected to the control module.

[0015] The second detection branch includes a second detection switch. The first end of the second detection switch is connected to the second polarity terminal of the photovoltaic input, the second end of the second detection switch is connected to the grid-connected output terminal of the inverter branch corresponding to the second detection switch, and the control terminal of the second detection switch is connected to the control module.

[0016] Optionally, both the first detection switch and the second detection switch are contactors.

[0017] Optionally, the detection circuit of the type I three-level inverter further includes: a boost inductor, a first capacitor, and a second capacitor;

[0018] The first terminal of the boost inductor is connected to the first polarity terminal of the photovoltaic input, the second terminal of the boost inductor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the second polarity terminal of the photovoltaic input.

[0019] The first end of the inverter branch is connected to the first end of the first capacitor, the second end of the inverter branch is connected to the second end of the first capacitor, the third end of the inverter branch is connected to the second end of the second capacitor, and the fourth end of the inverter branch is connected to the corresponding grid-connected output terminal of the inverter branch.

[0020] Optionally, for any of the inverter branches, the inverter branch includes an inverter inductor, and the inverter branch further includes: a third switch and a first switch connected in series between the first terminal of the first capacitor and the first terminal of the inverter inductor; a second switch and a fourth switch connected in series between the first terminal of the inverter inductor and the second polarity terminal of the photovoltaic input; a fifth diode and a sixth diode connected in series between the common terminal connected to the second switch and the fourth switch and the common terminal connected to the third switch and the first switch, and in the same direction; the common terminal connected to the fifth diode and the sixth diode is also connected to the second terminal of the first capacitor.

[0021] Optionally, the current detection module includes a Hall sensor, which is mounted on the line at the first end of the inverter inductor.

[0022] According to another aspect of the present invention, a detection system for a type I three-level inverter is provided, including the detection circuit for the type I three-level inverter described in the previous aspect.

[0023] Optionally, the detection system for the type I three-level inverter further includes an oscilloscope, which is connected to the current detection module.

[0024] The technical solution of this utility model embodiment provides a corresponding detection branch group for each phase in the T-type inverter. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected between the photovoltaic input first polarity terminal and the grid-connected output terminal, and the second detection branch is connected between the photovoltaic input second polarity terminal and the grid-connected output terminal. When detecting the switching transistor, the switching transistor and one of the first detection branch and the second detection branch are connected to form a current flow path. The abnormality detection of the switching transistor is achieved by detecting the current in the detection circuit. Meanwhile, since the first and second photovoltaic input terminals are themselves the interfaces for connecting the photovoltaic modules to the Type I three-level inverter, and the grid-connected output terminal is the interface for connecting to the power grid, and all three interfaces are located on the inverter's casing, the detection circuit in this invention can detect the internal switching transistors of the Type I three-level inverter by connecting to the three ports: the first and second photovoltaic input terminals and the grid-connected output terminal. This eliminates the need to disassemble the Type I three-level inverter's casing, ensuring the integrity of the casing's protection. Furthermore, the connection between the detection circuit and the Type I three-level inverter is convenient and quick, shortening testing time and improving production efficiency.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the detection circuit of a type I three-level inverter provided in this embodiment of the utility model;

[0028] Figure 2 A driving timing diagram of the detection circuit of a type I three-level inverter provided for an embodiment of this utility model;

[0029] Figure 3 A circuit diagram for detecting the fourth switching transistor provided in this embodiment of the present invention;

[0030] Figure 4 A current waveform diagram on the inverter inductor during the detection of the fourth switching transistor is provided in an embodiment of this utility model;

[0031] Figure 5A circuit diagram for detecting the second switching transistor provided in an embodiment of this utility model;

[0032] Figure 6 A circuit diagram for detecting a third switching transistor is provided in an embodiment of this utility model;

[0033] Figure 7 This is a circuit diagram for detecting the first switching transistor, provided as an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Figure 1 This is a schematic diagram of the detection circuit for a Type I three-level inverter provided in an embodiment of the present invention. The Type I three-level inverter includes a photovoltaic input first polarity terminal PV+, a photovoltaic input second polarity terminal PV-, at least one phase grid-connected output terminal INV, and an inverter branch 10 corresponding to the grid-connected output terminal INV. The inverter branch 10 is connected between the internal nodes of the Type I three-level inverter and the corresponding grid-connected output terminal INV. The photovoltaic input first polarity terminal PV+ and the photovoltaic input second polarity terminal PV- are PV interfaces used to connect to the input interfaces of a photovoltaic array or solar panel; one is the positive terminal, and the other is the negative terminal.

[0037] The detection circuit of the type I three-level inverter includes: a test power supply module 12, a control module, a detection branch group corresponding to each inverter branch 10, and a current detection module H1 corresponding to each inverter branch 10. The detection branch group includes a first detection branch 111 and a second detection branch 112. The first detection branch 111 is connected in series between the first polarity terminal PV+ of the photovoltaic input and the grid-connected output terminal INV of the inverter branch 10 corresponding to the first detection branch 111. The second detection branch 112 is connected in series between the second polarity terminal PV- of the photovoltaic input and the grid-connected output terminal INV of the inverter branch 10 corresponding to the second detection branch 112.

[0038] The first terminal of the test power supply module 12 is connected to the first polarity terminal PV+ of the photovoltaic input, the second terminal of the test power supply module 12 is connected to the second polarity terminal PV- of the photovoltaic input, and the control terminal of the test power supply module 12 is connected to the control module.

[0039] The current detection module H1 is configured to detect the current of the inverter branch 10 corresponding to the current detection module H1;

[0040] The inverter branch 10 includes at least one switching transistor. The control module is connected to the control terminal of each switching transistor, the control terminal of the first detection branch 111, and the control terminal of the second detection branch 112. The inverter branch 10 is configured to control one of the first detection branch 111 and the second detection branch 112 corresponding to the inverter branch 10 to which the switching transistor to be tested is turned on according to the switching transistor to be tested.

[0041] Furthermore, the detection circuit of the Type I three-level inverter also includes: boost inductor L2, first capacitor C1, and second capacitor C2;

[0042] The first terminal of the boost inductor L2 is connected to the first polarity terminal PV+ of the photovoltaic input, the second terminal of the boost inductor L2 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the second polarity terminal PV- of the photovoltaic input.

[0043] The first terminal of inverter branch 10 is connected to the first terminal of the first capacitor C1, the second terminal of inverter branch 10 is connected to the second terminal of the first capacitor C1, the third terminal of inverter branch 10 is connected to the second terminal of the second capacitor C2, and the fourth terminal of inverter branch 10 is connected to the corresponding grid-connected output terminal INV of inverter branch 10.

[0044] For any inverter branch 10, the inverter branch 10 includes an inverter inductor L1, and the inverter branch 10 also includes: a third switch T3 and a first switch T1 connected in series between the first terminal of the first capacitor C1 and the first terminal of the inverter inductor L1; a second switch T2 and a fourth switch T4 connected in series between the first terminal of the inverter inductor L1 and the second polarity terminal PV- of the photovoltaic input; a fifth diode D5 and a sixth diode D6 connected in series between the common terminal connected to the second switch T2 and the fourth switch T4 and the common terminal connected to the third switch T3 and the first switch T1, and in the same direction; the common terminal connected to the fifth diode D5 and the sixth diode D6 is also connected to the second terminal of the first capacitor C1.

[0045] Specifically, the first terminal of the third switch transistor T3 is connected to the first terminal of the first capacitor C1, the second terminal of the third switch transistor T3 is connected to the first terminal of the first switch transistor T1, the second terminal of the first switch transistor T1 is connected to the first terminal of the second switch transistor T2, the second terminal of the second switch transistor T2 is connected to the first terminal of the fourth switch transistor T4, the second terminal of the fourth switch transistor T4 is connected to the second terminal of the second capacitor, and the base of each switch transistor is connected to the control module. The first terminal of each switch transistor is the collector, and the second terminal is the emitter. Each switch transistor includes an anti-parallel diode. The anti-parallel diode included in the third switch transistor T3 is denoted as the third diode D3, the anti-parallel diode included in the first switch transistor T1 is denoted as the first diode D1, the anti-parallel diode included in the second switch transistor T2 is denoted as the second diode D2, and the anti-parallel diode included in the fourth switch transistor T4 is denoted as the fourth diode D4. The anti-parallel diodes included in the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 all have the same orientation; that is, the anode of the anti-parallel diode is connected to the second terminal of its respective switch transistor, and the cathode is connected to the first terminal of its respective switch transistor. The anode of the fifth diode D5 is connected to the second terminal of the second switch transistor T2, the cathode of the fifth diode D5 is connected to the anode of the sixth diode D6, and the cathode of the sixth diode D6 is connected to the second terminal of the third switch transistor T3. The first terminal of the third switch transistor T3 serves as the first terminal of the inverter branch 10, the anode of the sixth diode D6 serves as the second terminal of the inverter branch 10, and the second terminal of the fourth switch transistor T4 serves as the third terminal of the inverter branch.

[0046] Optionally, each inverter branch 10 also includes an inverter switch Rly. For any inverter branch: the first terminal of the inverter switch Rly is connected to the second terminal of the inverter inductor L1, the second terminal of the inverter switch Rly is connected to the grid-connected output terminal INV of the inverter branch 10, and the second terminal of the inverter switch Rly serves as the fourth terminal of the inverter branch 10.

[0047] Continue to refer to Figure 1Optionally, the current detection module H1 includes a Hall sensor, which is mounted on the line at the first end of the inverter inductor L1.

[0048] During the testing of the switching transistor, the current generated consumes energy in the copper busbar and inductor. Therefore, it is necessary to set the inverter DC bus to be charged by the test power supply module 12 after it falls below a certain amplitude before the subsequent test can continue, so as to ensure the smooth progress of the switching transistor test and the accuracy of the test results.

[0049] The technical solution of this utility model embodiment provides a corresponding detection branch group for each phase in the T-type inverter. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected between the photovoltaic input first polarity terminal and the grid-connected output terminal, and the second detection branch is connected between the photovoltaic input second polarity terminal and the grid-connected output terminal. When detecting the switching transistor, the switching transistor and one of the first detection branch and the second detection branch are connected to form a current flow path. The abnormality detection of the switching transistor is achieved by detecting the current in the detection circuit. Meanwhile, since the first and second photovoltaic input terminals are themselves the interfaces for connecting the photovoltaic modules to the Type I three-level inverter, and the grid-connected output terminal is the interface for connecting to the power grid, and all three interfaces are located on the inverter's casing, the detection circuit in this invention can detect the internal switching transistors of the Type I three-level inverter by connecting to the three ports: the first and second photovoltaic input terminals and the grid-connected output terminal. This eliminates the need to disassemble the Type I three-level inverter's casing, ensuring the integrity of the casing's protection. Furthermore, the connection between the detection circuit and the Type I three-level inverter is convenient and quick, shortening testing time and improving production efficiency.

[0050] Optionally, the test power supply module 12 includes a DC power supply 121 and a power control switch KM;

[0051] The first terminal of the power control switch KM is connected to the first terminal of the DC power supply 121, and the second terminal of the power control switch KM is connected to the first polarity terminal PV+ of the photovoltaic input. The control terminal of the power control switch KM is connected to the control module. The second terminal of the DC power supply 121 is connected to the second polarity terminal PV- of the photovoltaic input. The first terminal of the DC power supply 121 is the positive terminal, and the second terminal is the negative terminal.

[0052] The first detection branch 111 includes a first detection switch KM1. The first terminal of the first detection switch KM1 is connected to the first polarity terminal PV+ of the photovoltaic input, and the second terminal of the first detection switch KM1 is connected to the grid-connected output terminal INV of the inverter branch 10 corresponding to the first detection switch KM1. The control terminal of the first detection switch KM1 is connected to the control module. The second detection branch 112 includes a second detection switch KM2. The first terminal of the second detection switch KM2 is connected to the second polarity terminal PV- of the photovoltaic input, and the second terminal of the second detection switch KM2 is connected to the grid-connected output terminal INV of the inverter branch 10 corresponding to the second detection switch KM2. The control terminal of the second detection switch KM2 is connected to the control module.

[0053] Optionally, the first detection switch KM1, the second detection switch KM2, and the power control switch KM are all contactors. The contactors can switch large currents, and the contacts are made of high-quality materials, which are durable and can operate stably for a long time. They also allow high-frequency switching operations, and have high power carrying capacity, stability in frequent operation, convenience of remote control, and safety protection functions.

[0054] A Type I three-level inverter can be a three-phase inverter, including phases A, B, and C. Correspondingly, it includes three-phase inverter branches: the inverter branch for phase A, the inverter branch for phase B, and the inverter branch for phase C. The devices and their connections within each inverter branch 10 are identical. The Type I three-level inverter includes three grid-connected output terminals INV. The first and second detection branches of the phase A inverter branch are connected to the grid-connected output terminal of phase A; the first and second detection branches of the phase B inverter branch are connected to the grid-connected output terminal of phase B; and the first and second detection branches of the phase C inverter branch are connected to the grid-connected output terminal of phase C. When the Type I three-level inverter is a three-phase inverter, the performance of the switching transistors can be tested sequentially for each phase, or all three phases can be tested simultaneously. For any given phase, the performance of the four switching transistors included in that phase's inverter branch is tested sequentially. In three-phase simultaneous testing, the same switching transistors are turned on in each phase at the same time; for example, the first switching transistor T1 is tested in a three-phase simultaneous test. A type I three-level inverter can also be a single-phase inverter, such as... Figure 1 As shown, it includes only one inverter branch 10 and one grid-connected output port INV.

[0055] Figure 2 This is a driving timing diagram of the detection circuit of a type I three-level inverter provided in an embodiment of the present invention, and it is exemplarily shown that all switches are turned on at a high potential. Figure 3 This invention provides a circuit diagram for detecting the fourth switching transistor according to an embodiment of the present invention. Figure 4 This invention provides a current waveform diagram on the inverter inductor during the detection of the fourth switching transistor, as shown in this embodiment. Figure 4The horizontal axis represents time (in seconds), and the vertical axis represents the current iL in the first inductor (in amperes). Figure 5 This invention provides a circuit diagram for detecting the second switching transistor according to an embodiment of the present invention. Figure 6 This invention provides a circuit diagram for detecting a third switching transistor according to an embodiment of the present invention. Figure 7 This invention provides a circuit diagram for detecting the first switching transistor according to an embodiment of the present invention. Figure 3 , Figure 5 , Figure 6 and Figure 7 The red line represents the current path of the switching transistor, and the blue line represents the freewheeling current path of the anti-parallel diode.

[0056] like Figure 3 As shown, when the fourth switch T4 needs to be tested, since the output port of the inductor cannot be connected to the DC bus + inside the inverter product, the first detection branch where the first detection switch KM1 is located is connected to the first polarity terminal PV+ of the photovoltaic input, that is, connected to the DC bus + through the boost inductor L2. After closing the inverter switch Rly and the first detection switch KM1, a long-term conduction pulse is given to the second switch T2 to keep it conducting during the test of the fourth switch T4. Then, a drive pulse is given to the fourth switch T4, and the fourth switch T4 turns on. The current flows out from the first terminal of the first capacitor C1, through the boost inductor L2 and the inverter inductor L1, through the second switch T2 and the fourth switch T4, and flows into the second terminal of the second capacitor C2 (as shown by the red arrow in the loop). During this process, the current flowing through the second switch T2 and the fourth switch T4 increases linearly due to the current limiting effect of the inverter inductor L1 and the boost inductor L2 in the loop. When the drive pulse ends, the fourth switch T4 turns off first, and the current in the inverter inductor L1 rises to its highest value and then begins to decrease. The current freewheels in the circuit formed by the first diode D1, the third diode D3, the inverter inductor L1, and the boost inductor L2 until it is reduced to zero. The current in the inverter inductor L1 can be monitored throughout the process using the current detection module H1. Given a set switching time t1 for the second switch T2, a set initial voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and determined inductance values ​​for the inverter inductor L1 and the boost inductor L2, the theoretical current iL1 in the inverter inductor L1 at the moment the fourth switch T4 turns off can be calculated using the following formula: Where t1 is the conduction time of the fourth switch T4, L is the sum of the inductance values ​​of the inverter inductor L1 and the boost inductor L2, and the theoretical current value iL1 is stored in the control module and compared with the current value collected by the current detection module H1 during the above process. If the deviation between the two is less than the preset deviation value, the fourth switch T4 is functioning normally. Simultaneously, after the fourth switch T4 is turned off, the current in the inverter inductor L1 freewheels through the first diode D1 and the third diode D3, and the current value gradually decreases. By monitoring the trend of the current change in the inverter inductor L1, if there is a decreasing trend after the fourth switch T4 is turned off, it can be determined that the first diode D1 and the third diode D3 are functioning normally. If the current drops to 0 in a very short time without a gradual decreasing trend, it is determined that at least one of the first diode D1 and the third diode D3 is malfunctioning. Figure 4 As shown, when the fourth switch T4 is functioning normally, in the first stage M1, the fourth switch T4 is in the conducting state, and the current in the inverter inductor L1, i.e., the current in the circuit, gradually increases. In the second stage M2 after the fourth switch T4 is turned off, if the first diode D1 and the third diode D3 are functioning normally, the current in the circuit gradually decreases to 0. Therefore, by monitoring the current during the test, it can be determined whether the performance of the fourth switch T4, the first diode D1, and the third diode D3 is normal.

[0057] like Figure 5 As shown, for the case where the second switch T2 needs to be tested, since the output port of the inductor cannot be connected to the DC bus + inside the inverter product, the first detection branch containing the first detection switch KM1 is connected to the first polarity terminal PV+ of the photovoltaic input, that is, connected to the DC bus + through the boost inductor L2. After closing the inverter switch Rly and the first detection switch KM1, a drive pulse is first given to the second switch T2, turning on the second switch T2. Current flows out from the first terminal of the first capacitor C1, through the boost inductor L2 and the inverter inductor L1, through the second switch T2, through the fifth diode D5, and into the second terminal of the first capacitor C1 (as shown by the red arrow in the loop). During this process, the current flowing through the second switch T2 increases linearly due to the current limiting effect of the boost inductor L2 and the inverter inductor L1 in the loop. When the drive pulse ends, the second switch T2 turns off, and the current value on the inverter inductor L1 or the current in the loop rises to its maximum value and then begins to decrease. Due to the freewheeling effect of the boost inductor L2 and the inverter inductor L1, current freewheels through the first diode D1 and the third diode D3, resulting in zero loss. Given a set switching time t2 for the second switch T2, a set initial voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and determined inductance values ​​for the boost inductor L2 and the inverter inductor L1, the theoretical current iL2 across the inverter inductor L1 at the moment the second switch T2 is turned off can be calculated. Where t2 is the conduction time of the second switch T2 when detecting whether the second switch T2 is abnormal, L is the sum of the inductance values ​​of the inverter inductor L1 and the boost inductor L2, and U2 is the voltage across the first capacitor. Since the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are equal, U2 = U1 / 2. The theoretical current value iL2 will be stored in the control module and compared with the current value collected by the current detection module H1 in the above process to determine whether the performance of the second switch T2 and the fifth diode D5 is normal.

[0058] After testing the fourth switch T4 and the second switch T2, due to the energy loss in the copper busbar and inductor, the power control switch KM needs to be closed to charge the first capacitor C1 and the second capacitor C2 to ensure the smooth progress of subsequent tests and the accuracy of the test results.

[0059] like Figure 6 As shown, for the case where the third switch T3 needs to be tested, since the output port of the inductor cannot be connected to the DC bus inside the inverter, the second detection branch containing the second detection switch KM2 is connected to the second polarity terminal PV- of the photovoltaic input. The second polarity terminal PV- of the photovoltaic input is short-circuited with the DC bus inside the inverter. After closing the inverter switch Rly and the second detection switch KM2, a long-duration conduction pulse is first applied to the first switch T1. This conduction pulse continues throughout the entire conduction process of the third switch T3. Then, a drive pulse is applied to the third switch T3, turning it on. Current flows out from the first terminal of the first capacitor C1 on the DC bus, through the third switch T3 and the first switch T1, and then through the inverter inductor L1 to the second terminal of the second capacitor C2 on the DC bus (as shown by the red arrow in the loop). During this process, the current flowing through the first switch T1 and the third switch T3 increases linearly due to the current-limiting effect of the inverter inductor L1 in the loop. When the drive pulse ends, the third switch T3 turns off, and the current in the inverter inductor L1 rises to its maximum value and then begins to decrease. When the drive pulse for the third switch T3 ends, the first switch T1 turns off again, and the current in the inverter inductor L1 rises to its maximum value and then begins to decrease. The current freewheels in the circuit formed by the second diode D2 and the fourth diode D4 until the loss reaches zero. Given the switching time t3 of the third switch T3, the initial voltage U1 between the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and the inductance value of the inverter inductor L1, the theoretical current iL3 in the inverter inductor L1 at the moment the third switch T3 turns off can be calculated using the following formula: Where t3 is the conduction time of the third switch T3 when detecting whether the third switch T3 is abnormal, L11 is the inductance value of the inverter inductor L1, and the theoretical current value iL3 is stored in the control module. The current detection module H1 monitors the current of the inverter inductor L1 throughout the process. The theoretical current value iL3 of the inverter inductor L1 at the moment the third switch T3 is turned off is compared with the current value collected by the current detection module H1 during the process to determine whether the performance of the third switch T3 is normal. The current waveform flowing through the inverter inductor L1 is similar to that when testing the fourth switch T4, except that because the boost inductor L2 is not connected in series, the current rise slope will be greater. The turn-on time of the third switch T3 needs to be adjusted within the range that ensures the safety of the switch.

[0060] like Figure 7 As shown, for the case where the first switch T1 needs to be tested, since the output port of the inductor cannot be connected to the DC bus inside the inverter, the second detection branch containing the second detection switch KM2 is connected to the second polarity terminal PV- of the photovoltaic input. The second polarity terminal PV- of the photovoltaic input is shorted to the DC bus inside the inverter. After closing the inverter switch Rly and the second detection switch KM2, a drive pulse is first applied to the first switch T1, turning it on. Current flows out from the first terminal of the second capacitor C2 on the DC bus, through the sixth diode D6, through the first switch T1, and then through the inverter inductor L1 before flowing into the second terminal of the second capacitor C2 on the DC bus (as shown by the red arrow). During this process, the current flowing through the first switch T1 increases linearly due to the current limiting effect of the inverter inductor L1 in the circuit. When the drive pulse ends, the first switch T1 turns off, and the current in the inverter inductor L1 rises to its maximum value and then begins to decrease. Then, due to the freewheeling effect of inverter inductor L1, the current flows through the loop of second diode D2, fourth diode D4, and inverter inductor L1, decreasing to 0 with losses. Given a set switching time t4 for the first switch T1, a set initial voltage U1 at the first terminal of the first capacitor C1 and the second terminal of the second capacitor C2, and a determined inductance value for inverter inductor L1, the theoretical current iL4 across inverter inductor L1 at the moment the first switch T1 is turned off can be calculated using the following formula: Where t4 is the conduction time of the first switch T1 when detecting whether the first switch T1 is abnormal, L11 is the inductance value of the inverter inductor L1, and U3 is the voltage across the second capacitor, U3 = U1 / 2. The theoretical current value iL4 is stored in the control module. Through the current detection module H1, the current of the inverter inductor L1 can be monitored throughout the process. The current value collected by the current detection module H1 during the above process is compared with the theoretical current value iL4 of the inverter inductor L1 at the moment when the first switch T1 is turned off. In a typical Type I three-level inverter, the parameters of the fifth diode D5 and the sixth diode D6 differ from the parameters of the anti-parallel diodes in the switch. The turn-on time of the first switch T1 needs to be adjusted appropriately according to the parameters of the fifth diode D5 and the sixth diode D6.

[0061] Figure 3 One method is to test all three phases simultaneously, meaning that the first switch T1, the second switch T2, the third switch T3, and the fourth switch T3 of the three phases are tested at the same time. An example is shown where, for one phase, the fourth switch T4, the second switch T2, the third switch T3, and the first switch T1 are tested sequentially. In other embodiments, the timing of the switches can be adjusted according to actual conditions, such as testing the first switch T1, the fourth switch T4, the second switch T2, and the third switch T3 sequentially.

[0062] During the testing process, the detection circuit of the Type I three-level inverter communicates with the host computer. After the DC power supply completes charging and the Type I three-level inverter completes its self-test, the Type I three-level inverter notifies the host computer that the switching transistor testing can be started. The host computer sends a test start command to the Type I three-level inverter. Inside the Type I three-level inverter, the switching transistors of each phase are tested according to the above procedure. After the test, the current in the test circuit is compared with the theoretical current value to screen out the failed switching transistors and anti-parallel diodes, and the fault is reported to the host computer.

[0063] This utility model embodiment also provides a detection system for a type I three-level inverter, including the detection circuit for a type I three-level inverter in any of the above embodiments. Furthermore, the beneficial effects of the detection system for a type I three-level inverter are the same as those of the detection circuit for a type I three-level inverter, and will not be repeated here.

[0064] Optionally, the testing system for the Type I three-level inverter also includes an oscilloscope, which is connected to the current detection module to more intuitively display the waveform of the current on the inverter inductor during the test.

[0065] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0066] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A detection circuit of a type-I three-level inverter, applied to a type-I three-level inverter, characterized in that, The type I three-level inverter includes a photovoltaic input first polarity terminal, a photovoltaic input second polarity terminal, at least one grid-connected output terminal, and an inverter branch corresponding to the grid-connected output terminal. The inverter branch is connected between the internal nodes of the type I three-level inverter and the grid-connected output terminal corresponding to the inverter branch. The detection circuit of the type I three-level inverter includes: a test power supply module, a control module, a detection branch group corresponding to each inverter branch, and a current detection module corresponding to each inverter branch. The detection branch group includes a first detection branch and a second detection branch. The first detection branch is connected in series between the first polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the first detection branch. The second detection branch is connected in series between the second polarity terminal of the photovoltaic input and the grid-connected output terminal corresponding to the inverter branch corresponding to the second detection branch. The first end of the test power supply module is connected to the first polarity terminal of the photovoltaic input, the second end of the test power supply module is connected to the second polarity terminal of the photovoltaic input, and the control terminal of the test power supply module is connected to the control module; The current detection module is configured to detect the current of the inverter branch corresponding to the current detection module; The inverter branch includes at least one switching transistor. The control module is connected to the control terminal of each switching transistor, the control terminal of the first detection branch, and the control terminal of the second detection branch. The inverter branch is configured to control one of the first detection branch and the second detection branch corresponding to the inverter branch to which the switching transistor under test belongs to conduct according to the switching transistor under test.

2. The detection circuit of a type-I three-level inverter according to claim 1, characterized in that, The test power supply module includes a DC power supply and a power control switch; The first terminal of the power control switch is connected to the first electrode of the DC power supply, the second terminal of the power control switch is connected to the first polarity terminal of the photovoltaic input, and the control terminal of the power control switch is connected to the control module. The second terminal of the DC power supply is connected to the second polarity terminal of the photovoltaic input.

3. The detection circuit of a type-I three-level inverter according to claim 2, characterized in that, The power control switch is a contactor.

4. The detection circuit of a type-I three-level inverter according to claim 1, characterized by, The first detection branch includes a first detection switch, the first end of the first detection switch is connected to the first polarity terminal of the photovoltaic input, the second end of the first detection switch is connected to the grid-connected output terminal of the inverter branch corresponding to the first detection switch, and the control terminal of the first detection switch is connected to the control module. The second detection branch includes a second detection switch. The first end of the second detection switch is connected to the second polarity terminal of the photovoltaic input, the second end of the second detection switch is connected to the grid-connected output terminal of the inverter branch corresponding to the second detection switch, and the control terminal of the second detection switch is connected to the control module.

5. The detection circuit of a type-I three-level inverter according to claim 4, characterized in that, Both the first detection switch and the second detection switch are contactors.

6. The detection circuit of a type-I three-level inverter according to claim 1, characterized by, The detection circuit of the type I three-level inverter also includes: a boost inductor, a first capacitor, and a second capacitor; The first terminal of the boost inductor is connected to the first polarity terminal of the photovoltaic input, the second terminal of the boost inductor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the second polarity terminal of the photovoltaic input. The first end of the inverter branch is connected to the first end of the first capacitor, the second end of the inverter branch is connected to the second end of the first capacitor, the third end of the inverter branch is connected to the second end of the second capacitor, and the fourth end of the inverter branch is connected to the corresponding grid-connected output terminal of the inverter branch.

7. The detection circuit of a type-I three-level inverter according to claim 6, characterized by, For any of the inverter branches, the inverter branch includes an inverter inductor, and the inverter branch further includes: a third switch and a first switch connected in series between the first terminal of the first capacitor and the first terminal of the inverter inductor; a second switch and a fourth switch connected in series between the first terminal of the inverter inductor and the second polarity terminal of the photovoltaic input; a fifth diode and a sixth diode connected in series between the common terminal connected to the second switch and the fourth switch and the common terminal connected to the third switch and the first switch, and in the same direction; the common terminal connected to the fifth diode and the sixth diode is also connected to the second terminal of the first capacitor.

8. The detection circuit of a type-I three-level inverter according to claim 7, characterized by, The current detection module includes a Hall sensor, which is mounted on the line at the first end of the inverter inductor.

9. A detection system for a type I three-level inverter, characterized by The detection circuit includes the type I three-level inverter as described in any one of claims 1-8.

10. The detection system of a type-I three-level inverter according to claim 9, characterized in that, It also includes an oscilloscope, which is connected to the current detection module.

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