Clock alignment circuit and direct time-of-flight sensor

Abstract

This invention discloses a clock alignment circuit and a direct time-of-flight sensor, relating to the field of electronic technology. The clock alignment circuit includes a clock supply circuit, a delay phase-locked loop (PLL) circuit, a replica voltage-controlled delay (VCD) circuit, and a clock correction circuit. This application introduces an independent clock correction circuit to form an auxiliary calibration loop, comparing and dynamically adjusting the clock signal at the input of the replica VCD chain to compensate for the inherent delay in the PLL transmission path. This ensures high-precision phase alignment between the initial phase of the multi-phase clock signal and the reference second clock signal, thereby eliminating systematic measurement errors introduced by phase offset. By strictly aligning the initial phase of the multi-phase clock signal with the system clock, the accuracy of the fractional part of the time-of-flight measurement reference is ensured, effectively avoiding measurement errors that may occur in the fractional part due to phase misalignment, and improving the overall ranging accuracy and reliability of the direct time-of-flight sensor.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, and in particular to a clock alignment circuit and a direct time-of-flight sensor. Background Technology

[0002] Direct Time-of-Flight (DToF) sensors are a high-precision distance measurement technology. Their core principle involves emitting a laser pulse towards a target and accurately measuring the round-trip time (flight time) from emission to detection by a receiver. The distance is then calculated based on the speed of light. The flight time is typically obtained using a Time-to-Digital Converter (TDC). The TDC consists of coarse and fine counts, yielding the integer and fractional parts of the flight time respectively, thus achieving high-precision measurement. One feasible method for generating a multi-phase clock is to first generate a system clock using a phase-locked loop (PLL), and then use a time-delayed PLL to lock the system clock with a delay to obtain a precise multi-phase clock.

[0003] However, after the system clock is delayed and locked by the time-delay phase-locked loop (TDL), the initial phase of the TLL is no longer aligned with the system clock due to various delays in the TLL transmission path. This will affect the fractional part of the measured value. Utility Model Content

[0004] The main purpose of this invention is to propose a clock alignment circuit and a direct time-of-flight sensor, which aims to solve the technical problem that the initial phase of the existing direct time-of-flight sensor's time-delay phase-locked loop is not aligned with the system clock.

[0005] To achieve the above objectives, this application proposes a clock alignment circuit for use in a direct time-of-flight sensor, comprising: A clock providing circuit is used to provide multiple synchronized clock signals, the clock signals including at least a first clock signal and a second clock signal; The delay phase-locked loop circuit has its input terminal electrically connected to the output terminal of the clock providing circuit, and is used to receive and generate a first signal in the locked state according to the first clock signal; A voltage-controlled delay circuit is replicated, with the controlled terminal electrically connected to the output terminal of the delay phase-locked loop circuit, for delaying the input clock signal according to the first signal to generate a multi-phase clock signal; A clock correction circuit has a first input terminal and a second input terminal. The first input terminal is electrically connected to the output terminal of the clock providing circuit, and the second input terminal is electrically connected to the output terminal of the replication voltage-controlled delay circuit. The output terminal is electrically connected to the input terminal of the replication voltage-controlled delay circuit. The clock correction circuit is used to compare the phase difference between the second clock signal and the initial phase of the multi-phase clock signal, and dynamically adjust the clock signal output to the replication voltage-controlled delay circuit according to the comparison result until the initial phase of the multi-phase clock signal is aligned with the phase of the second clock signal.

[0006] In one embodiment, the direct flight time sensor includes a time-to-digital converter, and the clock providing circuitry includes: A phase-locked loop circuit is used to generate the system clock; The clock distribution network has an input terminal electrically connected to the output terminal of the phase-locked loop circuit and three output terminals for dividing the system clock into three in-phase clock signals, namely the first clock signal, the second clock signal, and the third clock signal. The input terminal of the time-to-digital converter is electrically connected to the output terminal of the clock distribution network to receive the third clock signal.

[0007] In one embodiment, the time-to-digital converter includes a first counting circuit and a second counting circuit; The third clock signal is used to drive the first counting circuit to measure the integer part of the flight time; The multi-phase clock signal is used to drive the second counting circuit to measure the fractional part of the flight time.

[0008] In one embodiment, the clock correction circuit includes: The phase comparator, with its input terminal electrically connected to the output terminal of the clock providing circuit and the output terminal of the replication voltage-controlled delay circuit, is used to compare the phase difference between the initial phase of the second clock signal and the initial phase of the multi-phase clock signal, and output the corresponding phase deviation signal. The control circuit, with its input terminal electrically connected to the output terminal of the phase comparator, is used to generate a corresponding control signal based on the phase deviation signal. The controllable delay circuit has its input terminal electrically connected to the output terminal of the clock providing circuit, and its controlled terminal electrically connected to the control terminal of the control circuit. It is used to receive and dynamically adjust the delay amount of the second clock signal according to the control signal of the control circuit, so as to generate and output a calibration clock signal to the replication voltage-controlled delay circuit. The control circuit is further configured to output a locking signal to the controllable delay circuit when it receives a detection signal indicating that the phase of the second clock signal output by the phase comparator is aligned with the initial phase of the multi-phase clock signal, so as to lock the delay amount of the second clock signal by the controllable delay circuit.

[0009] In one embodiment, the controllable delay circuit includes: The input terminal of the coarse adjustment delay circuit is electrically connected to the output terminal of the clock supply circuit. The fine-tuning delay circuit has its input terminal electrically connected to the output terminal of the coarse-tuning delay circuit, and its output terminal is the output terminal of the clock correction circuit. The coarse adjustment counting circuit has its input terminal electrically connected to the output terminal of the control circuit and its output terminal electrically connected to the controlled terminal of the coarse adjustment delay circuit. It is used to adjust the delay amount of the coarse adjustment delay circuit according to the received control signal. The fine-tuning counting circuit has its input terminal electrically connected to the output terminal of the control circuit and its output terminal electrically connected to the controlled terminal of the fine-tuning delay circuit. It is used to adjust the delay amount of the fine-tuning delay circuit according to the received control signal. The control circuit is used to adjust the coarse adjustment counting circuit and the fine adjustment counting circuit according to the phase deviation signal, so as to control the delay amount of the coarse adjustment delay circuit and the fine adjustment delay circuit until the phase comparator detects that the phase of the second clock signal is aligned with the initial phase of the multi-phase clock signal.

[0010] In one embodiment, the phase deviation signal includes a left-shift signal and a right-shift signal; When the phase comparator detects that the initial phase of the multi-phase clock signal lags behind the phase of the second clock signal, it outputs a left-shift signal to the control circuit to control the coarse-adjustment counting circuit and / or the fine-adjustment counting circuit to reduce the count value, thereby reducing the total delay. When the phase comparator detects that the initial phase of the multi-phase clock signal leads the phase of the second clock signal, it outputs a right-shift signal to the control circuit to control the coarse-adjustment counting circuit and / or the fine-adjustment counting circuit to increase the count value, thereby increasing the total delay.

[0011] In one embodiment, the phase comparator also outputs a bias-free signal; When the phase comparator detects that the second clock signal is aligned with the initial phase of the multi-phase clock signal, it outputs a no-deviation signal to the control circuit to control the count values ​​of the coarse-adjustment counting circuit and the fine-adjustment counting circuit to remain unchanged, thereby locking the delay amount of the second clock signal.

[0012] In one embodiment, the circuit structure of the replicated voltage-controlled delay circuit is the same as the voltage-controlled delay line structure inside the delay phase-locked loop circuit.

[0013] In one embodiment, the multi-phase clock signal is an N-phase clock, where N is an integer greater than 1.

[0014] In addition, to achieve the above objectives, this application also proposes a direct time-of-flight sensor, including a time-to-digital converter and a clock alignment circuit as described above.

[0015] This application introduces an independent clock correction circuit to form an auxiliary calibration loop. This loop compares and dynamically adjusts the clock signal at the input of the replicated voltage-controlled delay chain, compensating for the inherent delay in the time-locked loop (TLL) transmission path. This ensures high-precision phase alignment between the initial phase of the multi-phase clock signal and the second clock signal used as a reference, thereby eliminating systematic measurement errors introduced by phase offset. By strictly aligning the initial phase of the multi-phase clock signal with the system clock, the accuracy of the measurement reference for the fractional part of the time of flight is ensured, effectively avoiding measurement errors that may occur in the fractional part due to phase misalignment, thus improving the overall ranging accuracy and reliability of the direct time-of-flight sensor. Furthermore, the clock correction circuit is independent of the TLL. The clock correction circuit performs calibration by adjusting the clock signal input to the replicated delay chain without altering the already locked control signals within the TLL. Therefore, it does not disrupt the established stable state of the TLL or the precise intervals between the phases of the multi-phase clock, ensuring the linearity of phase interpolation and the stability of the overall system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a structural diagram of a clock alignment circuit according to a first embodiment of the present invention; Figure 2 This is a structural diagram of a second embodiment of the clock alignment circuit of this utility model; Figure 3 This is a structural diagram of the clock correction circuit of a clock alignment circuit according to the present invention, in embodiment three. Figure 4 This is a structural diagram of the clock correction circuit of embodiment four of the clock alignment circuit of this utility model.

[0018] Reference numerals: Clock providing circuit 01, delay phase-locked loop circuit 02, replication voltage-controlled delay circuit 03, clock correction circuit 04, phase comparator 41, control circuit 42, controllable delay circuit 43, coarse adjustment delay circuit 431, fine adjustment delay circuit 432, coarse adjustment counting circuit 433, fine adjustment counting circuit 434.

[0019] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, if the word "and / or" appears throughout the text, it means including three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0023] This application proposes a clock alignment circuit for use in a direct time-of-flight sensor, comprising: a clock providing circuit 01 for providing multiple synchronized clock signals, the clock signals including at least a first clock signal and a second clock signal; a time-locked loop circuit 02, the input terminal of which is electrically connected to the output terminal of the clock providing circuit 01, for receiving and generating a first signal in a locked state according to the first clock signal; and a voltage-controlled delay circuit 03, the controlled terminal of which is electrically connected to the output terminal of the time-locked loop circuit 02, for delaying the input clock signal according to the first signal to generate a multi-phase clock signal. The clock correction circuit 04 has a first input terminal and a second input terminal. The first input terminal is electrically connected to the output terminal of the clock providing circuit 01, and the second input terminal is electrically connected to the output terminal of the replication voltage-controlled delay circuit 03. The output terminal is electrically connected to the input terminal of the replication voltage-controlled delay circuit 03. The clock correction circuit 04 is used to compare the phase difference between the initial phase of the second clock signal and the initial phase of the multi-phase clock signal, and dynamically adjust the clock signal output to the replication voltage-controlled delay circuit 03 according to the comparison result until the initial phase of the multi-phase clock signal is aligned with the phase of the second clock signal.

[0024] More specifically, the Direct Time-of-Flight (DToF) sensor is a core sensing component in modern high-precision ranging systems. Its basic working principle is to measure the round-trip time (ToF) of a laser pulse from emission to its reflection from the target and back to the receiver. Based on the physical property that the speed of light in air is constant, this time interval can be directly converted into distance information of the target.

[0025] To achieve sub-nanosecond or even picosecond time resolution, DToF sensors typically integrate a high-precision time-to-digital converter (TDC). This TDC employs a hybrid architecture combining coarse and fine counting: the coarse-counting TDC (CTDC) determines the integer part of the time of flight (TOF_INT) by counting an integer number of system clock cycles; while the fine-counting TDC (FTDC) captures the fractional part (TOF_FRAC) that is less than one clock cycle. Combining the integer and fractional parts yields the total time of flight, thus achieving high-resolution time measurement far exceeding the length of a single clock cycle. In this architecture, the measurement accuracy of the FTDC heavily relies on a set of strictly aligned, highly uniformly spaced multi-phase clock signals; this clock sequence essentially acts as a time scale that precisely subdivides a single clock cycle.

[0026] A widely adopted multi-phase clock generation scheme first uses a phase-locked loop (PLL) to generate a high-frequency, low-jitter system master clock, which simultaneously drives the CTDC for integer cycle counting. Then, this system clock is input to a delay-locked loop (DLL). The DLL's delay-locking function precisely divides a single clock cycle into multiple equally spaced phases, thereby generating the required multi-phase clock signal specifically for fractional-time interpolation in the FTDC. Ideally, the starting phase (often denoted as PH0) of the multi-phase clock sequence generated by the DLL should be strictly aligned with the reference edge of the original system clock to ensure seamless connection between the integer cycles measured by the CTDC and the fractional cycles measured by the FTDC on the time axis, forming a continuous total flight time without reference deviation.

[0027] However, in actual integrated circuit implementation, such ideal alignment is difficult to achieve naturally. After the system clock signal is output from the clock source, it must pass through the input buffer circuit, control logic, and voltage-controlled delay chain within the DLL before finally outputting the multi-phase clock. Parasitic capacitance, gate delay, and other inherent circuit delays present in this complete signal path will cause the overall multi-phase clock sequence output by the DLL to have a fixed phase lead or lag offset, resulting in the initial phase PH0 being unable to keep synchronized with the original system clock. This phase misalignment problem will directly disrupt the reference consistency between CTDC and FTDC, causing timing splicing errors.

[0028] The consequences of this deviation are severe. When measuring the fractional part of the time of flight, due to the phase discrepancy between the FTDC measurement reference PH0 and the system clock used by the CTDC, the final measured fractional time TOF_FRAC will contain a systematic error. In extreme cases, when the fractional part of the actual time of flight approaches the boundary of a clock cycle, this phase discrepancy may cause a huge error in the FTDC output, approaching the length of a whole cycle. This results in a severely distorted distance value, greatly affecting the ranging accuracy and reliability of the DToF sensor.

[0029] Therefore, resolving the alignment issue between the initial phase of the multi-phase loop (DLL) and the system clock has become a key technical challenge for improving the performance of DToF sensors. To this end, this application proposes a clock alignment circuit designed to address the phase misalignment problem between the multi-phase clock reference and the system clock reference in high-precision time measurement systems. The clock alignment circuit includes a clock providing circuit 01, a delay phase-locked loop circuit 02, a replica voltage control delay line (Replica VCDL) circuit 03, and a clock correction circuit 04 (DESKEW).

[0030] The entire system begins operation with clock supply circuit 01. This circuit, acting as the system's clock source, is responsible for generating at least two synchronized clock signals: a first clock signal and a second clock signal. Synchronization means that these two signals originate from the same clock reference and have a known and stable phase relationship. The first clock signal serves as the initial input for generating the multi-phase clock; while the second clock signal serves as the phase reference for clock correction circuit 04, used to determine whether the initial phase of the multi-phase clock is aligned with the system clock.

[0031] The delay-locked loop (DLL) circuit 02 receives the first clock signal from the clock supply circuit 01 and measures the physical length of one clock cycle. Internally, the DLL contains a voltage-controlled delay chain that dynamically adjusts the total delay of the delay chain through a negative feedback control loop, making it exactly equal to the cycle of one input clock. When the loop is locked, the DLL outputs a first signal, typically a voltage signal, which represents the total delay corresponding to one clock cycle. This can be understood as a calibrated "ruler" representing unit time.

[0032] Next, the replicated voltage-controlled delay circuit 03 uses this "ruler" to generate the required "scale," namely, a multi-phase clock signal. The replicated voltage-controlled delay circuit 03 is a complete replica of the internal delay chain structure of the DLL, applying the first signal output by the DLL as a control quantity to itself, thereby ensuring that the delay of each delay unit is exactly the same as that of the internal unit of the DLL. When a clock signal passes through this replicated delay chain, it generates a series of clock signals with uniformly spaced phases at its various tap outputs. It is worth noting that the name "replicated voltage-controlled delay circuit 03" in this application is used for descriptive convenience; its essence is a complete replica of the internal delay chain structure of the DLL, therefore its specific functions and roles will not be elaborated here.

[0033] However, due to the unavoidable inherent delay in the path of the clock signal from the source to the DLL input and then to the replication chain output, the initial phase of the final multi-phase clock sequence will have a fixed phase deviation from the second clock signal, which serves as the ideal reference. This deviation is the key factor affecting measurement accuracy.

[0034] To address the aforementioned deviation, this application introduces a clock correction circuit 04. This circuit forms an independent auxiliary calibration loop specifically designed to eliminate this fixed phase deviation. Its operation follows a typical closed-loop feedback control process: the two inputs of the clock correction circuit 04 are respectively connected to a second clock signal serving as a reference and the initial phase of the multi-phase clock signal to be calibrated, and the phase difference between the two is continuously compared. Based on the detected phase difference (leading or lagging), a correction clock signal is generated. It is noteworthy that the clock correction circuit 04 does not directly change the calibrated first signal output by the DLL, but rather dynamically adjusts the phase of the clock signal output to the replication voltage-controlled delay circuit 03.

[0035] Specifically, clock correction circuit 04 intervenes in the path of the clock signal to the replication delay chain. By fine-tuning the phase of the clock signal fed into the replication chain, it is equivalent to adding an adjustable compensation delay to the entire signal path. Under the action of the calibration loop, this compensation amount is automatically adjusted to exactly cancel out the inherent path delay. When the loop is stable, the initial phase of the multi-phase clock will achieve high-precision phase alignment with the second clock signal.

[0036] This application introduces an independent clock correction circuit 04 to form an auxiliary calibration loop. This loop compares and dynamically adjusts the clock signal at the input of the replicated voltage-controlled delay chain, compensating for the inherent delay in the time-locked loop (TLL) transmission path. This ensures high-precision phase alignment between the initial phase of the multi-phase clock signal and the second clock signal used as a reference, thereby eliminating systematic measurement errors introduced by phase offset. By strictly aligning the initial phase of the multi-phase clock signal with the system clock, the accuracy of the measurement reference for the fractional part of the time of flight is ensured, effectively avoiding measurement errors that may occur in the fractional part due to phase misalignment, and improving the overall ranging accuracy and reliability of the direct time-of-flight sensor. Furthermore, the clock correction circuit 04 is independent of the TLL. The clock correction circuit 04 performs calibration by adjusting the clock signal input to the replicated delay chain without altering the already locked control signals within the TLL. Therefore, it does not disrupt the established stable state of the TLL or the precise intervals between the phases of the multi-phase clock, ensuring the linearity of phase interpolation and the stability of the overall system.

[0037] In one embodiment, the direct flight time sensor includes a time-to-digital converter, and the clock providing circuit 01 includes: A phase-locked loop circuit is used to generate the system clock; a clock distribution network, with its input terminal electrically connected to the output terminal of the phase-locked loop circuit, has three output terminals and is used to divide the system clock into three in-phase clock signals, namely a first clock signal, a second clock signal, and a third clock signal. The input terminal of the time-to-digital converter is electrically connected to the output terminal of the clock distribution network to receive the third clock signal.

[0038] In this embodiment, the clock providing circuit 01 comprises a phase-locked loop (PLL) circuit and a clock distribution network, which together ensure that the entire system has a unified, clean, and synchronized clock source. The PLL circuit generates a stable system clock (CLK). The clock distribution network distributes the single CLK signal losslessly and synchronously. To achieve synchronization, the distribution network typically employs a fully symmetrical buffer chain design, ensuring that the signal travels through a completely consistent path delay. The clock distribution network distributes the single CLK signal into three clock signals of the same origin and in phase: the first clock signal DLL_CLK, the second clock signal DSK_CLK, and the third clock signal TDC_CLK.

[0039] Specifically, the first clock signal, DLL_CLK, is fed into the delay-locked loop circuit 02. DLL adjusts the total delay of its voltage-controlled delay chain through its internal feedback loop, making it exactly equal to one cycle of DLL_CLK. After locking, DLL outputs a control signal that represents the length of "one unit of time".

[0040] The second clock signal, DSK_CLK, serves as the reference clock for the clock correction circuit 04. The control signal generated by the DLL drives a replica delay chain that perfectly matches its internal delay chain. When a clock signal passes through this replica chain, it generates multi-phase clock outputs at each tap. However, due to physical path delays, the initial phase (PH0) of these multi-phase clocks will have a fixed deviation from the original DSK_CLK reference. The clock correction circuit 04 adjusts the second clock signal DSK_CLK by continuously comparing the phase difference between the initial phase (PH0) of the multi-phase clocks output by the replica chain and the reference DSK_CLK, and generates a correction clock signal VCDL_CLK for the replica voltage-controlled delay circuit 03, indirectly "pulling" PH0 back to a position aligned with DSK_CLK. When precise alignment is achieved, the loop locks.

[0041] The third clock signal, TDC_CLK, is directly provided to the coarse counting circuit in the time-to-digital converter (CTDC). CTDC uses the rising edge of TDC_CLK to count the number of complete clock cycles that have elapsed during the laser's flight, thereby determining the integer part of the flight time (TOF_INT).

[0042] Since TDC_CLK, DLL_CLK, and DSK_CLK are synchronized from the source, when PH0 is aligned with DSK_CLK, it means that the starting point of the multiphase clock used for fine counting is perfectly aligned with the clock edge of TDC_CLK used for coarse counting. This ensures that the time-to-digital converter can seamlessly and accurately stitch together the integer and fractional parts of the measurement results, thereby obtaining an ultra-high precision total time-of-flight measurement, laying a solid foundation for the DToF sensor to achieve excellent ranging performance.

[0043] In one embodiment, the time-to-digital converter includes a first counting circuit and a second counting circuit; a third clock signal is used to drive the first counting circuit to measure the integer part of the flight time; and a multi-phase clock signal is used to drive the second counting circuit to measure the fractional part of the flight time.

[0044] Based on the above embodiments and background technology, for ease of description, this application defines the coarse counting TDC (CTDC) of the time-to-digital converter as a first counting circuit and the fine counting TDC (FTDC) of the time-to-digital converter as a second counting circuit. It can be understood that "first counting circuit" and "coarse counting TDC" are different expressions of the same meaning in this application, and "second counting circuit" and "fine counting TDC" are different expressions of the same meaning.

[0045] The first counting circuit, often referred to as the coarse counting circuit, is driven by the third clock TDC_CLK and measures the integer portion of the time of flight. The operation of this circuit is relatively straightforward: it is essentially a high-speed counter that counts complete cycles of the third clock signal, starting from the initial emission of the laser pulse. Each counted clock cycle represents a fixed, relatively large unit of time (e.g., corresponding to a distance of several centimeters or even tens of centimeters). The counter stops operating when a laser pulse reflected from the target is received. The final count value, the number of integer clock cycles, forms the main framework and fundamental value (TOF_INT) for the time of flight measurement. This value determines the "approximate range" of the distance.

[0046] However, the actual flight time is rarely exactly an integer multiple of the clock cycle; it almost always contains a fractional part less than one clock cycle. Measuring this tiny time difference is the task of the second counting circuit, often referred to as the fine counter. The driving clock for the second counting circuit is not a single signal, but rather a set of multi-phase clock signals generated by the replicated voltage-controlled delay circuit 03. This set of clocks effectively subdivides the clock cycle used by the first counting circuit along the time axis.

[0047] The second counting circuit works more like a high-speed "time encoder." When the echo signal arrives, the circuit instantly captures and latches the state of the current multi-phase clock group. By identifying which specific phase clock is active at the moment the echo arrives, it can accurately determine which tiny time interval within the current clock cycle the echo falls into. This latched state is then decoded to obtain the fractional part of the time of flight (TOF_FRAC).

[0048] The coordinated operation of both circuits is key to achieving high accuracy. The entire time-of-flight measurement process can be visualized as follows: the first counting circuit measures the clock period, while the second counting circuit measures the phase. Finally, the system adds the integer and fractional part measurements to obtain a complete and high-resolution time-of-flight value. Therefore, the success of this dual-counting circuit architecture depends on one prerequisite: the clock used for coarse counting (the third clock signal) and the starting point (PH0) of the multi-phase clock used for fine counting must be strictly aligned. In conjunction with the above embodiments, this application utilizes a clock correction circuit 04 to align the phase of the second clock signal with the initial phase of the multi-phase clock signal, thereby aligning the phase of the third clock signal with the initial phase of the multi-phase clock signal.

[0049] In one embodiment, the clock correction circuit 04 includes: Phase comparator 41, with its input terminal electrically connected to the output terminal of the clock providing circuit 01 and the output terminal of the replication voltage-controlled delay circuit 03, is used to compare the phase difference between the initial phase of the second clock signal and the multi-phase clock signal, and output a corresponding phase deviation signal; control circuit 42, with its input terminal electrically connected to the output terminal of the phase comparator 41, is used to generate a corresponding control signal based on the phase deviation signal; controllable delay circuit 43, with its input terminal electrically connected to the output terminal of the clock providing circuit 01 and its controlled terminal electrically connected to the control terminal of the control circuit 42, is used to receive and dynamically adjust the delay amount of the second clock signal according to the control signal of the control circuit 42, so as to generate and output a calibration clock signal to the replication voltage-controlled delay circuit 03; The control circuit 42 is further configured to output a locking signal to the controllable delay circuit 43 when it receives a detection signal that the phase of the second clock signal output by the phase comparator 41 is aligned with the initial phase of the multi-phase clock signal, so as to lock the delay amount of the second clock signal by the controllable delay circuit 43.

[0050] This embodiment's clock correction circuit 04 can be understood as including a phase comparator 41, a control circuit 42, and a controllable delay circuit 43. The phase comparator 41 has two inputs: one receives the second clock signal (DSK_CLK) from the clock distribution network; the other receives the initial phase (PH0) of the multi-phase clock signal fed back from the output of the replication voltage-controlled delay circuit 03. The phase comparator 41 continuously and with high precision compares the phase relationship between these two signals, determining whether PH0 leads or lags DSK_CLK, and quantifies the magnitude of this phase difference. This abstract phase difference is converted into a concrete phase deviation signal that can be processed by subsequent circuits.

[0051] The control circuit 42 receives the phase deviation signal from the phase comparator 41 and analyzes and makes decisions accordingly. Internally, it typically contains a state machine or logic algorithm to interpret the deviation information and generate corresponding control signals with a specific purpose. For example, if the phase comparator 41 reports PH0 as lagging, the control circuit 42 issues an "accelerate" command, instructing the execution unit to reduce the delay; conversely, it increases the delay. Its function is to ensure that the entire adjustment process is stable and convergent, avoiding over-adjustment or unstable back-and-forth oscillations. Furthermore, based on continuously input signals, the control circuit 42 determines that the phase difference between PH0 and DSK_CLK has narrowed to an acceptable range, i.e., they are aligned, and then generates a lock signal.

[0052] The controllable delay circuit 43 is a circuit whose delay can be precisely controlled by an external signal, such as a digitally controlled delay line or a voltage-controlled delay line. The input receives two clock signals (DSK_CLK), while the control terminal receives instructions to control circuit 42. Based on the control signals, the controllable delay circuit 43 dynamically and precisely adjusts its internal delay time, thereby changing the phase of its output clock. This real-time calibrated clock signal is then fed into the replica voltage-controlled delay circuit 03 as a reference for generating a multi-phase clock.

[0053] The working principle of the entire closed-loop calibration process is as follows: After system startup, the DLL locks independently first, and the replication chain begins generating multi-phase clocks. However, due to inherent delays in the signal path, an initial deviation exists between PH0 and the reference DSK_CLK. Phase comparator 41 immediately detects this deviation. The phase deviation signal is sent to control circuit 42, which, after judgment, issues an adjustment command to controllable delay circuit 43. Controllable delay circuit 43 changes its delay amount for DSK_CLK according to the command. This change in delay directly causes a phase shift in the calibration clock signal input to the replication chain, thereby causing a phase synchronization shift in the overall phase of all multi-phase clocks (including PH0) generated by the replication chain. This changed PH0 is fed back to phase comparator 41 for a new round of comparison with DSK_CLK.

[0054] The above process repeats continuously, forming a negative feedback closed loop. Control circuit 42 continuously fine-tunes, gradually "pulling" PH0 towards the position aligned with DSK_CLK. Once precisely aligned, control circuit 42 immediately issues a lock signal, freezing the current state of controllable delay circuit 43 and maintaining its current delay. At this point, the calibration loop enters a static locked state, ensuring the long-term uniformity and stability of the timing reference of the entire measurement system.

[0055] In one embodiment, the controllable delay circuit 43 includes: The coarse-adjustment delay circuit 431 has its input terminal electrically connected to the output terminal of the clock providing circuit 01; the fine-adjustment delay circuit 432 has its input terminal electrically connected to the output terminal of the coarse-adjustment delay circuit 431, and its output terminal is the output terminal of the clock correction circuit 04; the coarse-adjustment counting circuit 433 has its input terminal electrically connected to the output terminal of the control circuit 42, and its output terminal electrically connected to the controlled terminal of the coarse-adjustment delay circuit 431, used to adjust the delay amount of the coarse-adjustment delay circuit 431 according to the received control signal; the fine-adjustment counting circuit 434 has its input terminal electrically connected to the output terminal of the control circuit 42, and its output terminal electrically connected to the controlled terminal of the fine-adjustment delay circuit 432, used to adjust the delay amount of the fine-adjustment delay circuit 432 according to the received control signal; The control circuit 42 is used to adjust the coarse adjustment counting circuit 433 and the fine adjustment counting circuit 434 according to the phase deviation signal, so as to control the delay amount of the coarse adjustment delay circuit 431 and the fine adjustment delay circuit 432 until the phase comparator 41 detects that the phase of the second clock signal is aligned with the initial phase of the multi-phase clock signal.

[0056] In this embodiment, the controllable delay circuit 43 includes a coarse-adjustment delay circuit 431, a fine-adjustment delay circuit 432, a coarse-adjustment counting circuit 433, and a fine-adjustment counting circuit 434. The coarse-adjustment delay circuit 431 is characterized by a relatively large delay step size. This means that each adjustment results in a significant phase change, quickly covering a large delay range. The corresponding coarse-adjustment counting circuit 433 is a counter that receives instructions from the control circuit 42. The control circuit 42 issues instructions to the coarse-adjustment counting circuit 433 based on the large phase deviation signal output by the phase comparator 41. The output value of the counter directly controls the coarse-adjustment delay circuit 431, determining how many "large step size" basic delay units it introduces.

[0057] At the start of the calibration process, if the phase deviation is large, the control circuit 42 will prioritize driving the coarse adjustment counting circuit 433, causing the coarse adjustment delay circuit 431 to rapidly increase or decrease its total delay. This is equivalent to quickly pulling the two signals that need to be aligned to a position very close to each other, completing the phase "coarse aiming" or "capture" process, and efficiently eliminating most of the initial deviation.

[0058] The fine-tuning delay circuit 432 is connected in series after the coarse-tuning delay circuit 431 and receives its output. Its key feature is a relatively fine delay step size, with its minimum adjustment amount being much smaller than the coarse-tuning step size. Therefore, it can perform very fine phase adjustments. The corresponding fine-tuning counter circuit 434 is also a counter controlled by the control circuit 42, but the delay change brought about by each step it controls is extremely small. When the coarse-tuning process reduces the phase deviation to within the adjustment range of the fine-tuning delay circuit 432, the control circuit 42 switches its strategy to focus on fine-tuning. Based on the residual minute deviation detected by the phase comparator 41, it issues a fine adjustment command to the fine-tuning counter circuit 434. The fine-tuning delay circuit 432 then subtly increases or decreases the delay amount, gradually reducing the phase difference between the two signals to near zero, achieving the final "fine aiming" and "locking."

[0059] The control circuit 42 first determines that the phase deviation is large, and then primarily drives the coarse adjustment counting circuit 433 to make a large adjustment. The total delay of the coarse adjustment delay circuit 431 changes rapidly, causing the initial phase of the feedback multi-phase clock to quickly approach the reference clock. When the phase deviation enters the fine adjustment range, the control circuit 42 switches to fine mode, driving the fine adjustment counting circuit 434 to make small step adjustments. Each adjustment step more accurately reduces the residual error. Throughout the process, the control circuit 42 may need to coordinate some actions between coarse and fine adjustments according to the actual situation to ensure smooth convergence of the entire process. Finally, when the phase comparator 41 detects alignment, the control circuit 42 stops sending adjustment commands, the values ​​of the coarse and fine counting circuits are locked, and the total delay of the entire controllable delay circuit 43 is fixed, completing the calibration.

[0060] In one embodiment, the phase deviation signal includes a left-shift signal and a right-shift signal; When the phase comparator 41 detects that the initial phase of the multi-phase clock signal lags behind the phase of the second clock signal, it outputs a left-shift signal to the control circuit 42 to control the coarse-adjustment counting circuit 433 and / or the fine-adjustment counting circuit 434 to decrease the count value, thereby reducing the total delay; when the phase comparator 41 detects that the initial phase of the multi-phase clock signal leads the phase of the second clock signal, it outputs a right-shift signal to the control circuit 42 to control the coarse-adjustment counting circuit 433 and / or the fine-adjustment counting circuit 434 to increase the count value, thereby increasing the total delay.

[0061] This can be understood as the total delay of the entire delay line being equal to the sum of the delay of the coarse adjustment counter circuit 433 and the delay of the fine adjustment counter circuit 434. The fine adjustment counter circuit 434 provides a large adjustment span while providing fine adjustment capability. When the system starts working, DESKEW is in an unlocked state (DSK_LOCK=0), indicating that phase alignment is not yet complete and the calibration loop is in an active adjustment mode.

[0062] Subsequently, the phase comparator 41 (PD) continuously monitors the sequence of the reference clock DSK_CLK and the initial phase PH0 of the feedback multi-phase clock. The output of the PD consists of two key control signals: LS (left shift / lag signal) and RS (right shift / lead signal). Their function is to report the current phase error direction to the system. When the PD detects that the edge of PH0 occurs later than the edge of DSK_CLK, it outputs LS=1 (while RS=0). This signal is interpreted as: the current total delay is too large and needs to be reduced. Upon receiving LS=1, the control logic commands the counter to decrease its count value. The decrease in the count value means that the delay line is commanded to reduce the number of active delay units inside it, thereby reducing the total delay. As a result, the clocks arriving later in the replication delay chain will be advanced, causing the generated PH0 phase to shift forward (to the left) to catch up with the DSK_CLK phase.

[0063] Conversely, when the PD detects that the edge of PH0 occurs earlier than the edge of DSK_CLK, it outputs RS=1 (and LS=0 simultaneously). This signal means that the current total delay is insufficient and needs to be increased. Therefore, the control logic commands the counter to increment its count. The increased count introduces more delay into the delay lines, increasing the total delay. This delays the clock arriving at the replication chain, forcing the phase of PH0 to shift backward (to the right) until the phase of DSK_CLK catches up.

[0064] It is worth noting that the opposite control logic, i.e., increasing the count value when LS=1 and decreasing the count value when RS=1, is physically equally feasible. This depends on the conventions of circuit design, i.e., whether "increasing the delay" is defined as lagging or leading the phase. As long as the negative feedback relationship of the entire closed loop holds—the detected error drives the system to act in order to eliminate the error—the system can function normally. The above description uses the first convention.

[0065] The above adjustment process continues within each clock cycle. Based on the comparison result from the PD, the counter increases or decreases its count step-by-step, finely controlling the total delay. This negative feedback loop causes the phase of PH0 to continuously and gradually "approach" the phase of DSK_CLK. Finally, when the phase difference between PH0 and DSK_CLK is reduced to a point that the PD cannot distinguish, the PD stops outputting the LS or RS signal (i.e., LS=0 and RS=0). At this point, the system determines that the phase is precisely aligned. Therefore, the control logic sets the output signal DSK_LOCK to 1, indicating that the locking is complete.

[0066] In one embodiment, the phase comparator 41 also outputs a bias-free signal; When the phase comparator 41 detects that the second clock signal is aligned with the initial phase of the multi-phase clock signal, it outputs a no-deviation signal to the control circuit 42 to control the count values ​​of the coarse adjustment counting circuit 433 and the fine adjustment counting circuit 434 to remain unchanged, so as to lock the delay amount of the second clock signal.

[0067] This can be understood as follows: after the delay adjustment in the above embodiment, the system determines that the phase is precisely aligned. Therefore, the control logic sets the output signal DSK_LOCK to 1. DSK_LOCK=1 directly acts on the coarse adjustment counter circuit 433 and the fine adjustment counter circuit 434. Before this signal takes effect, these two counters continuously increment and decrement under the command of the control circuit 42. Now, the DSK_LOCK signal locks these two counters. The counters stop responding to any adjustment commands, and their current count values ​​are continuously maintained. Since the delay amounts of the coarse and fine delay lines are entirely controlled by the output values ​​of these two counters, the freezing of the counters means that the total delay amount of the entire controllable delay circuit 43 is locked. Before (DSK_LOCK=0): The system is in dynamic adjustment mode. The phase comparator 41, control circuit 42, counters, and delay lines form an active negative feedback loop, continuously searching for the optimal alignment point. After (DSK_LOCK=1): The system enters static locking mode. The feedback loop is interrupted, all adjustable components are fixed, and the previously calibrated optimal delay amount is maintained. The phase of the calibration clock signal output to the replication delay chain is stabilized to be precisely aligned with the system reference DSK_CLK.

[0068] In one embodiment, the circuit structure of the replicated voltage-controlled delay circuit 03 is the same as the voltage-controlled delay line structure inside the delay phase-locked loop circuit 02.

[0069] This can be understood as follows: the voltage-controlled delay line inside the delay phase-locked loop circuit 02 precisely delays the input clock in multiple phases to generate a series of phase clocks (PH0, PH1, ... PHn) required for TDC measurement. This is the "main battlefield" for performing the core functions. The purpose of replicating the voltage-controlled delay circuit 03 is to simulate or mirror the delay characteristics of the delay phase-locked loop circuit 02. It is designed to be as identical as possible to the main path in terms of circuit structure, transistor size, layout, and routing.

[0070] During the locking process, the DLL generates a stable control voltage (Vctrl). The magnitude of this voltage precisely determines the delay amount of each delay unit in the main voltage-controlled delay line. A crucial step is that this identical control voltage (Vctrl) is also simultaneously applied to the replica voltage-controlled delay circuit 03. Because the replica circuit is physically identical to the main circuit and is controlled by the same control voltage, the delay generated by the replica circuit (i.e., the delay from DSK_CLK to PH0) will be highly precisely equal to the delay of any stage in the DLL's delay chain (e.g., the delay from PH0 to PH1).

[0071] The clock correction circuit 04 calibrates precisely this path delay, simulated by the replication circuit and perfectly matching the main path. Compensating for this "mirror delay" using the controllable delay circuit 43 is equivalent to indirectly and accurately compensating for the actual delay on the main path. This is because any factor affecting the main path delay will affect the replication path in the same way.

[0072] The delay-locked loop (PLL) circuit 02 automatically compensates for all fixed delays between the clock input port of the DLL, through the buffer and wiring, and to the start of the voltage-controlled delay chain where timing actually begins. These delays cannot be eliminated by the DLL itself. For the TDC, the measurement accuracy directly depends on the accuracy and stability of the delay amount of each delay unit. Through this replication structure, the DESKEW loop ensures that the interval between each phase clock used by the downstream TDC is highly consistent with the ideal value set when the DLL is locked. This reduces gain errors caused by PVT variations and ensures the measurement linearity and accuracy of the TDC throughout the entire operating environment. Even if there are fluctuations in ambient temperature or ripples in the power supply voltage, as long as the changes in the main path and the replication path are synchronous and consistent, the correction relationship still holds, and the system can maintain the locked state, exhibiting extremely strong robustness.

[0073] In one embodiment, the multi-phase clock signal is an N-phase clock, where N is an integer greater than 1. This can be understood as the DLL receiving a reference clock (e.g., TDC_CLK, with a period of 2ns) and inputting it into a voltage-controlled delay chain consisting of N identical delay units. Each delay unit generates a small, fixed delay. Ideally, when the DLL is locked, the total delay of the entire delay chain is exactly equal to one reference clock period (2ns). Therefore, the delay (Td) generated by each delay unit is equal to the clock period divided by the number of stages, i.e., Td = Tclk / N.

[0074] In this way, the DLL generates N clock phases PH0, PH1, PH2, ..., PH(N-1) evenly distributed along the time axis. For example, when N=16, a "time ruler" with a minimum scale of 2ns / 16 = 125ps is obtained. The subsequent measurement logic of TDC achieves precise time interval measurement by detecting which phase interval the measured signal falls into. The larger the value of N, the denser the scale of this ruler, and the higher the theoretical original measurement accuracy. Without the DLL, the delay of this delay chain would be strongly affected by process, voltage, and temperature fluctuations. For example, an increase in voltage or a decrease in temperature would make the transistor speed faster and the delay Td smaller; conversely, Td would increase. This would cause the scale of the "time ruler" to fluctuate wildly, making the measurement results completely unreliable.

[0075] The DLL dynamically adjusts the control voltage of the delay chain through a negative feedback loop, forcing the total delay to lock onto a single clock cycle. This ensures that the delay Td of each stage remains stable at Tclk / N regardless of changes in the external environment. A fundamental flaw in conventional TDCs containing only the DLL is that they can only guarantee the accurate relative spacing between phases "within" the delay chain, but cannot guarantee the absolute alignment between the first phase (PH0) and the system reference clock (DSK_CLK). This is because the clock signal travels from the input port to the start of the DLL delay chain through buffers, clock trees, and traces, creating a fixed insertion delay that is also affected by PVT. This delay causes an unknown, drifting phase deviation of PH0 relative to the original DSK_CLK.

[0076] Therefore, this application adds a clock correction circuit 04 and a replication voltage-controlled delay circuit 03 to the conventional DLL to actively measure and compensate for this insertion delay, and finally align PH0 and DSK_CLK precisely.

[0077] Furthermore, to achieve the above objectives, this application also proposes a direct time-of-flight sensor, including a time-to-digital converter and a clock alignment circuit as described in all the embodiments above. The clock alignment circuit includes a clock providing circuit 01, a delay phase-locked loop circuit 02, a replication voltage-controlled delay circuit 03, and a clock correction circuit 04.

[0078] This application introduces an independent clock correction circuit 04 to form an auxiliary calibration loop. This loop compares and dynamically adjusts the clock signal at the input of the replicated voltage-controlled delay chain, compensating for the inherent delay in the time-locked loop (TLL) transmission path. This ensures high-precision phase alignment between the initial phase of the multi-phase clock signal and the second clock signal used as a reference, thereby eliminating systematic measurement errors introduced by phase offset. By strictly aligning the initial phase of the multi-phase clock signal with the system clock, the accuracy of the measurement reference for the fractional part of the time of flight is ensured, effectively avoiding measurement errors that may occur in the fractional part due to phase misalignment, and improving the overall ranging accuracy and reliability of the direct time-of-flight sensor. Furthermore, the clock correction circuit 04 is independent of the TLL. The clock correction circuit 04 performs calibration by adjusting the clock signal input to the replicated delay chain without altering the already locked control signals within the TLL. Therefore, it does not disrupt the established stable state of the TLL or the precise intervals between the phases of the multi-phase clock, ensuring the linearity of phase interpolation and the stability of the overall system.

[0079] The above embodiments are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A clock alignment circuit applied to a direct time-of-flight sensor, characterized in that, include: A clock providing circuit is used to provide multiple synchronized clock signals, the clock signals including at least a first clock signal and a second clock signal; The delay phase-locked loop circuit has its input terminal electrically connected to the output terminal of the clock providing circuit, and is used to receive and generate a first signal in the locked state according to the first clock signal; A voltage-controlled delay circuit is replicated, with the controlled terminal electrically connected to the output terminal of the delay phase-locked loop circuit, for delaying the input clock signal according to the first signal to generate a multi-phase clock signal; A clock correction circuit has a first input terminal and a second input terminal. The first input terminal is electrically connected to the output terminal of the clock providing circuit, and the second input terminal is electrically connected to the output terminal of the replication voltage-controlled delay circuit. The output terminal is electrically connected to the input terminal of the replication voltage-controlled delay circuit. The clock correction circuit is used to compare the phase difference between the second clock signal and the initial phase of the multi-phase clock signal, and dynamically adjust the clock signal output to the replication voltage-controlled delay circuit according to the comparison result until the initial phase of the multi-phase clock signal is aligned with the phase of the second clock signal.

2. The clock alignment circuit as described in claim 1, characterized in that, The direct flight time sensor includes a time-to-digital converter, and the clock providing circuitry includes: A phase-locked loop circuit is used to generate the system clock; The clock distribution network has an input terminal electrically connected to the output terminal of the phase-locked loop circuit and three output terminals for dividing the system clock into three in-phase clock signals, namely the first clock signal, the second clock signal, and the third clock signal. The input terminal of the time-to-digital converter is electrically connected to the output terminal of the clock distribution network to receive the third clock signal.

3. The clock alignment circuit as described in claim 2, characterized in that, The time-to-digital converter includes a first counting circuit and a second counting circuit; The third clock signal is used to drive the first counting circuit to measure the integer part of the flight time; The multi-phase clock signal is used to drive the second counting circuit to measure the fractional part of the flight time.

4. The clock alignment circuit as described in claim 1, characterized in that, The clock correction circuit includes: The phase comparator, with its input terminal electrically connected to the output terminal of the clock providing circuit and the output terminal of the replication voltage-controlled delay circuit, is used to compare the phase difference between the initial phase of the second clock signal and the initial phase of the multi-phase clock signal, and output the corresponding phase deviation signal. The control circuit, with its input terminal electrically connected to the output terminal of the phase comparator, is used to generate a corresponding control signal based on the phase deviation signal. The controllable delay circuit has its input terminal electrically connected to the output terminal of the clock providing circuit, and its controlled terminal electrically connected to the control terminal of the control circuit. It is used to receive and dynamically adjust the delay amount of the second clock signal according to the control signal of the control circuit, so as to generate and output a calibration clock signal to the replication voltage-controlled delay circuit. The control circuit is further configured to output a locking signal to the controllable delay circuit when it receives a detection signal indicating that the phase of the second clock signal output by the phase comparator is aligned with the initial phase of the multi-phase clock signal, so as to lock the delay amount of the second clock signal by the controllable delay circuit.

5. The clock alignment circuit as described in claim 4, characterized in that, The controllable delay circuit includes: The input terminal of the coarse adjustment delay circuit is electrically connected to the output terminal of the clock supply circuit. The fine-tuning delay circuit has its input terminal electrically connected to the output terminal of the coarse-tuning delay circuit, and its output terminal is the output terminal of the clock correction circuit. The coarse adjustment counting circuit has its input terminal electrically connected to the output terminal of the control circuit and its output terminal electrically connected to the controlled terminal of the coarse adjustment delay circuit. It is used to adjust the delay amount of the coarse adjustment delay circuit according to the received control signal. The fine-tuning counting circuit has its input terminal electrically connected to the output terminal of the control circuit and its output terminal electrically connected to the controlled terminal of the fine-tuning delay circuit. It is used to adjust the delay amount of the fine-tuning delay circuit according to the received control signal. The control circuit is used to adjust the coarse adjustment counting circuit and the fine adjustment counting circuit according to the phase deviation signal, so as to control the delay amount of the coarse adjustment delay circuit and the fine adjustment delay circuit until the phase comparator detects that the phase of the second clock signal is aligned with the initial phase of the multi-phase clock signal.

6. The clock alignment circuit as described in claim 5, characterized in that, The phase deviation signal includes a left shift signal and a right shift signal; When the phase comparator detects that the initial phase of the multi-phase clock signal lags behind the phase of the second clock signal, it outputs a left-shift signal to the control circuit to control the coarse-adjustment counting circuit and / or the fine-adjustment counting circuit to reduce the count value, thereby reducing the total delay. When the phase comparator detects that the initial phase of the multi-phase clock signal leads the phase of the second clock signal, it outputs a right-shift signal to the control circuit to control the coarse-adjustment counting circuit and / or the fine-adjustment counting circuit to increase the count value, thereby increasing the total delay.

7. The clock alignment circuit as described in claim 6, characterized in that, The phase comparator also outputs a bias-free signal; When the phase comparator detects that the second clock signal is aligned with the initial phase of the multi-phase clock signal, it outputs a no-deviation signal to the control circuit to control the count values ​​of the coarse-adjustment counting circuit and the fine-adjustment counting circuit to remain unchanged, thereby locking the delay amount of the second clock signal.

8. The clock alignment circuit as described in claim 1, characterized in that, The circuit structure of the replicated voltage-controlled delay circuit is the same as the voltage-controlled delay line structure inside the delay phase-locked loop circuit.

9. The clock alignment circuit as described in any one of claims 1-8, characterized in that, The multi-phase clock signal is an N-phase clock, where N is an integer greater than 1.

10. A direct time-of-flight sensor, characterized in that, It includes a time-to-digital converter and a clock alignment circuit as described in any one of claims 1-9.

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