Low-power compressed additional memory modules and motherboard components

Abstract

This application provides a low-power compressed additional memory module and a motherboard device. The low-power compressed additional memory module includes: a circuit board with at least one memory region, each memory region having pads arranged in an array; at least one memory chip, each memory chip including solder balls arranged in an array, each memory chip being disposed in a corresponding memory region and connected to a corresponding pad through the solder balls. The low-power compressed additional memory module provided by this application enables diverse designs of low-power compressed additional memory modules.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a low-power compressed additional memory module and motherboard device. Background Technology

[0002] The Joint Electron Device Engineering Council (JEDEC) has released Low Power Double Data Rate SynchronousDRAM Compression-Attached Memory Modules (LPDDR5 / 5X SDRAM CAMM2s), which are known for their low power consumption and small size and are specifically designed for use in mobile electronic devices.

[0003] However, the LPDDR5 / 5X CAMM2 (LP5CAMM2) module in the JESD 318 standard developed by JEDEC can only support memory chips of specific specifications, resulting in low flexibility in module design and difficulty in meeting the needs of diverse mobile devices. Utility Model Content

[0004] The purpose of this application is to provide a low-power compressed additional memory module and motherboard device, which can realize the diversified design of the low-power compressed additional memory module.

[0005] In a first aspect, this application provides a low-power compressed additional memory module, comprising: a circuit board having at least one memory region, each memory region having pads arranged in an array; at least one memory chip, each memory chip including solder balls arranged in an array, each memory chip being disposed in a corresponding memory region and connected to the corresponding pads through the solder balls.

[0006] In some embodiments, the circuit board includes at least two memory regions; in each of the at least two memory regions, the number of pads is the same.

[0007] In some embodiments, the circuit board includes at least two memory regions; in at least one of the memory regions, the number of pads is different from the number of pads in the other memory regions.

[0008] In some embodiments, the circuit board includes a rectangular region, and at least one memory region is disposed in the rectangular region; the length of the circuit board is greater than or equal to 65 mm, the width of the circuit board is greater than or equal to 14 mm, and the thickness of the circuit board is greater than or equal to 0.8 mm.

[0009] In some embodiments, the circuit board further includes a trapezoidal region, and the rectangular region is connected to the trapezoidal region.

[0010] In some embodiments, peripheral electronic devices are also provided on the circuit board, with a portion of the peripheral electronic devices disposed in the trapezoidal region and another portion of the peripheral electronic devices disposed in the rectangular region and respectively surrounding the memory region.

[0011] In some embodiments, peripheral electronic devices are also provided on the circuit board, and each of the peripheral electronic devices is arranged around the memory area.

[0012] In some embodiments, the peripheral electronic device includes a power supply module connected to at least one of the memory chips to provide at least three different output voltages to each of the memory chips.

[0013] In some embodiments, the power supply module includes a power management integrated circuit (PMIC) chip and a voltage regulator chip, wherein the PMIC chip and the voltage regulator chip are configured to jointly output three or four output voltages.

[0014] In some embodiments, the power supply module includes a power management integrated circuit (PMIC) chip, which is configured to output three or four output voltages.

[0015] In some embodiments, the power supply module includes at least two power conversion chips, which output at least three output voltages.

[0016] In some embodiments, the circuit board includes at least two memory regions, which are sequentially spaced apart along the length of the circuit board.

[0017] In some embodiments, the memory chip is a low-power double data rate fifth-generation chip, including LPDDR5 chips and LPDDR5X chips.

[0018] In some embodiments, the memory chip is a low-power double-speed fifth-generation or higher chip, including LPDDR6 chip, LPDDR6X chip, LPDDR7 chip and LPDDR7X chip.

[0019] In some embodiments, each memory chip includes 200 to 1000 solder balls.

[0020] Secondly, this application provides a motherboard device, including: a motherboard; a connector; and a low-power compressed additional memory module as described in any of the above embodiments, wherein the low-power compressed additional memory module is connected and installed on the motherboard through the connector to constitute the motherboard device.

[0021] The low-power compressed additional memory module provided in this application includes a circuit board and at least one memory chip. The circuit board has at least one memory region, each memory region having pads arranged in an array. Each memory chip includes solder balls arranged in an array, and each memory chip is disposed in a corresponding memory region and connected to the corresponding pads via solder balls. The low-power compressed additional memory module can support various types of memory chips. The circuit board is designed with at least one memory region, allowing for the installation of different numbers of memory chips according to actual needs, thereby realizing diversified designs for the low-power compressed additional memory module. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is an exploded view of the low-power compressed additional memory module provided in an embodiment of this application.

[0024] Figure 2 This is another exploded view of the low-power compressed additional memory module provided in an embodiment of this application.

[0025] Figure 3 This is a top view of a low-power compressed additional memory module with a memory chip, provided as an embodiment of this application.

[0026] Figure 4 A top view of a low-power compressed additional memory module with two memory chips provided in an embodiment of this application.

[0027] Figure 5 A top view of a low-power compressed additional memory module with three memory chips provided in an embodiment of this application.

[0028] Figure 6 A top view of a low-power compressed additional memory module with four memory chips provided in an embodiment of this application.

[0029] Figure 7 Another top view of a low-power compressed additional memory module with a memory chip provided in an embodiment of this application.

[0030] Figure 8 Another top view of a low-power compressed additional memory module with two memory chips provided in an embodiment of this application.

[0031] Figure 9 Another top view of a low-power compressed additional memory module with three memory chips provided in an embodiment of this application.

[0032] Figure 10 Another top view of a low-power compressed additional memory module with four memory chips provided in an embodiment of this application.

[0033] Figure 11 This is a schematic diagram of the structure of the low-power compression additional memory module provided in an embodiment of this application.

[0034] Figure 12 for Figure 11 The diagram shows the structure of the power supply module for the low-power compressed additional memory module.

[0035] Figure 13 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes a PMIC chip and a voltage regulator chip.

[0036] Figure 14 for Figure 12 The power supply module shown is another structural diagram including a PMIC chip and a voltage regulator chip.

[0037] Figure 15 for Figure 12 The diagram shown illustrates the structure of the power supply module, including the PMIC chip.

[0038] Figure 16 for Figure 12 The power supply module shown includes another structural diagram of a PMIC chip.

[0039] Figure 17 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes three power conversion chips.

[0040] Figure 18 for Figure 12 The power supply module shown includes another structural diagram of three power conversion chips.

[0041] Figure 19 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes four power conversion chips.

[0042] Figure 20 for Figure 12 The power supply module shown includes another structural diagram of four power conversion chips.

[0043] Figure 21 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes two power conversion chips.

[0044] Figure 22 for Figure 12 The power supply module shown includes another structural diagram of two power conversion chips.

[0045] Figure 23 This is an exploded view of the motherboard device provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0048] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0051] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0052] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0053] Please refer to the following: Figure 1 and Figure 2 , Figure 1 This is an exploded view of the low-power compression additional memory module provided in an embodiment of this application. Figure 2 This is another exploded view of the low-power compressed additional memory module provided in an embodiment of this application. The low-power compressed additional memory module 10 includes a circuit board 11 and at least one memory chip 12. The circuit board 11 has at least one memory region 110, and each memory region 110 has pads 111 arranged in an array. Each memory chip 12 includes solder balls 121 arranged in an array, and each memory chip 12 is disposed in a corresponding memory region 110 and connected to the corresponding pad 111 through the solder balls 121.

[0054] The low-power compressed additional memory module 10 includes a circuit board 11 and at least one memory chip 12. One side of the circuit board 11 has at least one memory region 110, and each memory chip 12 is disposed in a corresponding memory region 110. The number of memory regions 110 can be the same as the number of memory chips 12, so that each memory chip 12 corresponds one-to-one with each memory region 110. Alternatively, the number of memory regions 110 can be greater than the number of memory chips 12, so that each memory chip 12 can be selectively disposed in a corresponding memory region 110.

[0055] Each memory region 110 has pads 111 arranged in an array, and one side of each memory chip 12 includes solder balls 121 arranged in an array. Each memory chip 12 is connected to the pads 111 in the corresponding memory region 110 through the solder balls 121. The memory chips 12 are soldered to the circuit board 11 using a ball grid array (BGA) package.

[0056] The low-power compressed additional memory module 10 provided in this application embodiment includes a circuit board 11 and at least one memory chip 12. The circuit board 11 has at least one memory region 110, and each memory region 110 has pads 111 arranged in an array. Each memory chip 12 includes solder balls 121 arranged in an array, and each memory chip 12 is disposed in a corresponding memory region 110 and connected to the corresponding pads 111 via the solder balls 121. The memory chip 12 is directly surface-mounted on the circuit board 11 in the form of BGA packaging, which simplifies the packaging process of the memory chip 12, thereby shortening the process cycle and achieving a smaller module size. In the low-power compressed additional memory module 10, the circuit board 11 is designed with at least one memory region 110, and different numbers of memory chips 12 can be installed according to actual needs, thereby realizing the diversified design of the low-power compressed additional memory module 10.

[0057] In some embodiments, the number of pads 111 in memory region 110 may be greater than the number of solder balls 121 of the corresponding memory chip 12, the number of pads 111 in memory region 110 may be equal to the number of solder balls 121 of the corresponding memory chip 12, and the number of pads 111 in memory region 110 may be less than the number of solder balls 121 of the corresponding memory chip 12. No limitation is made here.

[0058] When the number of pads 111 in memory region 110 is greater than the number of solder balls 121 of the corresponding memory chip 12, at least two pads 111 of memory region 110 are connected to at least one solder ball 121 of the corresponding memory chip 12. That is, there may be a situation where multiple pads 111 are connected to one solder ball 121. In some embodiments, there may also be a situation where some pads 111 are not connected to solder balls 121, which is not limited here.

[0059] When the number of pads 111 in memory region 110 is equal to the number of solder balls 121 of the corresponding memory chip 12, the pads 111 in memory region 110 are connected one-to-one with the solder balls 121 of the corresponding memory chip 12.

[0060] When the number of pads 111 in memory region 110 is less than the number of solder balls 121 of the corresponding memory chip 12, at least one pad 111 of memory region 110 is connected to at least two solder balls 121 of the corresponding memory chip 12. That is, there may be a case where one pad 111 is connected to multiple solder balls 121. In some embodiments, there may also be a case where some solder balls 121 are not connected to the pads 111, which is not limited here.

[0061] When the number of pads 111 in the memory region 110 is less than the number of solder balls 121 in the corresponding memory chip 12, the pads 111 in the memory region 110 can be connected to multiple solder balls 121 in the corresponding memory chip 12 in a reused manner, avoiding an excessive number of pads 111 on the circuit board 11, reducing the wiring difficulty of the circuit board 11, and thus reducing the processing cost of the circuit board 11.

[0062] In some embodiments, the circuit board 11 includes at least two memory regions 110; in the at least two memory regions 110, the number of pads 111 in each memory region 110 is the same.

[0063] The number of pads 111 in all memory regions 110 on circuit board 11 is the same. The arrangement of pads 111 in all memory regions 110 can be the same or different, and there is no restriction here.

[0064] In some embodiments, the circuit board 11 includes at least two memory regions 110; in the at least two memory regions 110, the number of pads 111 in at least one memory region 110 is different from the number of pads 111 in the other memory regions 110.

[0065] The number of pads 111 in all memory regions 110 on circuit board 11 is not exactly the same. In all memory regions 110, at least one memory region 110 has a different number of pads 111 than the other memory regions 110. For example, if circuit board 11 has two memory regions 110, the number of pads 111 in the two memory regions 110 is different. Or, if circuit board 11 has three memory regions 110, two of the three memory regions 110 have the same number of pads 111, and one memory region 110 has a different number of pads 111 than the other two memory regions 110; or, all three memory regions 110 have a different number of pads 111.

[0066] In some embodiments, memory chip 12 can be a low-power double data rate fifth-generation chip, including LPDDR5 chip and LPDDR5X chip.

[0067] The memory chip 12 can be a Low Power Double Data Rate (LPDDR) fifth-generation chip, including LPDDR5 and LPDDR5X chips. The low-power compression attached memory module 10 can be an LPDDR5CAMM2 (LPDDR5 Compression Attached Memory Module 2) module, an LPDDR5X CAMM2 module, an LPDDR5SOCAMM2 (LPDDR5 Small Outline Compression Attached Memory Module 2) module, or an LPDDR5XSOCAMM2 module; no specific limitation is made here.

[0068] In some embodiments, the memory chip 12 may also be a low-power double-rate chip of generation 5 or higher, including but not limited to LPDDR6 chips, LPDDR6X chips, LPDDR7 chips, and LPDDR7X chips. Of course, low-power double-rate chips of generation 5 or higher may also include other variations of LPDDR6 chips, LPDDR6X chips, LPDDR7 chips, or LPDDR7X chips, and are not limited here.

[0069] In some embodiments, the number of solder balls 121 in each memory chip 12 can be 200 to 1000.

[0070] The number of solder balls 121 in each memory chip 12 can be any value from 200 to 1000. For example, the number of solder balls 121 in each memory chip 12 can be any of 315, 441, 496, 518, 561, and 563.

[0071] The number of solder balls 121 in each memory chip 12 can be 315, 441, 496, 518, 561, or 563, and is not limited here.

[0072] like Figure 2As shown, each memory chip 12 includes 496 solder balls 121. These 496 solder balls 121 are arranged in an array, comprising a first solder ball array, a second solder ball array, a third solder ball array, and a fourth solder ball array. The first and third solder ball arrays are opposite each other, while the second and fourth solder ball arrays are opposite each other and located between the first and third solder ball arrays. The first and third solder ball arrays each include 28*7 solder balls 121 arranged in an array, and the second and fourth solder ball arrays each include 4*13 solder balls 121 arranged in an array. The first, second, third, and fourth solder ball arrays are arranged end-to-end to form a rectangle.

[0073] The low-power compressed additional memory module 10 can support LPDDR5 chips, LPDDR5X chips, LPDDR6 chips or LPDDR7 chips with various solder ball counts. This not only realizes the diversified design of the low-power compressed additional memory module 10, but also increases the application scenarios of LPDDR5 chips, LPDDR5X chips, LPDDR6 chips and LPDDR7 chips with various solder ball counts.

[0074] Please refer to the following: Figures 3 to 6 , Figure 3 This is a top view of a low-power compressed additional memory module with a memory chip provided in an embodiment of this application. Figure 4 This is a top view of a low-power compressed additional memory module with two memory chips provided in an embodiment of this application. Figure 5 This is a top view of a low-power compressed additional memory module with three memory chips provided in an embodiment of this application. Figure 6 This is a top view of a low-power compressed additional memory module with four memory chips provided in an embodiment of this application. In some embodiments, the circuit board 11 includes a rectangular region 112, and at least one memory region 110 is disposed in the rectangular region 112; the length of the circuit board 11 is greater than or equal to 65 mm, the width of the circuit board 11 is greater than or equal to 14 mm, and the thickness of the circuit board 11 is greater than or equal to 0.8 mm.

[0075] The circuit board 11 includes a rectangular area 112. The length of the circuit board 11 is greater than or equal to 65 mm, the width of the circuit board 11 is greater than or equal to 14 mm, and the thickness of the circuit board 11 is greater than or equal to 0.8 mm. Correspondingly, the long side of the rectangular area 112 is greater than or equal to 65 mm, and the short side of the rectangular area 112 is greater than or equal to 14 mm. For example, the length of the circuit board 11 can be 65 mm, 70 mm, 75 mm, 80 mm, 85 mm, 90 mm, 95 mm, or 100 mm, etc.; the width of the circuit board 11 can be 14 mm, 18 mm, 22 mm, 26 mm, 30 mm, 34 mm, 38 mm, or 42 mm, etc.; and the thickness of the circuit board 11 can be 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, or 2.0 mm, etc.

[0076] In some embodiments, the circuit board 11 has a length of 78mm, a width of 23mm, and a thickness of 1.2mm. That is, the dimensions of the circuit board 11 are 78mm * 23mm * 1.2mm, and the dimensions of the rectangular area 112 are 78mm * 23mm.

[0077] like Figure 3 As shown, the circuit board 11 may include a memory region 110, which may be located at the center of a rectangular region 112 and symmetrically arranged along the axis of symmetry of the circuit board 11. Accordingly, the low-power compressed additional memory module 10 includes a memory chip 12, which is correspondingly located in one memory region 110.

[0078] In some embodiments, a memory region 110 may also be set at any position in the rectangular region 112, without limitation.

[0079] In some embodiments, the circuit board 11 includes at least two memory regions 110, which are arranged at intervals along the length of the circuit board 11. The length of the circuit board 11 is the direction of the long side of the rectangular region 112.

[0080] like Figure 4 As shown, the circuit board 11 may include two memory regions 110, which are arranged alternately along the length of the circuit board 11 and symmetrically arranged on both sides of the long side axis of the rectangular region 112. Correspondingly, the low-power compression additional memory module 10 includes two memory chips 12, which are arranged one-to-one in the two memory regions 110.

[0081] In some embodiments, the two memory regions 110 can also be set at any position in the rectangular region 112, without limitation.

[0082] In some embodiments, the low-power compression additional memory module 10 may include a memory chip 12, which may be selectively disposed in either of two memory regions 110.

[0083] like Figure 5 As shown, the circuit board 11 may include three memory regions 110, which are arranged sequentially and at intervals along the length of the circuit board 11. The three memory regions 110 can be located at any position in the rectangular region 112, and there is no limitation on this. Correspondingly, the low-power compression additional memory module 10 includes three memory chips 12, which are arranged one-to-one in the three memory regions 110.

[0084] In some embodiments, the low-power compression additional memory module 10 may include a memory chip 12, which may be selectively disposed in any one of the three memory regions 110. The low-power compression additional memory module 10 may also include two memory chips 12, which may be selectively disposed in any two of the three memory regions 110.

[0085] like Figure 6 As shown, the circuit board 11 may also include four memory regions 110, which are arranged sequentially and at intervals along the length of the circuit board 11, with each of the four memory regions 110 positioned in pairs on either side of the long side axis of symmetry of the rectangular region 112. Correspondingly, the low-power compressed additional memory module 10 may include four memory chips 12, which are arranged one-to-one in the four memory regions 110.

[0086] In some embodiments, the four memory regions 110 can also be set at any position in the rectangular region 112, without limitation.

[0087] In some embodiments, the low-power compression additional memory module 10 may include one memory chip 12, which may be selectively disposed in any one of the four memory regions 110. The low-power compression additional memory module 10 may also include two memory chips 12, which may be selectively disposed in any two of the four memory regions 110. The low-power compression additional memory module 10 may also include three memory chips 12, which may be selectively disposed in any three of the four memory regions 110.

[0088] The circuit board 11 can be optionally configured with one memory region 110, two memory regions 110, three memory regions 110, or four memory regions 110. Correspondingly, the low-power compression additional memory module 10 can optionally be equipped with one memory chip 12, two memory chips 12, three memory chips 12, or four memory chips 12, thereby realizing the diversified design of the low-power compression additional memory module 10.

[0089] Please refer to the following: Figures 3 to 6 In some embodiments, peripheral electronic devices 114 are also provided on the circuit board 11, and the peripheral electronic devices 114 are respectively arranged around the memory area 110.

[0090] The circuit board 11 is also equipped with peripheral electronic devices 114, which may include power supply modules, serial presence detection EEPROM with hub (SPD HUB), and other devices. The peripheral electronic devices 114 are all arranged around the memory area 110.

[0091] When the circuit board 11 is provided with one memory area 110, two memory areas 110, or three memory areas 110, or when the circuit board 11 is provided with a small memory chip 12, the rectangular area 112 of the circuit board 11 has more installation space. Therefore, all peripheral electronic devices 114 can be placed in the extra installation space of the rectangular area 112, so that the width of the circuit board 11 can be greater than or equal to 14mm, thereby reducing the width of the circuit board 11.

[0092] Please refer to the following: Figures 7 to 10 , Figure 7 Another top view of a low-power compressed additional memory module with a memory chip provided in an embodiment of this application. Figure 8 This is another top view of a low-power compressed additional memory module with two memory chips provided in an embodiment of this application. Figure 9 This is another top view of a low-power compressed additional memory module with three memory chips provided in an embodiment of this application. Figure 10 Another top view of a low-power compressed additional memory module with four memory chips provided in an embodiment of this application. In some embodiments, the circuit board 11 further includes a trapezoidal region 113, and the rectangular region 112 is connected to the trapezoidal region 113.

[0093] The circuit board 11 includes a rectangular region 112 and a trapezoidal region 113, with the longer base of the trapezoidal region 113 connected to one of the longer sides of the rectangular region 112. The trapezoidal region 113 is an isosceles trapezoid, and the circuit board 11 has a symmetrical structure with an axis of symmetry. The axis of symmetry of the circuit board 11 coincides with the axis of symmetry of the trapezoidal region 113.

[0094] In some embodiments, the circuit board 11 has a length of 78mm, a width of 34mm, and a thickness of 1.2mm. The long side of the rectangular region 112 is 78mm, the short side is 23mm, and the height of the trapezoidal region 113 is 11mm. That is, the dimensions of the circuit board 11 are 78mm * 34mm * 1.2mm, and the dimensions of the rectangular region 112 are 78mm * 23mm.

[0095] like Figure 7 As shown, the circuit board 11 may include a memory region 110, which may be located at the center of a rectangular region 112 and symmetrically arranged along the axis of symmetry of the circuit board 11. Accordingly, the low-power compressed additional memory module 10 includes a memory chip 12, which is correspondingly located in one memory region 110.

[0096] In some embodiments, a memory region 110 may also be set at any position in the rectangular region 112, without limitation.

[0097] In some embodiments, the circuit board 11 includes at least two memory regions 110, which are arranged at intervals along the length of the circuit board 11. The length of the circuit board 11 is the direction of the long side of the rectangular region 112.

[0098] like Figure 8 As shown, the circuit board 11 may include two memory regions 110, which are arranged sequentially at intervals along the length of the circuit board 11 and symmetrically arranged on both sides of the axis of symmetry of the circuit board 11. Correspondingly, the low-power compression additional memory module 10 includes two memory chips 12, which are arranged one-to-one in the two memory regions 110.

[0099] In some embodiments, the two memory regions 110 can also be set at any position in the rectangular region 112, without limitation.

[0100] In some embodiments, the low-power compression additional memory module 10 may include a memory chip 12, which may be selectively disposed in either of two memory regions 110.

[0101] like Figure 9As shown, the circuit board 11 may include three memory regions 110, which are arranged sequentially at intervals along the length of the circuit board 11. One of the three memory regions 110 is located at the center of the rectangular region 112 and is symmetrically arranged along the axis of symmetry of the circuit board 11. The other two memory regions 110 are symmetrically arranged on both sides of the axis of symmetry of the circuit board 11. Correspondingly, the low-power compressed additional memory module 10 includes three memory chips 12, which are arranged one-to-one in the three memory regions 110.

[0102] In some embodiments, the three memory regions 110 can also be set at any position in the rectangular region 112, without limitation.

[0103] In some embodiments, the low-power compression additional memory module 10 may include a memory chip 12, which may be selectively disposed in any one of the three memory regions 110. The low-power compression additional memory module 10 may also include two memory chips 12, which may be selectively disposed in any two of the three memory regions 110.

[0104] like Figure 10 As shown, the circuit board 11 may also include four memory regions 110, which are arranged sequentially and spaced apart along the length of the circuit board 11, with each pair of memory regions 110 positioned on either side of the axis of symmetry of the circuit board 11. Correspondingly, the low-power compression additional memory module 10 may include four memory chips 12, which are arranged one-to-one in the four memory regions 110.

[0105] In some embodiments, the four memory regions 110 can also be set at any position in the rectangular region 112, without limitation.

[0106] In some embodiments, the low-power compression additional memory module 10 may include one memory chip 12, which may be selectively disposed in any one of the four memory regions 110. The low-power compression additional memory module 10 may also include two memory chips 12, which may be selectively disposed in any two of the four memory regions 110. The low-power compression additional memory module 10 may also include three memory chips 12, which may be selectively disposed in any three of the four memory regions 110.

[0107] When the low-power compressed additional memory module 10 includes four memory chips 12, the low-power compressed additional memory module 10 including four memory chips 12 can increase the memory capacity, thus doubling the memory capacity, compared to the low-power compressed additional memory module 10 including only two memory chips 12.

[0108] The circuit board 11 can be optionally configured with one, two, three, or four memory regions 110. Correspondingly, the low-power compressed additional memory module 10 can optionally install one, two, three, or four memory chips 12, thereby achieving diversified designs for the low-power compressed additional memory module 10. Furthermore, the memory capacity of the low-power compressed additional memory module 10 can be varied from 16GB to 128GB by changing the number of memory chips 12, thus meeting different user needs.

[0109] Please refer to the following: Figures 7 to 10 In some embodiments, peripheral electronic devices 114 are also provided on the circuit board 11. A portion of the peripheral electronic devices 114 is provided in the trapezoidal region 113, and another portion of the peripheral electronic devices 114 is provided in the rectangular region 112 and is respectively provided around the memory region 110.

[0110] The circuit board 11 is also provided with peripheral electronic devices 114, which may include power supply modules, serial presence detection hubs, and other devices. Among them, a part of the peripheral electronic devices 114 is located in the trapezoidal area 113, and another part of the peripheral electronic devices 114 is located in the rectangular area 112 and is respectively arranged around the memory area 110.

[0111] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a low-power compressed additional memory module provided in an embodiment of this application. In some embodiments, the peripheral electronic device 114 includes a power supply module 115, which is connected to at least one memory chip 12 to provide at least three different output voltages to each memory chip 12.

[0112] The peripheral electronic device 114 includes a power supply module 115, which is connected to at least one memory chip 12. That is, the power supply module 115 is connected to each memory chip 12. The power supply module 115 provides at least three different output voltages to each memory chip 12. When the power supply module 115 provides three output voltages to each memory chip 12, the magnitudes of the three output voltages are all different. When the power supply module 115 provides four output voltages to each memory chip 12, the magnitudes of the four output voltages are all different; or, of the four output voltages, three are different, and the magnitude of the remaining output voltage is the same as the magnitude of one of the three output voltages, i.e., the power supply module 115 provides three different output voltages to each memory chip 12.

[0113] Power supply module 115 can be applied to, for example Figures 3 to 10 The low-power compressed additional memory module 10 shown is not limited here.

[0114] Please refer to Figure 12 , Figure 12 for Figure 11 The diagram shows the structure of the power supply module for the low-power compressed additional memory module. The power supply module 115 includes one input terminal 1154 and at least three output terminals 1155. The input terminal 1154 is configured to receive an input voltage, and the at least three output terminals 1155 are configured to output at least three different output voltages. Each output terminal 1155 outputs one output voltage and is connected to each memory chip 12.

[0115] Please refer to the following: Figure 13 and Figure 14 , Figure 13 for Figure 12 The diagram shown illustrates the structure of the power supply module, including the PMIC chip and the voltage regulator chip. Figure 14 for Figure 12 The diagram shows another structural schematic of the power supply module, including a PMIC chip and a voltage regulator chip. In some embodiments, the power supply module 115 includes a power management integrated circuit (PMIC) chip 1151 and a voltage regulator chip 1152, which are configured to jointly output three or four output voltages.

[0116] The power supply module 115 includes a PMIC (Power Management IC) chip 1151 and a voltage regulator (VR) chip 1152 (i.e., VR chip 1152). The PMIC chip 1151 is connected to input terminal 1154 and is configured to generate two or three output voltages based on the input voltage. The voltage regulator chip 1152 is connected to input terminal 1154 and is configured to generate one output voltage based on the input voltage. In some embodiments, the VR chip 1152 may also be referred to as a voltage regulator chip.

[0117] like Figure 13 As shown, the PMIC chip 1151 includes two voltage output terminals 11510, and correspondingly, the power supply module 115 includes three output terminals 1155, with each voltage output terminal 11510 connected to one output terminal 1155. The two voltage output terminals 11510 are configured to output two different output voltages. The voltage regulator chip 1152 includes a chip output terminal 11520, which is connected to one output terminal 1155 and configured to output a single output voltage.

[0118] In some embodiments, the output voltages output from the two voltage output terminals 11510 of the PMIC chip 1151 are a first voltage and a third voltage, respectively, and the output voltage output from the chip output terminal 11520 of the voltage regulator chip 1152 is a second voltage. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0119] like Figure 14 As shown, the PMIC chip 1151 includes three voltage output terminals 11510, and correspondingly, the power supply module 115 includes four output terminals 1155, with each voltage output terminal 11510 connected to one output terminal 1155. The three voltage output terminals 11510 are configured to output two identical output voltages and one output voltage different from the two identical output voltages, i.e., two different output voltages. The voltage regulator chip 1152 includes one chip output terminal 11520, which is connected to one output terminal 1155 and configured to output a single output voltage.

[0120] In some embodiments, the three voltage output terminals 11510 of the PMIC chip 1151 output voltages respectively as a first voltage, a second voltage, and a third voltage, and the chip output terminal 11520 of the voltage regulator chip 1152 outputs a second voltage. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0121] In some embodiments, the first voltage can be any value from 0.80V to 1.15V, such as 0.80V, 0.85V, 0.90V, 0.95V, 1.0V, 1.05V, 1.10V, or 1.15V; the second voltage can be any value from 0.25V to 0.60V, such as 0.25V, 0.30V, 0.35V, 0.40V, 0.45V, 0.50V, 0.55V, or 0.60V; and the third voltage can be any value from 1.50V to 2.0V, such as 1.50V, 1.55V, 1.60V, 1.65V, 1.70V, 1.75V, 1.80V, 1.85V, 1.90V, 1.95V, or 2.0V.

[0122] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V.

[0123] Please refer to the following: Figure 15 and Figure 16 , Figure 15 for Figure 12 The diagram shown illustrates the structure of the power supply module, including the PMIC chip. Figure 16 for Figure 12 The power supply module shown includes another structural schematic diagram of a PMIC chip. In some embodiments, the power supply module 115 includes a power management integrated circuit PMIC chip 1151, which is configured to output three or four output voltages.

[0124] like Figure 15 As shown, the power supply module 115 includes a PMIC chip 1151, which has three voltage output terminals 11510 configured to output three different output voltages, each configured to output one output voltage. Correspondingly, the power supply module 115 includes three output terminals 1155. Each voltage output terminal 11510 is connected to one output terminal 1155, so that the three output terminals 1155 output three different output voltages.

[0125] In some embodiments, the three voltage output terminals 11510 of the PMIC chip 1151 output a first voltage, a second voltage, and a third voltage through three output terminals 1155, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0126] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V. That is, the three voltage output terminals 11510 of the PMIC chip 1151 output 1.05V, 0.50V, and 1.80V respectively through three output terminals 1155. The PMIC chip 1151 can be a PMIC 5100 chip.

[0127] The power supply module 115 can be powered by a single PMIC chip 1151, namely the PMIC 5100 chip, which simplifies the layout design of the power supply module 115, reduces the space occupied by the power supply module 115, and thus reduces the cost of the power supply module 115.

[0128] like Figure 16 As shown, the power supply module 115 includes a PMIC chip 1151, which has four voltage output terminals 11510 configured to output four different output voltages, with each voltage output terminal 11510 configured to output one output voltage. Correspondingly, the power supply module 115 includes four output terminals 1155. Each voltage output terminal 11510 is connected to one output terminal 1155, so that the four output terminals 1155 output four different output voltages.

[0129] In some embodiments, the four voltage output terminals 11510 of the PMIC chip 1151 output a first voltage, a second voltage, a third voltage, and a fourth voltage through four output terminals 1155, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0130] In some embodiments, the fourth voltage is any value from 0.70V to 1.0V, such as 0.70V, 0.75V, 0.80V, 0.85V, 0.90V, 0.95V, or 1.0V.

[0131] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, the third voltage is 1.80V, and the fourth voltage is 0.90V. That is, the four voltage output terminals 11510 of the PMIC chip 1151 output 1.05V, 0.50V, 1.80V, and 0.90V respectively through four output terminals 1155. The PMIC chip 1151 can be a PMIC 5200 chip.

[0132] The power supply module 115 can be powered by a single PMIC chip 1151, namely the PMIC 5200 chip, which simplifies the layout design of the power supply module 115, reduces the space occupied by the power supply module 115, and thus reduces the cost of the power supply module 115.

[0133] Please refer to the following: Figures 17 to 22 , Figure 17 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes three power conversion chips. Figure 18 for Figure 12 The power supply module shown here includes another structural diagram of three power conversion chips. Figure 19 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes four power conversion chips. Figure 20 for Figure 12 The power supply module shown is another structural diagram including four power conversion chips. Figure 21 for Figure 12 The diagram shown illustrates the structure of the power supply module, which includes two power conversion chips. Figure 22 for Figure 12 The power supply module shown includes another structural schematic diagram of two power conversion chips. In some embodiments, the power supply module 115 includes at least two power conversion chips 1153, which output at least three output voltages.

[0134] The power supply module 115 includes at least two power conversion chips 1153. One end of each power conversion chip 1153 is connected to an input terminal 1154, and the other end of each power conversion chip 1153 is connected to an output terminal 1155. Based on the input voltage input from the input terminal 1154, the power conversion chip 1153 converts the input voltage to generate a corresponding output voltage, and outputs the output voltage through the corresponding output terminal 1155.

[0135] like Figure 17 As shown, in some embodiments, the power supply module 115 includes three power conversion chips 1153, each power conversion chip 1153 generating a corresponding output voltage. The output voltages of the three power conversion chips 1153 are a first voltage, a second voltage, and a third voltage, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0136] The power supply module 115 includes three power conversion chips 1153 and three output terminals 1155. Each power conversion chip 1153 is connected to a corresponding output terminal 1155. The three power conversion chips 1153 generate three different output voltages based on the input voltage, so that the three output terminals 1155 output three different output voltages.

[0137] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V. The output voltages generated by the three power conversion chips 1153 are 1.05V, 0.50V, and 1.80V, respectively.

[0138] like Figure 18 As shown, in some embodiments, the power supply module 115 includes three power conversion chips 1153. One of the three power conversion chips 1153 outputs two different output voltages, while the other two power conversion chips 1153 each generate a corresponding output voltage. That is, the three power conversion chips 1153 collectively generate four different output voltages. The output voltages of the three power conversion chips 1153 are a first voltage, a second voltage, a third voltage, and a fourth voltage. Specifically, the first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0139] The power supply module 115 includes three power conversion chips 1153 and four output terminals 1155. Two power conversion chips 1153, each outputting a different output voltage, are connected to two output terminals 1155, each generating a corresponding output voltage. The three power conversion chips 1153 generate four different output voltages based on the input voltage, allowing the four output terminals 1155 to output four different voltages.

[0140] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, the third voltage is 1.80V, and the fourth voltage is 0.90V. The output voltages generated by the three power conversion chips 1153 are 1.05V, 0.50V, 1.80V, and 0.90V, respectively.

[0141] like Figure 19As shown, in some embodiments, the power supply module 115 includes four power conversion chips 1153, each power conversion chip 1153 generating a corresponding output voltage. The output voltages of the four power conversion chips 1153 are a first voltage, a second voltage, a third voltage, and a fourth voltage, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0142] The power supply module 115 includes four power conversion chips 1153 and four output terminals 1155. Each power conversion chip 1153 is connected to a corresponding output terminal 1155. The four power conversion chips 1153 generate four different output voltages based on the input voltage, so that the four output terminals 1155 output four different output voltages.

[0143] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, the third voltage is 1.80V, and the fourth voltage is 0.90V. The output voltages generated by the four power conversion chips 1153 are 1.05V, 0.50V, 1.80V, and 0.90V, respectively.

[0144] In some embodiments, the four power conversion chips 1153 can generate two different output voltages and two identical output voltages based on the input voltage. The two identical output voltages and the two different output voltages are all different; that is, the four power conversion chips 1153 collectively generate three different output voltages. The output voltages generated by the four power conversion chips 1153 can be a first voltage, a second voltage, a third voltage, or any one of the first voltage, second voltage, and third voltage. For example, the four power conversion chips 1153 can generate the first voltage, the first voltage, the second voltage, and the third voltage, or the first voltage, the second voltage, the second voltage, and the third voltage, or the first voltage, the second voltage, the third voltage, and the third voltage; no limitation is made here.

[0145] like Figure 20 As shown, in some embodiments, the power supply module 115 includes four power conversion chips 1153. Two of the four power conversion chips 1153 jointly generate one output voltage, while the other two power conversion chips 1153 each generate a corresponding output voltage. That is, the four power conversion chips 1153 jointly generate three different output voltages. The output voltages of the four power conversion chips 1153 are a first voltage, a second voltage, and a third voltage, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0146] The power supply module 115 includes four power conversion chips 1153 and three output terminals 1155. Two power conversion chips 1153 that generate a common output voltage are connected to the same output terminal 1155, and two power conversion chips 1153 that generate a corresponding output voltage are each connected to a separate output terminal 1155. The four power conversion chips 1153 generate three different output voltages based on the input voltage, so that the three output terminals 1155 output three different output voltages.

[0147] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V. The output voltages generated by the four power conversion chips 1153 are 1.05V, 0.50V, and 1.80V, respectively.

[0148] like Figure 21 and Figure 22 As shown, in some embodiments, the power supply module 115 includes two power conversion chips 1153, at least one of which generates two output voltages.

[0149] like Figure 21 As shown, in some embodiments, one of the two power conversion chips 1153 generates two different output voltages, while the other power conversion chip 1153 generates one output voltage; that is, the two power conversion chips 1153 together generate three different output voltages. The output voltages of the two power conversion chips 1153 are a first voltage, a second voltage, and a third voltage, respectively. The first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0150] The power supply module 115 includes two power conversion chips 1153 and three output terminals 1155. A power conversion chip 1153 generating two different output voltages is connected to the two output terminals 1155, and a power conversion chip 1153 generating one output voltage is connected to the one output terminal 1155. The two power conversion chips 1153 generate three different output voltages based on the output voltage conversion, so that the three output terminals 1155 output three different output voltages.

[0151] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V. The output voltages generated by the two power conversion chips 1153 are 1.05V, 0.50V, and 1.80V, respectively.

[0152] like Figure 22As shown, in some embodiments, both power conversion chips 1153 generate two output voltages. One power conversion chip 1153 generates two different output voltages, while the other generates two identical output voltages. In other words, the two power conversion chips 1153 jointly generate three different output voltages. The output voltages of the two power conversion chips 1153 are a first voltage, a second voltage, a third voltage, or any one of the first, second, and third voltages. Specifically, the first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, and the third voltage is greater than or equal to 1.50V.

[0153] The power supply module 115 includes two power conversion chips 1153 and four output terminals 1155, with each power conversion chip 1153 connected to two output terminals 1155 respectively. The two power conversion chips 1153 can generate output voltages of a first voltage, a first voltage, a second voltage, and a third voltage, or a first voltage, a second voltage, a second voltage, and a third voltage, or a first voltage, a second voltage, and a third voltage, etc., which are not limited here.

[0154] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, and the third voltage is 1.80V.

[0155] In some embodiments, both power conversion chips 1153 generate two output voltages, with each power conversion chip 1153 generating two different output voltages, meaning the two power conversion chips 1153 together generate four different output voltages. The output voltages of the two power conversion chips 1153 are a first voltage, a second voltage, a third voltage, and a fourth voltage. Specifically, the first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0156] The power supply module 115 includes two power conversion chips 1153 and four output terminals 1155, with each power conversion chip 1153 connected to two output terminals 1155 respectively. The two power conversion chips 1153 generate four different output voltages based on the output voltage conversion, so that the four output terminals 1155 output four different output voltages.

[0157] In some embodiments, the first voltage is 1.05V, the second voltage is 0.50V, the third voltage is 1.80V, and the fourth voltage is 0.90V. The output voltages generated by the two power conversion chips 1153 are 1.05V, 0.50V, 1.80V, and 0.90V, respectively.

[0158] In some embodiments, the power supply module 115 may include five power conversion chips 1153 and five output terminals 1155. Each power conversion chip 1153 generates a corresponding output voltage based on the input voltage, and each power conversion chip 1153 is connected to a corresponding output terminal 1155. Two of the five power conversion chips 1153 generate two identical output voltages, while the remaining three power conversion chips 1153 generate three different output voltages. The two identical output voltages and any one of the three different output voltages are different; that is, the five power conversion chips 1153 collectively generate four different output voltages. The output voltages generated by the five power conversion chips 1153 based on the input voltage are, respectively, a first voltage, a second voltage, a third voltage, a fourth voltage, and any one of the first voltage, second voltage, third voltage, and fourth voltage. For example, the output voltages generated by the five power conversion chips 1153 can be a first voltage, a second voltage, a third voltage, and a fourth voltage; or they can be the same voltage as above, without limitation. Specifically, the first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0159] In some embodiments, the power supply module 115 may include five power conversion chips 1153, with at least two of the five power conversion chips 1153 jointly generating an output voltage. For example, two of the five power conversion chips 1153 jointly generate an output voltage, while the remaining three power conversion chips 1153 each generate a corresponding output voltage, meaning the five power conversion chips 1153 jointly generate four different output voltages; the output voltages of the five power conversion chips 1153 are a first voltage, a second voltage, a third voltage, and a fourth voltage. As another example, four of the five power conversion chips 1153 jointly generate an output voltage in pairs, while the remaining power conversion chip 1153 generates a corresponding output voltage, meaning the five power conversion chips 1153 jointly generate three different output voltages; the output voltages of the five power conversion chips 1153 are a first voltage, a second voltage, and a third voltage. For example, three of the five power conversion chips 1153 generate a single output voltage, while the remaining two generate their own corresponding output voltages. In other words, the five power conversion chips 1153 collectively generate three different output voltages: a first voltage, a second voltage, and a third voltage. Specifically, the first voltage is greater than or equal to 0.80V, the second voltage is greater than or equal to 0.25V, the third voltage is greater than or equal to 1.50V, and the fourth voltage is greater than or equal to 0.70V.

[0160] In some embodiments, the power conversion chip 1153 includes a DC-DC conversion chip.

[0161] Each power conversion chip 1153 includes a DC-DC converter chip.

[0162] The power supply module 115 is powered by at least two power conversion chips 1153. It can adapt the output capability of the power conversion chips 1153 according to the actual situation, so as to adjust the number of power conversion chips 1153, flexibly meet diverse power supply needs, improve the scenario adaptability of the power supply module 115, and make the power supply module 115 have high compatibility, thereby realizing the diversified design of the low power compression additional memory module 10.

[0163] Please refer to the following: Figures 17 to 22 In some embodiments, the power supply module 115 further includes a logic control unit 1156, and each power conversion chip 1153 is connected to the logic control unit 1156 to determine the power-on and power-off sequence of the corresponding output voltage based on the logic control signal output by the logic control unit 1156.

[0164] The power supply module 115 also includes a logic control unit 1156. One end of the input terminal 1154 of each power conversion chip 1153 is also used to connect to the logic control unit 1156. The logic control unit 1156 outputs logic control signals to each power conversion chip 1153, and each power conversion chip 1153 determines the power-on and power-off sequence of the corresponding output voltage based on the logic control signals.

[0165] The power supply module 115 also includes a control logic control unit 1156 for power-on and power-off timing. It provides power through discrete power supply and logic control, and can precisely control the power-on and power-off timing of multiple power conversion chips 1153 to ensure the normal operation of each power conversion chip 1153 and the stability of the power supply module 115.

[0166] The power supply module 115 can provide output voltage through the PMIC chip 1151 and VR chip 1152, or through the PMIC chip 1151 alone, or through multiple power conversion chips 1153. These multiple power supply methods provide output voltage to the memory chip 12, allowing for fine-tuning according to actual needs and scenarios, thus achieving a diversified design for the low-power compressed additional memory module 10.

[0167] Please refer to Figure 23 , Figure 23 This is an exploded view of the motherboard device provided in an embodiment of this application. The motherboard device 1 includes a motherboard 20, a connector 30, and a low-power compressed additional memory module 10 as described in any of the above embodiments. The low-power compressed additional memory module 10 is connected and installed on the motherboard 20 via the connector 30 to constitute the motherboard device 1.

[0168] One side of connector 30 is connected to the side of circuit board 11 away from memory chip 12, and the other side of connector 30 is connected to motherboard 20.

[0169] The low-power compressed additional memory module 10 features a versatile design, allowing for customization to meet specific needs and scenarios, thus enabling the motherboard device 1 to satisfy the diverse requirements of mobile devices. Furthermore, when the motherboard device 1 is used in portable electronic devices such as laptops, users can easily expand memory capacity by simply replacing the low-power compressed additional memory module 10, without needing to replace the entire motherboard device 1, significantly improving the maintainability and flexibility of portable electronic devices.

[0170] In some embodiments, the functions or modules of the apparatus provided in this application can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0171] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0172] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0173] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0174] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A low power consumption compressed additional memory module, characterized by, include: The circuit board has at least one memory region, and each memory region has pads arranged in an array. At least one memory chip, each memory chip including solder balls arranged in an array, each memory chip being disposed in a corresponding memory region and connected to a corresponding pad via the solder balls.

2. The low power compressed additional memory module of claim 1, wherein, The circuit board includes at least two memory regions; In the at least two memory regions, the number of pads in each memory region is the same; or in the at least two memory regions, the number of pads in at least one memory region is different from the number of pads in the other memory regions.

3. The low-power compressed additional memory module according to claim 1, characterized in that, The circuit board includes a rectangular region, and at least one of the memory regions is disposed in the rectangular region; The circuit board has a length greater than or equal to 65mm, a width greater than or equal to 14mm, and a thickness greater than or equal to 0.8mm.

4. The low-power compressed additional memory module according to claim 3, characterized in that, The circuit board also includes a trapezoidal region, and the rectangular region is connected to the trapezoidal region.

5. The low-power compressed additional memory module according to claim 4, characterized in that, The circuit board is also provided with peripheral electronic devices. A portion of the peripheral electronic devices is located in the trapezoidal area, and another portion of the peripheral electronic devices is located in the rectangular area and respectively surrounds the memory area.

6. The low-power compressed additional memory module according to claim 3, characterized in that, The circuit board is also equipped with peripheral electronic components, which are arranged around the memory area.

7. The low-power compressed additional memory module according to claim 5 or 6, characterized in that, The peripheral electronic device includes a power supply module, which is connected to at least one of the memory chips to provide at least three different output voltages to each of the memory chips.

8. The low-power compressed additional memory module according to claim 7, characterized in that, The power supply module includes a power management integrated circuit (PMIC) chip and a voltage regulator chip, wherein the PMIC chip and the voltage regulator chip are configured to jointly output three or four output voltages; or The power supply module includes a power management integrated circuit (PMIC) chip, which is configured to output three or four output voltages.

9. The low-power compressed additional memory module according to claim 7, characterized in that, The power supply module includes at least two power conversion chips, and the at least two power conversion chips output at least three output voltages.

10. The low-power compressed additional memory module according to claim 3 or 5, characterized in that, The circuit board includes at least two memory regions, which are arranged at intervals along the length of the circuit board.

11. The low-power compressed additional memory module according to claim 1, characterized in that, The memory chip is a low-power, double-data-rate fifth-generation chip, including LPDDR5 and LPDDR5X chips, or... The memory chips are low-power, double-speed, fifth-generation or higher chips, including LPDDR6 chips, LPDDR6X chips, LPDDR7 chips, and LPDDR7X chips.

12. The low power compressed additional memory module of claim 1, wherein, The number of solder balls for each memory chip is 200 to 1000.

13. A motherboard device, characterized by include: Motherboard; Connector; The low-power compressed additional memory module as described in any one of claims 1 to 12, wherein the low-power compressed additional memory module is connected and installed on the motherboard via the connector to form the motherboard device.

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