A novel external power supply reset circuit for preventing system crashes

Abstract

This utility model discloses a novel external power supply reset circuit for preventing system crashes, comprising an external watchdog circuit and a main control LDO power supply circuit. Through the external watchdog, a novel combined circuit is implemented that enables automatic power-off restart of the device when the device firmware and internal watchdog fail and cannot recover normally. This is achieved through the enable control terminals of the external watchdog and the main control MCU / main control module's power supply LDO / DC-DC power conversion module. By using a low-cost external watchdog and existing power conversion modules, mobile IoT terminal nodes can quickly recover from power failures in firmware anomalies. In most unattended application scenarios, this ensures long-term stable and reliable operation of the terminal nodes, greatly reducing the manpower required for equipment maintenance and improving the intelligence level of terminal devices.

Description

Technical Field

[0001] This utility model relates to the field of power supply circuit technology, and in particular to a novel external power supply reset circuit for preventing system crashes. Background Technology

[0002] With the rapid development of mobile IoT, smart homes, and sensor technology, smart sensors have become widely used in people's daily lives. However, how to ensure that mobile IoT node devices can operate stably for a long time while maintaining low power consumption, especially when the nodes are deployed in unattended environments, and can automatically recover when the internal firmware of the device malfunctions, has become an urgent problem to be solved.

[0003] Many mobile IoT device nodes are deployed in unattended scenarios. The main control MCU and modules of the node itself usually have internal watchdogs to ensure stable firmware operation. However, if the firmware itself malfunctions, it cannot be guaranteed that the device will automatically resume normal operation. Utility Model Content

[0004] The purpose of this utility model is to provide a new type of anti-crash external power reset circuit to address the defects and deficiencies of the existing technology. By using an external watchdog timer, a new combination circuit can be implemented to enable the device to automatically power off and restart when the device firmware and internal watchdog timer fail and cannot be restored normally. This is achieved through the enable control terminal of the external watchdog timer and the power supply LDO / DC-DC power conversion module of the main control MCU / main control module.

[0005] To achieve the above objectives, this utility model provides the following technical solution: A novel external power supply reset circuit for preventing system crashes includes an external watchdog circuit and a main control LDO power supply circuit. The external watchdog circuit and the main control LDO power supply circuit are connected. The external watchdog circuit includes a VIN terminal, an LDO_EN terminal, a WDI terminal, resistors R411, R413, R414, and R416, a capacitor C413, and a chip U401. The VIN terminal is connected to one end of resistor R414, and the other end of resistor R414 is connected to resistors R41 and R416 respectively. One end of pin 3 is connected to pin 1 of chip U401, the other end of resistor R413 is connected to the LDO_EN terminal, pin 2 of chip U401 is grounded, pin 3 of chip U401 is connected to one end of resistor R416, the other end of resistor R416 is grounded, pin 4 of chip U401 is connected to one end of resistor R411 and the WDI terminal respectively, the other end of resistor R411 is grounded, and pin 5 of chip U401 is connected to one end of capacitor C413 and the VIN terminal respectively, the other end of capacitor C413 is grounded.

[0006] As a further preferred embodiment of the novel anti-crash external power supply reset circuit of this utility model, the main control LDO power supply circuit includes a chip U402, a VIN terminal, an LDO_EN terminal, capacitors C407, C408, C409, and C410, a resistor R415, a diode D401, and a 3.0V voltage output terminal. The VIN terminal is connected to one end of capacitor C407, one end of capacitor C410, one end of resistor R415, and pin 1 of chip U402. The other ends of capacitors C407 and C410 are connected to and grounded. The other end of resistor R415 is connected to pin 3 of chip U402 and the LDO_EN terminal. Pin 2 of chip U402 is grounded. Pin 5 of chip U402 is connected to one end of diode D401, the 3.0V voltage output terminal, one end of capacitor C408, and one end of capacitor C409. The other end of diode D401 is grounded. The other ends of capacitors C408 and C409 are connected to and grounded.

[0007] As a further preferred embodiment of the novel anti-crash external power supply reset circuit of this utility model, the chip model of the chip U401 is STWD100NYWY.

[0008] As a further preferred embodiment of the novel anti-crash external power supply reset circuit of this utility model, the VIN terminal is the battery input voltage, which is usually 3.7~4.2V.

[0009] As a further preferred embodiment of the novel anti-crash external power supply reset circuit of this utility model, the chip model of the chip U402 is R6232B33M.

[0010] Compared with the prior art, the present invention, by adopting the above technical solution, has the following technical effects: 1. This utility model discloses a novel external power supply reset circuit for preventing system crashes. It is a novel combined circuit that enables automatic power-off and restart of the device when the device firmware and internal watchdog fail and cannot be restored normally. This is achieved through the enable control terminal of the external watchdog and the power supply LDO / DC-DC power conversion module of the main control MCU / main control module.

[0011] 2. This utility model discloses a novel external power supply reset circuit for preventing system crashes. It uses a low-cost external watchdog timer and an existing power LDO / DC-DC converter to achieve automatic power-off restart without manual intervention. In the event of a local node malfunction, it can enable the node to power off and restart within a very short time, usually no more than a few hundred milliseconds, providing a power-on reset function for the main control MCU / wireless module. Implemented using hardware circuitry, it can automatically recover the node even in the event of a complete software malfunction. Both the recovery speed and stability are determined by the mature hardware circuitry, ensuring stable and reliable operation. Attached Figure Description

[0012] The accompanying drawings, which are provided to further illustrate the present invention and form part of this application, do not constitute an undue limitation of the present invention. In the drawings: Figure 1 This is a circuit diagram of the external watchdog circuit of this utility model; Figure 2 Circuit diagram of the main control LDO power supply circuit of this utility model; Figure 3 This is a schematic diagram of the working timing of the external watchdog of this utility model. Detailed Implementation

[0013] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The illustrative embodiments and descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0014] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the scope of protection of the present utility model. This invention is implemented using an external watchdog circuit and a hardware LDO / DC-DC power conversion module or power module. The external watchdog circuit's feed signal is provided by the main control MCU / main control module. When the local node software malfunctions or the internal watchdog fails, the main control stops outputting the feed signal WDI (WDI_P0.20). If the external watchdog does not detect the feed signal within a fixed period, it determines that the feed signal has terminated and outputs a low-level reset signal (WDO#), which is maintained for at least a certain period (e.g., 210ms). This signal is connected to the power conversion circuit LDO / DC-DC or other similar power conversion modules with an enable signal (LDO_EN), causing the power conversion module to output a low level. The duration of this low level is delayed by a certain period based on the enable signal, further enabling the MCU / main control module to complete a power-off restart, ultimately restoring the local node's main control to normal operation.

[0015] Figure 1This is an external watchdog circuit, including the VIN terminal, LDO_EN terminal, WDI terminal, resistors R411, R413, R414, and R416, capacitor C413, and chip U401. The VIN terminal is connected to one end of resistor R414. The other end of resistor R414 is connected to one end of resistor R413 and pin 1 of chip U401. The other end of resistor R413 is connected to the LDO_EN terminal. Pin 2 of chip U401 is grounded. Pin 3 of chip U401 is connected to one end of resistor R416, and the other end of resistor R416 is grounded. Pin 4 of chip U401 is connected to one end of resistor R411 and the WDI terminal, and the other end of resistor R411 is grounded. Pin 5 of chip U401 is connected to one end of capacitor C413 and the VIN terminal, and the other end of capacitor C413 is grounded. VIN is the battery input voltage (typically 3.7~4.2V). Pin 5 (VCC) of U401 powers the external watchdog timer. Pin 4 (WDI) of U405 is the watchdog input signal, provided by the MCU's signal WDI_P0.20. Pull-down resistor R411 (1MΩ) keeps the WDI pin low when there is no watchdog signal input. Pin 3 (EN#) is active low and is kept enabled by pull-down resistor R416 (1MΩ). Pin 2 (GND) of U401 is connected to the motherboard's GND, providing a reference ground level for U401. The WDO# pin is connected to the LDO enable signal LDO_EN and is externally pulled up to VIN by R414 (10kΩ) to ensure a high output when the watchdog timer is properly fed. R413 (0Ω) is a redundancy design; during debugging, the WDO# and LDO_EN signals can be disconnected to ensure normal program debugging.

[0016] Figure 2This is the power supply circuit for the main control MCU / main control module. The main control LDO power supply circuit includes chip U402, VIN terminal, LDO_EN terminal, capacitors C407, C408, C409, and C410, resistor R415, diode D401, and a 3.0V voltage output terminal. The VIN terminal is connected to one end of capacitor C407, one end of capacitor C410, one end of resistor R415, and pin 1 of chip U402. The other ends of capacitors C407 and C410 are connected to ground, and the other end of resistor R415 is connected to... Do not connect pin 3 of chip U402 to the LDO_EN terminal. Pin 2 of chip U402 is grounded. Pin 5 of chip U402 is connected to one end of diode D401, the 3.0V voltage output terminal, one end of capacitor C408, and one end of capacitor C409, respectively. The other end of diode D401 is grounded. The other ends of capacitors C408 and C409 are connected and grounded. Pin 1 of U401 is connected to the battery power supply VIN. C407 and C415 are used to filter power supply ripple and regulate voltage. Pin 3 is the enable signal CE (Chip). The Enable pin is connected to VIN via R415 (100kΩ) to ensure that the LDO outputs 3.3V to power the MCU or main control module by default. This pin is also connected to the external watchdog output signal WDO# (Watchdog Output, active low). When the watchdog is stopped, a low-level signal is output to the LDO's EN pin to complete the power-on restart of the MCU / main control module. Pin 2, GND, is connected to the logic ground signal to provide a reference ground level for the LDO. Pin 4 is the NC empty pin and can be left unconnected. Pin 5 is the LDO's power conversion output of 3.0V, otherwise it powers the main control MCU / main control module. Figure 3 This is a schematic diagram of the external watchdog's operating timing.

[0017] This invention utilizes an external watchdog timer to implement a novel combined circuit that enables automatic power-off and restart of the device when the device firmware and internal watchdog fail and cannot be restored normally. This circuit is achieved through the external watchdog timer and the enable control terminal of the power supply LDO / DC-DC power conversion module of the main control MCU / main control module.

[0018] Automatic power-off restart is achieved by using a low-cost external watchdog and an existing power supply LDO / DC-DC converter, without manual intervention. In the event of a local node malfunction, the node can be powered off and restarted in a very short time, usually within a few hundred milliseconds, providing a power-on reset function for the main control MCU / wireless module. Implemented using hardware circuitry, the node can automatically recover even in the event of a complete software malfunction. Both the recovery speed and stability are determined by the mature hardware circuitry, ensuring stable and reliable operation.

[0019] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0020] The above embodiments are merely illustrative of the technical concept of this utility model and should not be construed as limiting the scope of protection of this utility model. Any modifications made to the technical solution based on the technical concept proposed in this utility model shall fall within the scope of protection of this utility model. The implementation methods of this utility model have been described in detail above, but this utility model is not limited to the above-described implementation methods. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this utility model.

Claims

1. A novel external power supply reset circuit for preventing system crashes, characterized in that: It includes an external watchdog circuit and a main control LDO power supply circuit, which are connected together. The external watchdog circuit includes a VIN terminal, an LDO_EN terminal, a WDI terminal, resistors R411, R413, R414, and R416, a capacitor C413, and a chip U401. The VIN terminal is connected to one end of resistor R414. The other end of resistor R414 is connected to one end of resistor R413 and pin 1 of chip U401. The other end of resistor R413 is connected to the LDO_EN terminal. Pin 2 of chip U401 is grounded. Pin 3 of chip U401 is connected to one end of resistor R416, and the other end of resistor R416 is grounded. Pin 4 of chip U401 is connected to one end of resistor R411 and the WDI terminal, and the other end of resistor R411 is grounded. Pin 5 of chip U401 is connected to one end of capacitor C413 and the VIN terminal, and the other end of capacitor C413 is grounded.

2. A new anti-hang-up external power supply reset circuit according to claim 1, characterized in that: The main control LDO power supply circuit includes chip U402, VIN terminal, LDO_EN terminal, capacitors C407, C408, C409, and C410, resistor R415, diode D401, and a 3.0V voltage output terminal. The VIN terminal is connected to one end of capacitor C407, one end of capacitor C410, one end of resistor R415, and pin 1 of chip U402. The other ends of capacitors C407 and C410 are connected to and grounded. The other end of resistor R415 is connected to pin 3 of chip U402 and the LDO_EN terminal. Pin 2 of chip U402 is grounded. Pin 5 of chip U402 is connected to one end of diode D401, the 3.0V voltage output terminal, one end of capacitor C408, and one end of capacitor C409. The other end of diode D401 is grounded. The other ends of capacitors C408 and C409 are connected to and grounded.

3. A new anti-hang-up external power supply reset circuit according to claim 1, characterized in that: The chip model of the U401 is STWD100NYWY.

4. A new anti-hang-up external power supply reset circuit according to claim 1, characterized in that: The VIN terminal represents the battery input voltage, which is 3.7~4.2V.

5. A new anti-hang-up external power supply reset circuit according to claim 1, characterized in that: The chip model of the U402 is R6232B33M.

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