Power chips and storage devices
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-04
- Publication Date
- 2026-08-14
AI Technical Summary
[0004]本申请提供了电源芯片以及存储装置，以解决电源芯片功耗高以及电源转换效率低的问题
[0015]为解决上述技术问题，本申请的电源芯片通过包括逻辑电路单元以及电源单元，电源单元上设置有第一引脚以及第二引脚，第一引脚与电感的一端连接，电感的另一端与逻辑电路单元连接；第二引脚分别连接电感与逻辑电路单元。上述电感设计使电压转换效率提升，减少能量转换过程中的热损耗，达到降低整体功耗和工作温度的效果。同时保留LDO模式可确保与现有系统兼容，避免因电源方案变更导致的适配问题。这种双模式设计在保证电源稳定性的同时，通过优化能量转换路径实现功耗降低，为不同应用场景提供灵活的电源管理方案。
Smart Images
Figure CN224636816U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip structure technology, and in particular to a power chip and a storage device. Background Technology
[0002] Storage devices have problems with high power consumption and high temperature when they are working normally. It is necessary to limit the number of concurrent operations of the chip through software, but this also limits the read and write performance.
[0003] The power consumption mainly occurs in the power supply chip, and its main sources of power consumption are the large operating current of the power supply and the low efficiency of the power supply in converting the core voltage through LDO mode (low dropout linear regulator). Utility Model Content
[0004] This application provides a power chip and a storage device to solve the problems of high power consumption and low power conversion efficiency of power chips.
[0005] To solve the above-mentioned technical problems, this application provides a power chip, including: a logic circuit unit and a power supply unit. The power supply unit is provided with a first pin and a second pin. The first pin is connected to one end of an inductor, and the other end of the inductor is connected to the logic circuit unit. The second pin is connected to both the inductor and the logic circuit unit.
[0006] The inductor is located outside the power chip and is connected to the first and second pins inside the power chip via connecting wires.
[0007] The first pin and the second pin are respectively led to the corresponding pads on the power chip, so as to be connected to the inductor through the corresponding pads, so that the first pin and the second pin are respectively connected to the inductor.
[0008] A connection point is provided between the inductor and the logic circuit unit. The second pin is connected to the connection point to connect the inductor and the logic circuit unit respectively. A capacitor is also provided between the connection point and the logic circuit unit. One side of the capacitor is connected to both the connection point and the logic circuit unit, and the other side of the capacitor is grounded.
[0009] The first pin includes the power switch output pin; the second pin includes the feedback pin.
[0010] The power supply unit is also equipped with power pins, which are connected to external power lines.
[0011] The inductance value ranges from 50 to 800 nanohenries.
[0012] To address the aforementioned technical problems, this application provides a storage device, comprising: a power chip and a storage circuit board. The power chip includes any of the aforementioned power chips, the power chip is mounted on the storage circuit board, and the power pins of the power chip are connected to the power lines of the storage circuit board.
[0013] The inductor of the power chip is fixedly mounted on the storage circuit board.
[0014] The power chip has multiple pads soldered onto the storage circuit board, and the inductors are connected to the corresponding pads and the power lines are connected to the corresponding pads via the connection lines of the storage circuit board.
[0015] To address the aforementioned technical issues, the power chip of this application comprises a logic circuit unit and a power supply unit. The power supply unit has a first pin and a second pin. The first pin is connected to one end of an inductor, and the other end of the inductor is connected to the logic circuit unit. The second pin connects both the inductor and the logic circuit unit. This inductor design improves voltage conversion efficiency, reduces heat loss during energy conversion, and thus lowers overall power consumption and operating temperature. Simultaneously, retaining the LDO mode ensures compatibility with existing systems, avoiding adaptation issues caused by changes in power supply solutions. This dual-mode design, while ensuring power stability, reduces power consumption by optimizing the energy conversion path, providing a flexible power management solution for different application scenarios. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the power chip provided in this application;
[0017] Figure 2 This is a schematic diagram of an embodiment of the storage device provided in this application. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0020] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0021] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the power chip provided in this application.
[0022] The power chip 100 of this embodiment includes a logic circuit unit 120 and a power supply unit 110. The logic circuit unit 120 refers to the logic circuits in the power chip 100 that process data, such as a CPU or a memory controller. The specific composition and circuit structure can be set according to the actual needs of the power chip 100 and are not limited here.
[0023] The power supply unit 110 is provided with a first pin 111 and a second pin 112. The first pin 111 is connected to one end of the inductor L, and the other end of the inductor L is connected to the logic circuit unit 120. The second pin 112 is connected to the inductor L and the logic circuit unit 120 respectively.
[0024] In the above connection method, the power supply unit 110 can sequentially reach the logic circuit unit 120 through the first pin 111 and the inductor L. During this process, the inductor L can store energy when it is turned on and release energy to the logic circuit unit 120 when it is turned off. This process has no resistive loss, thereby improving power efficiency, reducing power consumption of the power chip 100, and lowering the operating temperature of the power chip 100. Furthermore, the power supply unit 110 can also directly reach the logic circuit unit 120 through the second pin 112, i.e., LDO mode. This allows the power chip 100 to be set to two power supply modes, enabling it to select any power supply mode according to actual needs, increasing the power supply flexibility of the power chip 100, and reducing the current loss during operation.
[0025] With the above structure, the power chip in this embodiment includes a logic circuit unit and a power supply unit. The power supply unit has a first pin and a second pin. The first pin is connected to one end of an inductor, and the other end of the inductor is connected to the logic circuit unit. The second pin is connected to both the inductor and the logic circuit unit. This inductor design improves voltage conversion efficiency, reduces heat loss during energy conversion, and achieves the effect of reducing overall power consumption and operating temperature. Retaining the LDO mode ensures compatibility with existing systems and avoids adaptation problems caused by changes in power supply solutions. This dual-mode design ensures power stability while reducing power consumption by optimizing the energy conversion path, providing a flexible power management solution for different application scenarios.
[0026] In some embodiments, the inductor L is located outside the power chip 100, and the inductor L is connected to the first pin 111 and the second pin 112 inside the power chip 100 via connecting lines (not shown in the figure).
[0027] By moving the inductor L from the power chip 100 to an external location, the chip structure design is optimized. This allows for the addition of the inductor L without increasing the height of the power chip 100, thus facilitating miniaturization. Furthermore, externalizing the inductor L effectively reduces the heat source density inside the power chip 100, preventing performance degradation of internal components due to high temperatures. The external inductor L layout also allows for the use of larger inductance components to improve power conversion efficiency.
[0028] In some embodiments, the first pin 111 and the second pin 112 are respectively led to the corresponding pads (not shown) of the power chip 100 to be connected to the inductor L through the corresponding pads, so that the first pin 111 and the second pin 112 are respectively connected to the inductor L.
[0029] In this configuration, the first pin 111 and the second pin 112 are connected to the inductor L via pads, which serve as physical interfaces to enable electrical communication between the pins and the inductor L. This connection method allows the inductor L to be placed outside the power supply chip 100, rather than integrated inside the power supply chip 100.
[0030] In some embodiments, a connection point 130 is provided between the inductor L and the logic circuit unit 120, and the second pin 112 is connected to the connection point 130 to connect the inductor L and the logic circuit unit 120 respectively; a capacitor C is also provided between the connection point 130 and the logic circuit unit 120, one side of the capacitor C is connected to the connection point 130 and the logic circuit unit 120 respectively, and the other side of the capacitor C is grounded.
[0031] The capacitor C mentioned above has a filtering function, which stabilizes the input / output voltage by suppressing power supply noise; it can also cope with load changes and reduce voltage fluctuations; and by grounding, it optimizes noise suppression and system reliability.
[0032] In some embodiments, the first pin 111 includes a power switch output pin (Switch Node); the second pin 112 includes a feedback pin.
[0033] The power switch output pin (SW pin) controls the switching action to achieve voltage conversion. The feedback pin (FB pin) monitors the output voltage and provides a feedback signal to regulate the conversion process. In practice, connecting the power switch output pin to an inductor can form a DC-DC conversion loop. When an external inductor L is not required, the feedback pin can be directly used as the voltage regulation terminal in LDO mode, achieving low-efficiency but low-complexity voltage conversion through internal circuitry. This design allows selection of DC-DC or LDO operating mode according to actual needs.
[0034] In some embodiments, the power supply unit 110 is further provided with a power supply pin 113, which is connected to an external power line to supply power to the power chip 100.
[0035] In some embodiments, the inductance value of inductor L ranges from 50 to 800 nanohenries, specifically including but not limited to 50 nanohenries, 60 nanohenries, 80 nanohenries, 100 nanohenries, 110 nanohenries, 150 nanohenries, 180 nanohenries, 220 nanohenries, 260 nanohenries, 280 nanohenries, 300 nanohenries, 350 nanohenries, 390 nanohenries, 400 nanohenries, 460 nanohenries, 470 nanohenries, 500 nanohenries, 580 nanohenries, 620 nanohenries, 670 nanohenries, 690 nanohenries, 700 nanohenries, 720 nanohenries, 760 nanohenries, 790 nanohenries, or 800 nanohenries.
[0036] By setting the inductance value within the 50-800 nanohenry range, power conversion efficiency can be optimized and power consumption reduced. When the inductance value is within this range, energy conversion losses in DC-DC mode are significantly reduced. For example, a 50 nanohenry inductor can reduce high-frequency switching losses, and an 800 nanohenry inductor can reduce output current ripple, thereby improving overall energy efficiency. At the same time, inductance values within this range can ensure voltage stability in LDO mode, avoiding voltage oscillations caused by too small an inductance value or dynamic response delays caused by too large an inductance value.
[0037] Please refer to further information. Figure 2 , Figure 2 This is a schematic diagram of an embodiment of the storage device provided in this application.
[0038] The storage device 200 of this embodiment includes a power chip 100 and a storage circuit board 210. The power chip 100 is mounted on the storage circuit board 210, and the power pin 113 of the power chip 100 is connected to the power line (not shown) of the storage circuit board 210.
[0039] In this embodiment, the power chip 100 includes any of the power chip 100 described in the above embodiments. Therefore, the power chip 100 of the storage device 200 in this embodiment improves voltage conversion efficiency through inductor design, reduces heat loss during energy conversion, and achieves the effect of reducing overall power consumption and operating temperature. Simultaneously, retaining the LDO mode ensures compatibility with existing systems and avoids adaptation problems caused by changes in power solutions. This dual-mode design ensures power stability while reducing power consumption by optimizing the energy conversion path, providing a flexible power management solution for different application scenarios.
[0040] In some embodiments, the inductor L of the power chip 100 is fixedly mounted on the storage circuit board 210.
[0041] In some embodiments, multiple pads 150 of the power chip 100 are soldered onto the storage circuit board 210 to connect the inductor L to the corresponding pad 150 and the power line to the corresponding pad 150 via the connection lines of the storage circuit board 210.
[0042] In a specific application scenario, the power chip 100 can have both the SW and FB pins brought out to pad 150, allowing for external circuit configuration. When the user selects to install inductor L on the storage circuit board 210, the power chip 100 enters DC-DC mode, with inductor L externally mounted. When the user selects not to install inductor L, the FB pin can directly power the digital section, and the circuit operates in LDO mode. Switching between the two modes is achieved through external circuit configuration, retaining the traditional LDO solution while providing an efficient DC-DC solution. The inductor can be implemented using different materials or structures, such as high-frequency magnetic materials or specific winding methods. The signal connections between the SW and FB pins can use different wiring methods to meet circuit requirements.
[0043] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A power supply chip, characterized by comprising: include: Logic circuit unit; The power supply unit has a first pin and a second pin. The first pin is connected to one end of an inductor, and the other end of the inductor is connected to the logic circuit unit. The second pin is connected to both the inductor and the logic circuit unit.
2. The power supply chip of claim 1, wherein, The inductor is located outside the power chip, and the inductor is connected to the first pin and the second pin inside the power chip via connecting wires.
3. The power supply chip of claim 2, wherein, The first pin and the second pin are respectively led to the corresponding pads of the power chip and connected to the inductor through the corresponding pads, so that the first pin and the second pin are respectively connected to the inductor.
4. The power supply chip of claim 1, wherein, A connection point is provided between the inductor and the logic circuit unit, and the second pin is connected to the connection point to connect the inductor and the logic circuit unit respectively. A capacitor is also provided between the connection point and the logic circuit unit. One side of the capacitor is connected to both the connection point and the logic circuit unit, and the other side of the capacitor is grounded.
5. The power supply chip of claim 1, wherein, The first pin includes a power switch output pin; the second pin includes a feedback pin.
6. The power supply chip of claim 1, wherein, The power supply unit is also provided with a power pin, which is connected to an external power line.
7. The power supply chip of claim 1, wherein, The inductance value of the inductor ranges from 50 to 800 nanohenries.
8. A memory device, comprising: The storage device includes: Power chip, the power chip comprising the power chip according to any one of claims 1-7; A storage circuit board, wherein the power chip is mounted on the storage circuit board and the power pins of the power chip are connected to the power lines of the storage circuit board.
9. The memory device of claim 8, wherein, The inductor of the power chip is fixedly mounted on the storage circuit board.
10. The memory device of claim 8, wherein, The power chip has multiple pads soldered onto the storage circuit board, so that the inductor and the corresponding pad are connected, and the power line and the corresponding pad are connected, respectively, through the connection lines of the storage circuit board.