A power-loss data retention system

Abstract

This application provides a power-down data retention system, which includes an embedded processor, a power-down detection circuit, a non-volatile static random access memory (SRAM), and a non-volatile memory. The power-down detection circuit, SRAM, and non-volatile memory are all connected to the embedded processor, and the power-down detection circuit is also connected to the main power supply of the power-down data retention system. This application solves the technical problem of data loss due to power failure in embedded systems, which disrupts the continuity of subsequent processes, by using a power-down detection circuit and different types of memory.

Description

Technical Field

[0001] This application relates to the field of embedded device operation and maintenance technology, and in particular to a power-down data retention system. Background Technology

[0002] In the field of industrial control, PLC (Programmable Controller) devices often face sudden power outages. Once a PLC device loses power, it faces the problem of losing critical data. Even after restarting, the loss of data will affect the continuity of subsequent production processes. Utility Model Content

[0003] In view of this, the purpose of this application is to provide at least one power-down data retention system, which solves the technical problem of data loss due to power failure in embedded systems, thereby disrupting the continuity of subsequent processes, through power failure detection circuit and different types of memory.

[0004] This application mainly includes the following aspects: In a first aspect, embodiments of this application provide a power-down data retention system, which includes an embedded processor, a power-down detection circuit, a non-volatile static random access memory (SRAM), and a non-volatile memory; wherein the power-down detection circuit, the SRAM, and the non-volatile memory are respectively connected to the embedded processor, and the power-down detection circuit is also connected to the main power supply of the power-down data retention system.

[0005] In one possible implementation, the power-down detection circuit is responsible for sending the detected power-down signal to the embedded processor. After receiving the power-down signal, the embedded processor saves the power-down data to non-volatile memory and non-volatile static random access memory.

[0006] In one possible implementation, the power-down data retention system further includes a power-down retention circuit, which is connected to both the power-down detection circuit and the embedded processor.

[0007] In one possible implementation, the power failure detection circuit is also responsible for sending the detected power failure signal to the power failure retention circuit, which is responsible for maintaining a delayed power supply for at least a predetermined time after the power failure.

[0008] In one possible implementation, the power-down data retention system also includes a clock module connected to the embedded processor.

[0009] In one possible implementation, the power-down detection circuit includes a first capacitor, a second capacitor, a third capacitor, a power-down detection chip, a first resistor, a second resistor, and a fourth capacitor. The power supply pins of the power-down detection chip are connected to the system power supply input and grounded through the first capacitor. The detection pins of the power-down detection chip are connected to the power-down monitoring voltage and grounded through the second capacitor. The reset delay programming pin of the power-down detection chip is grounded through the third capacitor. The open-drain output pin of the power-down detection chip outputs a power-down signal and is connected to the power-down holding circuit through the first resistor, to the reference voltage through the first and second resistors, and grounded through the first resistor and the fourth capacitor. The ground pin of the power-down detection chip is grounded.

[0010] In one possible implementation, the power-down retention circuit includes a charging module, a backup power supply, and a power supply switching control module. The first input terminal of the charging module is connected to the main power supply and the first input terminal of the power supply switching control module, respectively. The main power supply is connected to the system power supply input terminal. The second input terminal of the charging module is connected to the power-down signal output by the power-down detection circuit. The output terminal of the charging module is connected to the second input terminal of the power supply switching control module and the backup power supply, respectively. The output terminal of the power supply switching control module is connected to the system power supply input terminal.

[0011] In one possible implementation, the charging module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a charging chip. The first power input pin and the second power input pin of the charging chip are connected to the main power supply, the first input terminal of the power supply switching control module, one end of the third resistor, one end of the fourth resistor, and one end of the fifth resistor, respectively. The other end of the third resistor is connected to the enable pin of the charging chip. The other end of the fourth resistor is connected to the open-drain output pin of the charging chip and, through the sixth resistor, to the positive input return pin of the charging chip. The other end of the fifth resistor is connected to the clamping voltage selection pin of the charging chip and grounded through the seventh resistor. The positive output pin of the charging chip is connected to a power-down signal through the eighth resistor. The first power output pin and the second power output pin of the charging chip are connected to the second input terminal of the power supply switching control module and the backup power supply, respectively. The charging current setting pin of the charging chip is grounded after being connected to the ground pin of the charging chip through the ninth resistor.

[0012] In one possible implementation, the backup power supply includes a first supercapacitor and a second supercapacitor, wherein one end of the first supercapacitor is connected to the second input terminal of the power supply switching control module and the output terminal of the charging module, the other end of the first supercapacitor is connected to one end of the second supercapacitor and the voltage balance detection pin of the charging chip in the charging module, and the other end of the second supercapacitor is grounded.

[0013] In one possible implementation, the power supply switching control module includes a driver chip, a tenth resistor, a diode, a first control switch, and a second control switch. The drain pin of the first control switch is connected to the first input terminal of the charging module and the main power supply, respectively. The drain pin of the second control switch and the anode of the diode are both connected to the output terminal of the charging module. The cathode of the diode is connected to the input pin of the driver chip. The ground pin of the driver chip is connected to the control pin of the driver chip and then grounded. The detection pin of the driver chip is connected to the source pin of the first control switch, the source pin of the second control switch, and the system power supply input terminal, respectively. The gate drive pin of the driver chip is connected to the gate pin of the second control switch. The status indication pin of the driver chip is connected to the gate pin of the first control switch and to the system power supply input terminal through the tenth resistor, respectively.

[0014] This application provides a power-down data retention system, which includes an embedded processor, a power-down detection circuit, a non-volatile static random access memory (SRAM), and a non-volatile memory. The power-down detection circuit, SRAM, and non-volatile memory are all connected to the embedded processor, and the power-down detection circuit is also connected to the main power supply of the power-down data retention system. This application solves the technical problem of data loss due to power failure in embedded systems, which disrupts the continuity of subsequent processes, by using a power-down detection circuit and different types of memory.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This illustration shows a schematic diagram of a power-down data retention system provided in an embodiment of this application; Figure 2 This paper shows a schematic diagram of a power-down detection circuit provided in an embodiment of this application. Figure 3 This illustration shows one of the structural schematic diagrams of a power-down retention circuit provided in an embodiment of this application; Figure 4 This illustration shows one of the structural schematic diagrams of a power-down retention circuit provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] In the field of industrial control, PLC (Programmable Controller) devices often face sudden power outages. Once a PLC device loses power, it faces the problem of losing critical data. Even after restarting, the loss of data will affect the continuity of subsequent production processes.

[0021] Based on this, this application provides a power-down data retention system, which solves the technical problem of data loss due to power failure in embedded systems, thus disrupting the continuity of subsequent processes, by using a power-down detection circuit and different types of memory. Specifically, the system is as follows: Please see Figure 1 , Figure 1 A schematic diagram of a power-down data retention system provided in an embodiment of this application is shown. Figure 1 As shown, the power-down data retention system provided in this application embodiment includes an embedded processor 1, a power-down detection circuit 2, a non-volatile static random access memory (NVSRAM), and a non-volatile memory (Flash). The power-down detection circuit 2, the NVSRAM, and the Flash are respectively connected to the embedded processor 1. The power-down detection circuit 2 is also connected to the main power supply POWERm of the power-down data retention system.

[0022] Preferred, such as Figure 1 As shown, the power-down data retention system also includes a power-down retention circuit 3 and a clock module 4. The power-down retention circuit 3 is connected to the embedded processor 1 and the power-down detection circuit 2, respectively, and the clock module 4 is connected to the embedded processor 1.

[0023] In one specific embodiment, the embedded processor 1 is connected to the non-volatile static random access memory (NVSRAM) via SPI (Serial Peripheral Interface), the embedded processor 1 is connected to the non-volatile memory (Flash) via QSPI, and the embedded processor 1 is connected to the clock module 4 via the IIC interface.

[0024] In a preferred embodiment, the power failure detection circuit 2 is responsible for monitoring whether the main power supply POWERm has lost power, and sends the detected power failure signal Pwr_Fall# to the embedded processor 1. After receiving the power failure signal Pwr_Fall#, the embedded processor 1 saves the power failure data to non-volatile memory Flash and non-volatile static random access memory NVSRAM.

[0025] In one specific embodiment, the power-down data includes pre-set power-down protection data and power-down storage data. The power-down protection data includes pre-defined key data involved in the operation of the embedded device, such as key process parameters and key program operation parameters. This is pre-configured data and is not specifically limited here. The power-down storage data is pre-defined storage information related to the power-down protection data in the non-volatile memory Flash, such as including but not limited to at least one of the following: the logical address, physical address, CRC checksum, timestamp, erasure count, and identification information of the storage area occupied by the power-down protection data in the non-volatile memory Flash.

[0026] In a preferred embodiment, the power failure detection circuit 2 is also responsible for sending the detected power failure signal to the power failure holding circuit 3, which is responsible for maintaining a delayed power supply for at least a predetermined time after the power failure, specifically, the predetermined time is 1 second.

[0027] In a preferred embodiment, please refer to Figure 2 , Figure 2 A schematic diagram of a power-down detection circuit provided in an embodiment of this application is shown. Figure 2 As shown, the power failure detection circuit 2 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a power failure detection chip U1, a first resistor R1, a second resistor R2, and a fourth capacitor C4.

[0028] Among them, the power supply pin VDD of the power-down detection chip U1 is connected to the system power supply input terminal P1 and grounded to GND through the first capacitor C1; the detection pin SENSE of the power-down detection chip U1 is connected to the main power supply POWERm and grounded to GND through the second capacitor C2; the reset delay programming pin CT of the power-down detection chip U1 is grounded to GND through the third capacitor C3; and the open-drain output pin of the power-down detection chip U1... The output power-down signal Pwr_Fall# is connected to the power-down retention circuit through the first resistor R1, to the reference voltage 3V3 through the first resistor R1 and the second resistor R2, and to ground GND through the first resistor R1 and the fourth capacitor C4. The ground pin GND of the power-down detection chip U1 is grounded to GND. The manual reset input pin of the power-down detection chip U1 is also connected to GND. Suspended in mid-air.

[0029] Preferably, the power failure detection chip U1 is model TPS3808G50DBCR.

[0030] In this application, the system power input terminal P1 is connected to the system operating voltage provided by the main power supply POWERm or the backup power supply POWERs.

[0031] In a preferred embodiment, the power-down detection circuit provided in this application uses a voltage monitoring chip U1 as the power-down detection chip. When the detection pin SENSE of the power-down detection chip U1 detects that the voltage of the main power supply POWERm has dropped to a given threshold, the open-drain output pin of the power-down detection chip U1 will trigger an alarm. Output a power-down signal Pwr_Fall# (level signal) and send it to embedded processor 1 and power-down retention circuit 3. When embedded processor 1 receives the power-down signal Pwr_Fall#, it indicates that the system has lost power, which triggers the power-down data protection action. When power-down retention circuit 3 receives the power-down signal Pwr_Fall#, it triggers the backup power supply to maintain power to the power-down data retention system for at least a predetermined time. In a preferred embodiment, please refer to Figure 3 , Figure 3 This illustration shows one of the structural schematic diagrams of a power-down retention circuit provided in an embodiment of this application. For example... Figure 3As shown, the power-down retention circuit 3 includes a charging module 31, a backup power supply POWERs, and a power supply switching control module 32. The first input terminal of the charging module 31 is connected to the main power supply POWERm and the first input terminal of the power supply switching control module 32, respectively. The second input terminal of the charging module 31 is connected to the power-down signal Pwr_Fall# output by the power-down detection circuit 2. The output terminal of the charging module 31 is connected to the second input terminal of the power supply switching control module 32 and the backup power supply POWERs, respectively. The output terminal of the power supply switching control module 32 is connected to the system power supply input terminal P1.

[0032] In a preferred embodiment, please refer to Figure 4 , Figure 4 This is a second schematic diagram of a power-down retention circuit provided in an embodiment of this application. For example... Figure 4 As shown, the charging module 31 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a charging chip U2.

[0033] The power supply switching control module 32 includes a driver chip U3, a tenth resistor R10, a diode D1, a first control switch Q1, and a second control switch Q2.

[0034] Preferably, after the first power input pin VIN1 and the second power input pin VIN2 of the charging chip U2 are connected, they are respectively connected to the main power supply POWERm, the drain pins D1~D4 of the first control switch Q1, one end of the third resistor R3, one end of the fourth resistor R4, and one end of the fifth resistor R5. The other end of the third resistor R3 is connected to the enable pin EN of the charging chip U2. The other end of the fourth resistor R4 is connected to the open-drain output pin PFI of the charging chip U2 and to the positive input return pin PFI_RET of the charging chip U2 through the sixth resistor R6. The other end of the fifth resistor R5 is connected to the clamp voltage selection pin SEL of the charging chip U2 and to ground GND through the seventh resistor R7. The positive output pin PFO of the charging chip U2 is connected to the power-down signal Pwr_Fall# through the eighth resistor R8.

[0035] After the first power output pin VOUT1 and the second power output pin VOUT2 of the charging chip U2 are connected, they are respectively connected to the drain pins D1~D4 of the second control switch Q2 and the backup power supply POWERs. The charging current setting pin PROG of the charging chip U2 is connected to the ground pin GND of the charging chip U2 through the ninth resistor R9 and then grounded to GND.

[0036] Preferably, the backup power supplies include a first supercapacitor Cp1 and a second supercapacitor Cp2. One end of the first supercapacitor Cp1 is connected to the drain pins D1~D4 of the second control switch Q2 and the first power output pin VOUT1 and the second power output pin VOUT2 of the charging chip U2, respectively. The other end of the first supercapacitor Cp1 is connected to one end of the second supercapacitor Cp2 and the voltage balance detection pin VMID of the charging chip U2, respectively. The other end of the second supercapacitor Cp2 is grounded to GND.

[0037] In a preferred embodiment, the first power output pin VOUT1 and the second power output pin VOUT2 of the charging chip U2 are also connected to the anode of the diode D1. The cathode of the diode D1 is connected to the input pin VIN of the driver chip U3. The ground pin GND of the driver chip U3 is connected to the control pin CTL of the driver chip U3 and then grounded to GND. The detection pin SENSE of the driver chip U3 is connected to the source pins S1~S3 of the first control switch Q1, the source pins S1~S3 of the second control switch Q2, and the system power input terminal P1, respectively. The gate drive pin GATE of the driver chip U3 is connected to the gate pin G of the second control switch Q2. The status indicator pin STAT of the driver chip U3 is connected to the gate pin G of the first control switch Q1 and to the system power input terminal P1 through the tenth resistor R10, respectively.

[0038] In one specific embodiment, the charging chip is selected as LTC4425EMSE, the driver chip U3 is selected as LTC4412ES6, the first control switch Q1 and the second control switch Q2 are selected as SI4421DY, and the first supercapacitor Cp1 and the second supercapacitor Cp2 are selected as BCAP0025-P270-S12.

[0039] In one specific embodiment, the power-down retention circuit 3 provided in this application has a charging module 31 that charges the first supercapacitor Cp1 and the second supercapacitor Cp2, and a driver chip U3 used to switch the power supply mode of the power-down data retention system. The first control switch Q1 and the second control switch Q2 are two MOSFETs.

[0040] When the power-down data retention system is in normal working condition with the main power supply POWERm, the power-down signal Pwr_Fall# is a level signal indicating that the system has not experienced a power failure. At this time, the charging chip U1 captures this signal and charges the first supercapacitor Cp1 and the second supercapacitor Cp2. The detection pin SENSE of the driver chip U3 detects that the main power supply POWERm is normally connected, controls the first control switch to be turned on, and the second control switch to be turned off, so that the main power supply POWERm continuously provides the working voltage of the power-down data retention system.

[0041] When the power-down data retention system is in a power-down state, i.e., the power-down signal Pwr_Fall# is a level signal indicating that the system has lost power, the charging chip U1 captures this signal and stops charging the first supercapacitor Cp1 and the second supercapacitor Cp2. The detection pin SENSE of the driver chip U3 detects that the main power supply POWERm is disconnected, controls the second control switch to turn on, and the first control switch to turn off. The first supercapacitor Cp1 and the second supercapacitor Cp2 replace the main power supply POWERm as backup power supplies to maintain a delayed power supply for a predetermined time to support the retention of power-down data.

[0042] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power fail data retention system, comprising: The power-down data retention system includes an embedded processor, a power-down detection circuit, a non-volatile static random access memory, and a non-volatile memory. The power-down detection circuit, the non-volatile static random access memory, and the non-volatile memory are respectively connected to the embedded processor, and the power-down detection circuit is also connected to the main power supply of the power-down data retention system.

2. The power fail data retention system of claim 1, wherein, The power failure detection circuit is responsible for sending the detected power failure signal to the embedded processor. After receiving the power failure signal, the embedded processor saves the power failure data to non-volatile memory and non-volatile static random access memory.

3. The power fail data retention system of claim 1, wherein, The power-loss data retention system also includes a power-loss retention circuit. The power-down retention circuit is connected to both the power-down detection circuit and the embedded processor.

4. The power fail data retention system of claim 3 wherein, The power failure detection circuit is also responsible for sending the detected power failure signal to the power failure holding circuit, which is responsible for maintaining power supply for at least a predetermined time after the power failure.

5. The power fail data retention system of claim 1, wherein, The power-down data retention system also includes a clock module. The clock module is connected to the embedded processor.

6. The power fail data retention system of claim 1, wherein, The power failure detection circuit includes a first capacitor, a second capacitor, a third capacitor, a power failure detection chip, a first resistor, a second resistor, and a fourth capacitor. The power supply pins of the power-down detection chip are connected to the system power supply input terminal and grounded through a first capacitor. The detection pins of the power-down detection chip are connected to the power-down monitoring voltage and grounded through a second capacitor. The reset delay programming pin of the power-down detection chip is grounded through a third capacitor. The open-drain output pin of the power-down detection chip outputs a power-down signal and is connected to the power-down holding circuit through a first resistor, connected to the reference voltage through a first resistor and a second resistor, and grounded through a first resistor and a fourth capacitor. The grounding pin of the power-down detection chip is grounded.

7. The power fail data retention system of claim 3 wherein, The power-down retention circuit includes a charging module, a backup power supply, and a power supply switching control module. The first input terminal of the charging module is connected to the main power supply and the first input terminal of the power supply switching control module. The main power supply is connected to the system power supply input terminal. The second input terminal of the charging module is connected to the power failure signal output by the power failure detection circuit. The output terminal of the charging module is connected to the second input terminal of the power supply switching control module and the backup power supply. The output terminal of the power supply switching control module is connected to the system power supply input terminal.

8. The power fail data retention system of claim 7 wherein, The charging module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a charging chip. After the first power input pin and the second power input pin of the charging chip are connected, they are respectively connected to the main power supply, the first input terminal of the power supply switching control module, one end of the third resistor, one end of the fourth resistor, and one end of the fifth resistor. The other end of the third resistor is connected to the enable pin of the charging chip. The other end of the fourth resistor is connected to the open-drain output pin of the charging chip and to the positive input return pin of the charging chip through the sixth resistor. The other end of the fifth resistor is connected to the clamping voltage selection pin of the charging chip and to ground through the seventh resistor. The positive output pin of the charging chip is connected to the power-down signal through the eighth resistor. After the first power output pin and the second power output pin of the charging chip are connected, they are respectively connected to the second input terminal of the power supply switching control module and the backup power supply. The charging current setting pin of the charging chip is grounded after being connected to the ground pin of the charging chip through the ninth resistor.

9. The power fail data retention system of claim 7 wherein, The backup power supply includes a first supercapacitor and a second supercapacitor. One end of the first supercapacitor is connected to the second input terminal of the power supply switching control module and the output terminal of the charging module, respectively. The other end of the first supercapacitor is connected to one end of the second supercapacitor and the voltage balance detection pin of the charging chip in the charging module, respectively. The other end of the second supercapacitor is grounded.

10. The power fail data retention system of claim 7 wherein, The power supply switching control module includes a driver chip, a tenth resistor, a diode, a first control switch, and a second control switch. The drain pin of the first control switch is connected to the first input terminal of the charging module and the main power supply, respectively. The drain pin of the second control switch and the anode of the diode are both connected to the output terminal of the charging module. The cathode of the diode is connected to the input pin of the driver chip. The ground pin of the driver chip is connected to the control pin of the driver chip and then grounded. The detection pin of the driver chip is connected to the source pin of the first control switch, the source pin of the second control switch and the system power supply input terminal, respectively. The gate drive pin of the driver chip is connected to the gate pin of the second control switch. The status indicator pin of the driver chip is connected to the gate pin of the first control switch and connected to the system power supply input terminal through the tenth resistor, respectively.

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