LCD timing control circuit

Abstract

This invention proposes a liquid crystal timing control circuit, comprising: multiple control terminals, each configured to output a timing control signal; and multi-stage delay circuits, wherein the input terminal of each subsequent delay circuit is coupled to the output terminal of the preceding delay circuit, and the output terminal of each delay circuit is coupled to a corresponding control terminal; the preceding delay circuit is configured to output its generated timing control signal as a trigger signal to the subsequent delay circuit, thereby sequentially triggering the subsequent delay circuits to generate corresponding timing control signals. This liquid crystal timing control circuit is simple, stable, and low-cost, generating different timing control signals through hardware circuitry, thus reducing the overhead of the controller's GPIO ports.

Description

Technical Field

[0001] This invention relates to a liquid crystal timing control circuit. Background Technology

[0002] LCD screens are widely used in various electronic devices as display terminals. The stable operation of their display systems depends on the strict timing control signal power-on timing requirements. If the timing control requirements are not met, it will usually cause display abnormalities such as black screen or distorted screen. In the prior art, in order to meet the timing requirements of key timing control signals such as RSTB (reset), STBYB (standby), DISON (display on), and BLON (backlight on) of LCD screens, the common practice is to use software programming to realize the sequential output and delay control of signals through the GPIO pins of the controller (such as MCU or SOC). However, the above software control scheme has the following defects: (1) It requires multiple GPIO pins of the controller, which leads to the shortage of system hardware interface resources. In order to meet the requirements of multiple GPIO pins, a higher configuration controller must be selected, which directly leads to an increase in hardware cost; (2) It requires writing complex timing control programs, and the optimization and upgrading of software programs may change the signal delay parameters, resulting in timing abnormalities.

[0003] Therefore, how to replace traditional software control with hardware circuit design to simplify the system structure and improve timing stability has become an urgent technical problem to be solved in the design of LCD display systems. Utility Model Content

[0004] According to one aspect of the present invention, a liquid crystal timing control circuit is provided, comprising: a plurality of control terminals, each control terminal configured to output a timing control signal; a multi-stage delay circuit, wherein the input terminal of a subsequent stage delay circuit is coupled to the output terminal of a preceding stage delay circuit, and the output terminal of each stage delay circuit is respectively coupled to a corresponding control terminal; the preceding stage delay circuit is configured to output its generated timing control signal as a trigger signal to the subsequent stage delay circuit, so as to sequentially trigger the subsequent stage delay circuit to generate corresponding timing control signals; wherein the delay circuit comprises:

[0005] A first resistor, a first capacitor, a first transistor, a first diode, and a second transistor;

[0006] Wherein, one end of the first resistor is coupled to the input terminal of this stage, the other end of the first resistor is coupled to one end of the first capacitor and one end of the first diode, and the other end of the first capacitor is grounded;

[0007] The other end of the first diode is coupled to the base of the first transistor, the collector of the first transistor is coupled to the base of the second transistor, the emitter of the second transistor is coupled to a power supply terminal, and the collector of the second transistor is coupled to the output terminal and the corresponding control terminal of this stage, outputting the corresponding timing control signal.

[0008] In one embodiment of this novel invention, the delay circuit further includes:

[0009] A second resistor, one end of which is coupled to the collector of the first transistor, and the other end of which is coupled to the base of the second transistor.

[0010] In one embodiment of this novel invention, the delay circuit further includes:

[0011] A third resistor, one end of which is coupled to the collector of the first transistor, and the other end of which is coupled to the power supply terminal.

[0012] In one embodiment of this novel invention, the first transistor and the second transistor are bipolar transistors, and the...

[0013] The first transistor is a PNP transistor, and the second transistor is an NPN transistor.

[0014] In one embodiment of this novel diode, the first diode is a common forward-conducting diode, one end of the first diode is the anode, and the anode is coupled to one end of the first capacitor; the other end of the first diode is the cathode, and the cathode is coupled to the base of the first transistor.

[0015] In one embodiment of this novel diode, the first diode is a Zener diode, one end of the first diode is a cathode, and the cathode is coupled to one end of the first capacitor; the other end of the first diode is an anode, and the anode is coupled to the base of the first transistor.

[0016] In one embodiment of this invention, the delay duration of each stage of the delay circuit is the same, and the same delay circuit is used, wherein the first diode of the delay circuit is a common forward-conducting diode or a Zener diode.

[0017] In one embodiment of this novel circuit, at least one stage of delay circuit has a different delay duration than the other stages of delay circuit. The at least one stage of delay circuit and the other stages of delay circuit employ different delay circuits. The first diode of the delay circuit corresponding to the stage with the larger delay duration is a Zener diode, and the first diode of the delay circuit corresponding to the stage with the smaller delay duration is a common forward-conducting diode.

[0018] In one embodiment of this novel invention, the plurality of control terminals include a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal;

[0019] The multi-stage delay circuit includes a first-stage delay circuit, a second-stage delay circuit, a third-stage delay circuit, and a fourth-stage delay circuit cascaded in sequence. The input terminal of the first-stage delay circuit is coupled to the power supply terminal, and the output terminal is coupled to the first control terminal, outputting a first timing control signal. The output terminal of the second-stage delay circuit is coupled to the second control terminal, outputting a second timing control signal. The output terminal of the third-stage delay circuit is coupled to the third control terminal, outputting a third timing control signal. The output terminal of the fourth-stage delay circuit is coupled to the fourth control terminal, outputting a fourth timing control signal.

[0020] The first-stage delay circuit, the second-stage delay circuit, the third-stage delay circuit, and the fourth-stage delay circuit all use the same delay circuit, wherein the first diode in the delay circuit is a common forward-conducting diode.

[0021] In one embodiment of this novel invention, the plurality of control terminals include a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal;

[0022] The multi-stage delay circuit includes a first-stage delay circuit, a second-stage delay circuit, a third-stage delay circuit, and a fourth-stage delay circuit cascaded in sequence. The input terminal of the first-stage delay circuit is coupled to the power supply terminal, and the output terminal is coupled to the first control terminal, outputting a first timing control signal. The output terminal of the second-stage delay circuit is coupled to the second control terminal, outputting a second timing control signal. The output terminal of the third-stage delay circuit is coupled to the third control terminal, outputting a third timing control signal. The output terminal of the fourth-stage delay circuit is coupled to the fourth control terminal, outputting a fourth timing control signal.

[0023] The first-stage delay circuit, the second-stage delay circuit, and the third-stage delay circuit all use the same delay circuit, and the first diode of the delay circuit is a common forward-conducting diode; the first diode of the fourth-stage delay circuit is a Zener diode.

[0024] According to another aspect of the present invention, a liquid crystal display device is provided, comprising a liquid crystal display and a liquid crystal timing control circuit employing the above-described method, wherein a plurality of control terminals of the liquid crystal timing control circuit are coupled to corresponding pins of the liquid crystal display.

[0025] As can be seen from the above solutions, the advantages of this new invention are:

[0026] This novel LCD timing control circuit utilizes a multi-stage cascaded delay circuit. Each stage is based on the RC charging delay characteristic, combined with the voltage drop of a common forward-conducting diode or the reverse breakdown voltage of a Zener diode, and the conduction characteristics of a transistor to achieve delay duration control. It sequentially outputs timing control signals of different timing sequences, enabling the hardware circuit to generate different timing control signals for use in LCD timing control. This LCD timing control circuit is simple, stable, and low-cost, reducing the overhead of the controller's GPIO ports by generating different timing control signals from hardware.

[0027] To provide a better understanding of the above and other aspects of this invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0028] Figure 1 A block diagram of a liquid crystal timing control circuit according to the present invention is shown;

[0029] Figure 2 A block diagram illustrating an example of a liquid crystal display device according to the present invention;

[0030] Figure 3 A block diagram illustrating the delay circuit of the liquid crystal timing control circuit provided in one embodiment of the present invention is shown;

[0031] Figure 4 A block diagram illustrating the delay circuit of the liquid crystal timing control circuit provided in another embodiment of the present invention is shown;

[0032] Figure 5A A block diagram of a liquid crystal timing control circuit according to a first embodiment of the present invention is shown;

[0033] Figure 5B A block diagram of a liquid crystal timing control circuit according to a second embodiment of the present invention is shown;

[0034] Figure 5C A block diagram of a liquid crystal timing control circuit according to a third embodiment of the present invention is shown;

[0035] Figure 6A A specific example of a liquid crystal timing control circuit according to an embodiment of the present invention is illustrated;

[0036] Figure 6B A specific example of a liquid crystal timing control circuit according to another embodiment of the present invention is illustrated.

[0037] In the attached figures, the following labels are used:

[0038] 100, 200, 300: LCD timing control circuit;

[0039] 400: LCD display;

[0040] 101_1...101_n: Control terminals;

[0041] 102_1..102_n、102'、102”: Delay circuit;

[0042] ctr_1...ctr_n, RSTB, STBYB, DISON, BLON: Timing control signals;

[0043] 102_in: Input terminal;

[0044] 102_out: Output terminal;

[0045] R1: First resistor;

[0046] C1: First capacitor;

[0047] Q1: First transistor;

[0048] D1: First diode;

[0049] Q2: Second transistor;

[0050] R2: Second resistor;

[0051] R3: Third resistor;

[0052] 301_1: First control terminal;

[0053] 301_2: Second control terminal;

[0054] 301_3: Third control terminal;

[0055] 301_4: Fourth control terminal;

[0056] 302_1: First-stage delay circuit;

[0057] 302_2: Second-stage delay circuit;

[0058] 302_3: Third-stage delay circuit;

[0059] 302_4: Fourth-stage delay circuit. Detailed Implementation

[0060] The various embodiments of this invention will be described in detail below, with illustrations provided. In addition to these detailed descriptions, this invention can be widely implemented in other embodiments, and any easy substitutions, modifications, or equivalent changes to the described embodiments are included within the scope of this invention, and are subject to the claims. In the description of this specification, many specific details and embodiments are provided to give the reader a more complete understanding of this invention; however, these specific details and embodiments should not be considered as limitations of this invention. Furthermore, well-known steps or elements are not described in the details to avoid creating unnecessary limitations for this invention.

[0061] Please refer to Figure 1 The diagram illustrates a block diagram of a liquid crystal timing control circuit according to the present invention. Figure 1 As shown, a liquid crystal timing control circuit 100 includes: multiple control terminals 101_1...101_n and multi-stage delay circuits 102_1...102_n. Each control terminal 101_i is configured to output a timing control signal ctr_i, and multiple control terminals 101_1...101_n output timing control signals ctr_1...ctr_n. The input terminal 102_in of the next stage delay circuit 102_i+1 of the multi-stage delay circuit is coupled to the output terminal 102_out of the previous stage delay circuit 102_i, and the output terminal 102_out of each stage delay circuit 102_i is coupled to the corresponding control terminal 101_i. The previous stage delay circuit 102_i is configured to output the timing control signal ctr_i it generates as a trigger signal to the next stage delay circuit 102_i+1, so as to sequentially trigger the next stage delay circuit 102_i+1 to generate the corresponding timing control signal ctr_i+1.

[0062] See Figure 2 , Figure 2 A block diagram of a liquid crystal display device is shown. The liquid crystal display device includes a liquid crystal display 400 and a liquid crystal timing control circuit 100. Multiple control terminals 101_1...101_n of the liquid crystal timing control circuit 100 can be coupled to corresponding pins of the liquid crystal display 400.

[0063] In this embodiment, a multi-stage cascaded delay circuit is used. The timing control signal generated by the previous stage delay circuit is output as a trigger signal to the next stage delay circuit, so as to trigger the next stage delay circuit to generate the corresponding timing control signal and output it to the next stage delay circuit in sequence, thereby realizing the sequential control of timing. Finally, each control terminal outputs timing control signals with different timing sequences to the corresponding pins of the liquid crystal display (LCD) in sequence, so as to realize the power-on timing control of the LCD.

[0064] Please refer to Figure 3 , Figure 3 A block diagram of the delay circuit of a liquid crystal timing control circuit according to an embodiment of the present invention is shown. Each stage of the delay circuit 102' includes: a first resistor R1, a first capacitor C1, a first transistor Q1, a first diode D1, and a second transistor Q2. In this embodiment, the first diode D1 is a common forward-conducting diode, such as a common silicon diode. One end of the first resistor R1 is coupled to the input terminal 102_in of this stage, and the other end of the first resistor R1 is coupled to one end of the first capacitor C1 and the anode of the first diode D1. The other end of the first capacitor C1 is grounded to GND. The cathode of the first diode D1 is coupled to the base of the first transistor Q1, the collector of the first transistor Q1 is coupled to the base of the second transistor Q2, the emitter of the second transistor Q2 is coupled to a power supply terminal VDD, and the collector of the second transistor Q2 is coupled to the output terminal 102_out of this stage and the corresponding control terminal 101_i, outputting the corresponding timing control signal ctr_i.

[0065] In this embodiment, the first resistor R1 and the first capacitor C1 form an RC charging network, which, combined with the first diode D1, increases the turn-on threshold voltage of the first transistor Q1, thereby increasing the delay time. After the second transistor Q1 turns on, the second transistor Q2 turns on, outputting a timing control signal. This achieves a controllable delay from the turn-on of the second transistor Q2 to the turn-on of the first transistor, based on the timing control signal received at the input terminal. The delay time T is determined by the parameters of the first resistor R1 and the first capacitor C1, where T≈R1C1. The function of the first diode D1 is to increase the turn-on threshold voltage of the first transistor without increasing the capacitance of the first capacitor C1, thus increasing the delay time. The condition for the first transistor Q1 to turn on is that the charging voltage of the first capacitor C1 is greater than the base-emitter voltage V of the first transistor. BE The voltage drop V of the first diode D1 F The sum of, i.e., V C1 >V BE +V F For a typical silicon diode, the diode voltage drop V0 F Typically, 0.7V is used. Initial stage: The voltage across the first capacitor C1 cannot change abruptly; the initial voltage is 0V. At this time, the base (B) voltage of the first transistor Q1 is determined by the voltage across the first capacitor C1. Since the first capacitor C1 is not charged, the base voltage of the first transistor Q1 is approximately 0V, so the first transistor Q1 is cut off, and the second transistor Q2 is also cut off. Charging stage: The input terminal receives the timing control signal ctr_i from the previous stage and charges the first capacitor C1 through the first resistor R1. The voltage across the first capacitor C1 is V... C1The voltage gradually increases. The first diode D1 increases the conduction voltage threshold of the first transistor Q1, prolonging the charging time to reach the threshold, thus increasing the total delay. At the end of the delay phase: the first capacitor C1 charges to the threshold voltage, i.e., V... C1 >V BE +V F When the collector (C) and emitter (E) of the first transistor Q1 are connected, the base (B) of the second transistor Q1 is connected to the power supply terminal VDD and the collector of the first transistor Q1, causing the base voltage to rise and satisfying the conduction condition of the second transistor Q1. The second transistor Q2 then turns on, and its collector is connected to the control terminal, outputting the corresponding timing control signal ctr_i+1. The delay time of the timing control signal ctr_i+1 relative to the timing control signal ctr_i is approximately R1C1. Thus, through the cascading of multiple delay circuits, timing control signals with different timing sequences are output sequentially, realizing the generation of different timing control signals by the hardware circuit.

[0066] The LCD timing control circuit in this embodiment is based on the RC charging delay characteristic, and uses the diode voltage drop and transistor conduction characteristics to generate multiple sets of timing control signals with different delays for use in LCD timing control. This LCD timing control circuit is simple, stable, and low-cost. Different timing control signals are generated by hardware circuitry, reducing the overhead of the controller's GPIO ports, and timing testing is not required after software updates.

[0067] In one embodiment, further reference is made to Figure 3 As shown, the delay circuit 102' further includes a second resistor R2, one end of which is coupled to the collector of the first transistor Q1, and the other end of which is coupled to the base of the second transistor Q2. The second resistor R2 serves as a pull-up protection resistor, providing a reliable cutoff bias for the second transistor Q2, ensuring that the second transistor Q2 can be stably cut off when the first transistor Q1 is turned off, thus preventing false turn-on.

[0068] In one embodiment, further reference is made to Figure 3 As shown, the delay circuit 102' further includes a third resistor R3, one end of which is coupled to the collector of the first transistor Q1, and the other end of which is coupled to the power supply terminal VDD. The third resistor R3 serves as the base bias resistor for the second transistor Q2. When the first transistor Q1 is turned on, it provides sufficient base current to the second transistor Q2 to ensure reliable conduction of the second transistor Q2; simultaneously, it stabilizes the operating state of the second transistor Q2 during state switching.

[0069] In one embodiment, the first transistor Q1 and the second transistor Q2 are bipolar transistors, and the first...

[0070] The first transistor is a PNP type transistor, and the second transistor is an NPN type transistor.

[0071] Please refer to Figure 4 , Figure 4 A block diagram of the delay circuit of a liquid crystal timing control circuit according to another embodiment of the present invention is shown. Each stage of the delay circuit 102” includes: a first resistor R1, a first capacitor C1, a first transistor Q1, a first diode D1, and a second transistor Q2. In this embodiment, the first diode D1 is a Zener diode. One end of the first resistor R1 is coupled to the input terminal 102_in of this stage, and the other end of the first resistor R1 is coupled to one end of the first capacitor C1 and the cathode of the first diode D1. The other end of the first capacitor C1 is grounded to GND. The anode of the first diode D1 is coupled to the base of the first transistor Q1, the collector of the first transistor Q1 is coupled to the base of the second transistor Q2, the emitter of the second transistor Q2 is coupled to a power supply terminal VDD, and the collector of the second transistor Q2 is coupled to the output terminal 102_out of this stage and the corresponding control terminal 101_i, outputting the corresponding timing control signal ctr_i.

[0072] In this embodiment, the first resistor R1 and the first capacitor C1 form an RC charging network, which, combined with the first diode D1, increases the turn-on threshold voltage of the first transistor Q1, thereby increasing the delay time. After the second transistor Q1 turns on, the second transistor Q2 turns on, outputting a timing control signal. This achieves a controllable delay from the turn-on of the second transistor Q2 to the turn-on of the first transistor, based on the timing control signal received at the input terminal. The delay time T is determined by the parameters of the first resistor R1 and the first capacitor C1, where T≈R1C1. The function of the first diode D1 is to increase the turn-on threshold voltage of the first transistor without increasing the capacitance of the first capacitor C1, thus increasing the delay time. The condition for the first transistor Q1 to turn on is that the charging voltage of the first capacitor C1 is greater than the base-emitter voltage V of the first transistor. BE The sum of the reverse breakdown voltage Vz of the first diode D1, i.e., V C1 >V BE +Vz, for example, Vz voltage can be selected from 2.0V to 3.0V. Initial stage: The voltage across the first capacitor C1 cannot change abruptly, and the initial voltage is 0V. At this time, the base (B) voltage of the first transistor Q1 is determined by the voltage across the first capacitor C1. Since the first capacitor C1 is not charged, the base voltage of the first transistor Q1 is approximately 0V, the first transistor Q1 is cut off, and the second transistor Q2 is cut off. Charging stage: The input terminal receives the timing control signal ctr_i from the previous stage and charges the first capacitor C1 through the first resistor R1. The voltage across the first capacitor C1 V C1The voltage gradually increases. The first diode D1 increases the conduction voltage threshold of the first transistor Q1, prolonging the charging time to reach the threshold, thus increasing the total delay. At the end of the delay phase: the first capacitor C1 charges to the threshold voltage, i.e., V... C1 >V BE When +Vz, the first transistor Q1 is turned on, meaning its collector (C) and emitter (E) are connected. At this time, the base (B) of the second transistor Q1 is connected to the power supply terminal VDD and the collector of the first transistor Q1, increasing the base voltage and satisfying the turn-on condition of the second transistor Q1. The second transistor Q2 then turns on, and its collector is connected to the control terminal, outputting the corresponding timing control signal ctr_i+1. Thus, through the cascading of multiple delay circuits, timing control signals with different timing sequences are output sequentially, realizing the generation of different timing control signals by the hardware circuit. Compared to the attached... Figure 3 The delay circuit design of the embodiment shown uses a Zener diode as the first diode. Compared with a normal forward-conducting diode, the reverse breakdown voltage Vz of the Zener diode is greater than the voltage drop of a normal forward-conducting diode, which further increases the conduction voltage threshold of the first transistor, thereby increasing the delay time.

[0073] The LCD timing control circuit in this embodiment is based on the RC charging delay characteristic. It utilizes the reverse breakdown voltage of the Zener diode and the conduction characteristics of the transistor to generate multiple sets of timing control signals with different delays for use in LCD timing control. This LCD timing control circuit is simple, stable, and low-cost. Different timing control signals are generated by hardware circuitry, reducing the overhead of the controller's GPIO ports. Furthermore, timing testing is not required after software updates.

[0074] refer to Figures 5A to 5C As shown, in the first embodiment, as Figure 5A As shown, the delay duration of each stage of the delay circuit in the liquid crystal timing control circuit 200 is the same, and the same delay circuit is used. Each stage of the delay circuit can use an additional delay circuit. Figure 3 The delay circuit 102' shown has a first diode D1 that is a common forward-conducting diode.

[0075] In the second embodiment, as Figure 5B As shown, the delay duration of each stage of the delay circuit in the liquid crystal timing control circuit 200 is the same, and the same delay circuit is used. Each stage of the delay circuit can use an additional delay circuit. Figure 4 The first diode D1 in the delay circuit 102" shown is a Zener diode.

[0076] In the third embodiment, as Figure 5CAs shown, the liquid crystal timing control circuit 200 has at least one delay circuit with a different delay duration than the other delay circuits. This at least one delay circuit and the other delay circuits employ different delay circuits. The first diode in the delay circuit corresponding to the larger delay duration is a Zener diode, i.e., it uses an auxiliary diode. Figure 4 The delay circuit 102 shown. The first diode of the delay circuit corresponding to the shorter delay duration is a common forward-conducting diode, that is, a diode with an additional... Figure 3 The delay circuit 102' shown is shown.

[0077] like Figure 6A As shown in Figure 6, a specific example of a liquid crystal timing control circuit provided in an embodiment is illustrated. This liquid crystal timing control circuit 300 includes: a first control terminal 301_1, a second control terminal 301_2, a third control terminal 301_3, and a fourth control terminal 301_4; a first-stage delay circuit 302_1, a second-stage delay circuit 302_2, a third-stage delay circuit 302_3, and a fourth-stage delay circuit 302_4. The input terminal 302_in of the first-stage delay circuit 302_1 is coupled to the power supply terminal VDD, and the output terminal 302_out is coupled to the first control terminal 301_1, outputting a first timing control signal, which can be a reset signal RSTB. The input terminal 302_in of the second-stage delay circuit 302_2 is coupled to the output terminal 302_out of the first-stage delay circuit 302_1 and the first control terminal 301_1. The output terminal 302_out of the second-stage delay circuit 302_2 is coupled to the second control terminal 301_2, outputting a second timing control signal, which can be a standby signal STBYB. The input terminal 302_in of the third-stage delay circuit 302_3 is coupled to the output terminal 302_out of the second-stage delay circuit 302_2 and the second control terminal 301_2. The output terminal 302_out of the third-stage delay circuit 302_3 is coupled to the third control terminal 301_3, outputting a third timing control signal, which can be a display on signal DISON. The input terminal 302_in of the fourth-stage delay circuit 302_4 is coupled to the output terminal 302_out of the third-stage delay circuit 302_3 and the third control terminal 301_3. The output terminal 302_out of the fourth-stage delay circuit 302_4 is coupled to the third control terminal 301_4, outputting a fourth timing control signal, which can be the backlight on signal BLON. The first control terminal 301_1, the second control terminal 301_2, the third control terminal 301_3, and the fourth control terminal 301_4 are coupled to the corresponding pins of the liquid crystal display LCD400.

[0078] In this embodiment, the first-stage delay circuit 302_1, the second-stage delay circuit 302_2, the third-stage delay circuit 302_3, and the fourth-stage delay circuit 302_4 all use the same delay circuit, specifically employing the attached... Figure 3 The delay circuit 102' shown, i.e., the first diode D1, is a common forward-conducting diode. The delay durations of the first-stage delay circuit 302_1, the second-stage delay circuit 302_2, the third-stage delay circuit 302_3, and the fourth-stage delay circuit 302_4 are the same. The timing control signals RSTB, STBYB, DISON, and BLON control the timing sequentially. VDD controls the delay of the RSTB signal, the RSTB signal acts as a control signal to control the delay of the STBYB signal, the STBYB signal acts as a control signal to control the delay of the DISON signal, and the DISON signal acts as a timing control signal to control the delay of the BLON signal.

[0079] like Figure 6B As shown, Figure 6BA specific example of a liquid crystal timing control circuit provided in another embodiment is shown. This liquid crystal timing control circuit 300 includes: a first control terminal 301_1, a second control terminal 301_2, a third control terminal 301_3, and a fourth control terminal 301_4; a first-stage delay circuit 302_1, a second-stage delay circuit 302_2, a third-stage delay circuit 302_3, and a fourth-stage delay circuit 302_4. The input terminal 302_in of the first-stage delay circuit 302_1 is coupled to the power supply terminal VDD, and the output terminal 302_out is coupled to the first control terminal 301_1, outputting a first timing control signal, which can be a reset signal RSTB. The input terminal 302_in of the second-stage delay circuit 302_2 is coupled to the output terminal 302_out of the first-stage delay circuit 302_1 and the first control terminal 301_1. The output terminal 302_out of the second-stage delay circuit 302_2 is coupled to the second control terminal 301_2, outputting a second timing control signal, which can be a standby signal STBYB. The input terminal 302_in of the third-stage delay circuit 302_3 is coupled to the output terminal 302_out of the second-stage delay circuit 302_2 and the second control terminal 301_2. The output terminal 302_out of the third-stage delay circuit 302_3 is coupled to the third control terminal 301_3, outputting a third timing control signal, which can be a display on signal DISON. The input terminal 302_in of the fourth-stage delay circuit 302_4 is coupled to the output terminal 302_out of the third-stage delay circuit 302_3 and the third control terminal 301_3. The output terminal 302_out of the fourth-stage delay circuit 302_4 is coupled to the third control terminal 301_4, outputting a fourth timing control signal, which can be the backlight on signal BLON. The first control terminal 301_1, the second control terminal 301_2, the third control terminal 301_3, and the fourth control terminal 301_4 are coupled to the corresponding pins of the liquid crystal display LCD400.

[0080] With the above appendix Figure 6A Unlike the illustrated embodiment, in this embodiment, the first-stage delay circuit 302_1, the second-stage delay circuit 302_2, the third-stage delay circuit 302_3, and the fourth-stage delay circuit 302_4 do not all use the same delay circuit. Specifically, the first-stage delay circuit 302_1, the second-stage delay circuit 302_2, and the third-stage delay circuit 302_3 use the same delay circuit, but the specific implementation is as follows: Figure 3 The delay circuit 102' shown, i.e., the first diode D1, is a common forward-conducting diode. The fourth-stage delay circuit 302_4 uses a different delay circuit structure than the previous three stages, specifically as shown in the attached diagram. Figure 4The delay circuit 102 shown is a Zener diode, where the first diode D1 is a Zener diode. Thus, the delay durations of the first-stage delay circuit 302_1, the second-stage delay circuit 302_2, and the third-stage delay circuit 302_3 are the same, while the delay duration of the fourth-stage delay circuit 302_4 is longer than the previous three. The timing control signals RSTB, STBYB, DISON, and BLON control the timing sequentially. VDD controls the delay of the RSTB signal, the RSTB signal acts as a control signal to control the delay of the STBYB signal, the STBYB signal acts as a control signal to control the delay of the DISON signal, and the DISON signal acts as a timing control signal to control the delay of the BLON signal.

[0081] In summary, the LCD timing control circuit provided by this invention uses a multi-stage cascaded delay circuit. Each stage of the delay circuit is based on the RC charging delay characteristics, combined with the voltage drop of a common forward-conducting diode or the reverse breakdown voltage of a Zener diode, and the conduction characteristics of a transistor to achieve delay duration control. Different timing control signals are output sequentially, realizing the generation of different timing control signals by the hardware circuit for use in LCD timing control. This LCD timing control circuit is simple, stable, and low-cost. Generating different timing control signals by the hardware circuit reduces the overhead of the controller's GPIO ports, and timing retesting is not required after software updates.

[0082] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the scope of the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention is defined by the claims.

Claims

1. A liquid crystal timing control circuit, characterized by comprising: Include: Multiple control terminals, each of which is configured to output a timing control signal; A multi-stage delay circuit, wherein the input terminal of the subsequent stage delay circuit is coupled to the output terminal of the preceding stage delay circuit, and the output terminal of each stage delay circuit is coupled to the corresponding control terminal; the preceding stage delay circuit is configured to output the timing control signal it generates as a trigger signal to the subsequent stage delay circuit, so as to trigger the subsequent stage delay circuit to generate the corresponding timing control signal in sequence. The delay circuit includes: A first resistor, a first capacitor, a first transistor, a first diode, and a second transistor; Wherein, one end of the first resistor is coupled to the input terminal of this stage, the other end of the first resistor is coupled to one end of the first capacitor and one end of the first diode, and the other end of the first capacitor is grounded; The other end of the first diode is coupled to the base of the first transistor, the collector of the first transistor is coupled to the base of the second transistor, the emitter of the second transistor is coupled to a power supply terminal, and the collector of the second transistor is coupled to the output terminal and the corresponding control terminal of this stage, outputting the corresponding timing control signal.

2. The liquid crystal timing control circuit according to claim 1, characterized by The delay circuit further includes: A second resistor, one end of which is coupled to the collector of the first transistor, and the other end of which is coupled to the base of the second transistor.

3. The liquid crystal timing control circuit of claim 1, wherein, The delay circuit further includes: A third resistor, one end of which is coupled to the collector of the first transistor, and the other end of which is coupled to the power supply terminal.

4. The liquid crystal timing control circuit of claim 1, wherein, The first transistor and the second transistor are transistors, and the first transistor is a PNP transistor and the second transistor is an NPN transistor.

5. The liquid crystal timing control circuit of claim 1, wherein, The first diode is a common forward-conducting diode. One end of the first diode is the anode, which is coupled to one end of the first capacitor. The other end of the first diode is the cathode, which is coupled to the base of the first transistor.

6. The liquid crystal timing control circuit of claim 1, wherein, The first diode is a Zener diode, one end of the first diode is the cathode, and the cathode is coupled to one end of the first capacitor; the other end of the first diode is the anode, and the anode is coupled to the base of the first transistor.

7. The liquid crystal timing control circuit according to claim 5 or 6, characterized by The delay time of each stage of the delay circuit is the same, and the same delay circuit is used. The first diode of the delay circuit is a common forward-conducting diode or a Zener diode.

8. The timing control circuit of claim 5 or 6, wherein, There is at least one delay circuit with a different delay duration than the other delay circuits, and the at least one delay circuit and the other delay circuits use different delay circuits; The first diode in the delay circuit corresponding to the longer delay time is a Zener diode, while the first diode in the delay circuit corresponding to the shorter delay time is a common forward-conducting diode.

9. The liquid crystal timing control circuit of claim 7, wherein, The plurality of control terminals include a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal; The multi-stage delay circuit includes a first-stage delay circuit, a second-stage delay circuit, a third-stage delay circuit, and a fourth-stage delay circuit cascaded in sequence. The input terminal of the first-stage delay circuit is coupled to the power supply terminal, and the output terminal is coupled to the first control terminal, outputting a first timing control signal. The output terminal of the second-stage delay circuit is coupled to the second control terminal, outputting a second timing control signal. The output terminal of the third-stage delay circuit is coupled to the third control terminal, outputting a third timing control signal. The output terminal of the fourth-stage delay circuit is coupled to the fourth control terminal, outputting a fourth timing control signal. The first-stage delay circuit, the second-stage delay circuit, the third-stage delay circuit, and the fourth-stage delay circuit all use the same delay circuit, wherein the first diode in the delay circuit is a common forward-conducting diode.

10. The liquid crystal timing control circuit of claim 8, wherein, The plurality of control terminals include a first control terminal, a second control terminal, a third control terminal, and a fourth control terminal; The multi-stage delay circuit includes a first-stage delay circuit, a second-stage delay circuit, a third-stage delay circuit, and a fourth-stage delay circuit cascaded in sequence. The input terminal of the first-stage delay circuit is coupled to the power supply terminal, and the output terminal is coupled to the first control terminal, outputting a first timing control signal. The output terminal of the second-stage delay circuit is coupled to the second control terminal, outputting a second timing control signal. The output terminal of the third-stage delay circuit is coupled to the third control terminal, outputting a third timing control signal. The output terminal of the fourth-stage delay circuit is coupled to the fourth control terminal, outputting a fourth timing control signal. The first-stage delay circuit, the second-stage delay circuit, and the third-stage delay circuit all use the same delay circuit, and the first diode of the delay circuit is a common forward-conducting diode; the first diode of the fourth-stage delay circuit is a Zener diode.

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