A small fusible resistor

Abstract

This invention discloses a miniature fusible resistor, comprising a ceramic substrate, a resistive layer, a protective layer, electrode plates, and a heat dissipation layer. The resistive layer is formed on the upper surface of the ceramic substrate and has a narrow-neck fusing region. The protective layer covers the resistive layer and has stress relief grooves. A pair of electrode plates are respectively disposed at both ends of the ceramic substrate, and a pair of pressing portions are integrally formed on each electrode plate, pressing the pressing portions onto the top sidewalls at both ends of the resistive layer. This invention achieves precise and rapid fusing during overcurrent through the synergistic effect of a three-stage narrow-neck fusing structure and a pre-cracked groove in the substrate; the cross-grid stress relief grooves effectively control debris splashing, improving safety; the electrode connection and buffer layer design ensures mechanical reliability under miniaturization; the overall structure is compact, combining high response speed and stable protection characteristics, making it particularly suitable for the protection needs of high-density electronic circuits.

Description

Technical Field

[0001] This utility model belongs to the field of resistor technology, specifically relating to a small fusible resistor. Background Technology

[0002] Fusible resistors are widely used in power supply circuits, charging equipment, LED drivers and other scenarios. They can automatically melt and break in case of overcurrent to protect subsequent circuits.

[0003] Traditional fusible resistors mostly employ wire-wound or axial lead structures, resulting in large size, slow fusing response, and uncontrollable fusing position, which can easily generate arcs or spatter, affecting circuit board safety. With the miniaturization of electronic products, there is an urgent need for a small, fast, reliable, and easy-to-install surface-mount fusible resistor.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a small fusible resistor that can solve the problems of large size, slow response and uncontrollable melting of existing fusible resistors.

[0006] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows: A miniature fusible resistor includes a ceramic substrate, a resistive layer, a protective layer, electrode plates, and a heat dissipation layer. The resistive layer is formed on the upper surface of the ceramic substrate and has a narrow-neck fusible region. The protective layer covers the resistive layer and has stress relief grooves. A pair of electrode plates are respectively disposed at both ends of the ceramic substrate. A pair of pressing portions are integrally formed on the pair of electrode plates and are respectively pressed onto the top sidewalls at both ends of the resistive layer. The heat dissipation layer covers the exposed sidewalls of the ceramic substrate.

[0007] In one or more embodiments of the present invention, a pre-cracked groove is formed on the upper surface of the ceramic substrate at the bottom of the narrow neck melting zone, and the pre-cracked groove is configured as V-shaped.

[0008] In one or more embodiments of this utility model, the narrow neck fusion region is disposed on the side biased towards the negative electrode, and the narrow neck fusion region is disposed in a three-level gradient from the center side of the resistive layer to the negative electrode side.

[0009] In one or more embodiments of this utility model, the widths of the three-level gradient of the narrow neck fuse zone are set to 60%, 40%, and 30% of the width of the normal resistance layer, respectively, and the length ratio of the three levels is 3:2:1.

[0010] In one or more embodiments of this utility model, the stress relief groove is disposed above the narrow neck fracturing zone, and the stress relief groove is arranged in a cross-grid manner.

[0011] In one or more embodiments of this utility model, a silicon dioxide buffer layer is provided between the resistive layer and the protective layer, and a plurality of crimping grooves are provided on the silicon dioxide buffer layer.

[0012] In one or more embodiments of this utility model, the thickness of the silica buffer layer is set to 0.5-2μm, and the porosity of the crimping groove is 30%-50%.

[0013] In one or more embodiments of this utility model, a pressing groove is provided at the bottom of both ends of the silicon dioxide buffer layer, and the pressing part is embedded in the pressing groove and pressed onto the resistive layer.

[0014] In one or more embodiments of this utility model, the heat dissipation layer is made of aluminum nitride.

[0015] In one or more embodiments of this utility model, a microchannel array is formed within the heat dissipation layer.

[0016] Compared with existing technologies, this utility model achieves precise and rapid melting during overcurrent by synergistic effect of a three-stage narrow-neck fusing structure and a substrate pre-cracked groove; the cross-grid stress relief groove effectively controls debris splashing and improves safety; the electrode connection and buffer layer design ensures mechanical reliability under miniaturization; the overall structure is compact and has both high response speed and stable protection characteristics, making it particularly suitable for the protection needs of high-density electronic circuits. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a small fusible resistor in one embodiment of the present invention; Figure 2 This is an exploded view of a small fusible resistor according to an embodiment of the present invention; Figure 3 This is a cross-sectional view of a small fusible resistor according to an embodiment of the present invention; Figure 4 This utility model Figure 3A schematic diagram at point A in the middle; Figure 5 This is a schematic diagram of the resistive layer of this utility model.

[0019] Explanation of key figure labels: 1-Ceramic substrate, 11-Pre-cracked groove, 2-Resistor layer, 21-Narrow neck fusing zone, 3-Protective layer, 31-Stress relief groove, 4-Silica buffer layer, 41-Crimping groove, 5-Electrode plate, 51-Crimping part, 6-Heat dissipation layer, 61-Microchannel array. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0021] like Figures 1-5 As shown, a miniature fusible resistor in one embodiment of the present invention includes a ceramic substrate 1, a resistive layer 2, a protective layer 3, an electrode plate 5, and a heat dissipation layer 6. The resistive layer 2 is formed on the upper surface of the ceramic substrate 1, and a narrow neck fusible region 21 is provided on the resistive layer 2. The protective layer 3 covers the resistive layer 2 and is provided with a stress relief groove 31. A pair of electrode plates 5 are provided and are respectively provided at both ends of the ceramic substrate 1. A pair of pressing parts 51 are integrally formed on the pair of electrode plates 5, and the pair of pressing parts 51 are respectively pressed onto the top sidewalls at both ends of the resistive layer 2. The heat dissipation layer 6 covers the exposed sidewalls of the ceramic substrate 1.

[0022] The working principle of this miniature fusible resistor is as follows: the resistor is installed in the circuit through a pair of electrode plates 5. When current passes through the resistor, it flows on the resistive layer 2. The heat generated by the resistive layer 2 is transferred to the heat dissipation layer 6, which conducts the heat away to keep the temperature of the resistive layer 2 at a normal level. When the current is overloaded, the temperature of the resistive layer 2 rises sharply. When the temperature at the narrow neck fusible region 21 exceeds the melting point due to the overload, the narrow neck fusible region 21 melts, vaporizes, and breaks, causing the resistive layer 2 to break, thus disconnecting the circuit for overload protection. Because the width of the narrow neck fusible region 21 is narrower than that of the normal resistive layer 2, the current density at the narrow neck fusible region 21 increases inversely proportional to the square, thereby increasing the heat generation per unit volume at the narrow neck fusible region 21 by several times. This results in a millisecond-level response time for the melting of the resistive layer 2 when the circuit is overloaded, greatly improving the reaction rate of the resistor's melting response.

[0023] like Figure 2 As shown, a pre-crack groove 11 is formed on the upper surface of the ceramic substrate 1 at the bottom of the narrow neck melting zone 21. The pre-crack groove 11 is set in V shape. By setting the V-shaped pre-crack groove 11, the fracture path can be precisely controlled when the narrow neck melting zone 21 melts due to circuit overload.

[0024] like Figure 5 As shown, the narrow neck fusion region 21 is located on the side biased towards the negative electrode, and the narrow neck fusion region 21 is arranged in a three-level gradient from the center side of the resistive layer 2 towards the negative electrode side. Since the positive electrode dissipates heat faster than the negative electrode, the difference in electrode thermal conductivity is used to accelerate the melting process.

[0025] like Figure 5 As shown, the widths of the three-stage gradient of the narrow neck fuse zone 21 are set to be 60%, 40%, and 30% of the width of the normal resistance layer 2, respectively, and the length ratio of the three stages is 3:2:1 to enhance the current skin effect.

[0026] like Figure 3 and Figure 4 The stress relief groove 31 is located above the narrow neck melting zone 21. The stress relief groove 31 is arranged in a cross grid pattern. When the narrow neck melting zone 21 melts and breaks, the stress is released through the stress relief groove 31, which effectively controls the flying debris and improves safety.

[0027] like Figures 2-4 As shown, a silicon dioxide buffer layer 4 is provided between the resistive layer 2 and the protective layer 3, and multiple crimping grooves 41 are provided on the silicon dioxide buffer layer 4.

[0028] like Figures 2-4 As shown, the thickness of the silica buffer layer 4 is set to 0.5-2μm, and the porosity of the crimp groove 41 is 30%-50%, so that the silica buffer layer 4 can absorb the impact when the narrow neck fusion zone 21 melts, ensuring the mechanical reliability of the resistor under miniaturization.

[0029] like Figures 2-4 As shown, the bottom of both ends of the silicon dioxide buffer layer 4 is provided with a pressing groove 41, and the pressing part 51 is embedded in the pressing groove 41 and pressed onto the resistor layer 2, so that there is a stable contact between the resistor layer 2 and the electrode plate 5.

[0030] like Figures 1-3 The heat dissipation layer 6 is made of aluminum nitride, which allows the heat dissipation layer 6 to dissipate heat quickly and efficiently while also providing insulation.

[0031] Preferably, a microchannel array 61 is provided in the heat dissipation layer 6 to improve the heat dissipation capacity of the heat dissipation layer 6. In order to further improve the heat dissipation capacity of the heat dissipation layer 6, the microchannel array 61 can be filled with phase change material so as to suppress heat diffusion through the combination of microchannel heat-conducting layer and phase change material and avoid damage to surrounding components.

[0032] In use, the resistor is installed in the circuit through a pair of electrode plates 5. When current passes through the resistor, it flows on the resistive layer 2. The heat generated by the resistive layer 2 is transferred to the heat dissipation layer 6, which conducts the heat away to keep the temperature of the resistive layer 2 normal. When the current is overloaded, the temperature of the resistive layer 2 rises sharply. When the temperature at the narrow neck fuse region 21 exceeds the melting point due to the overload, the narrow neck fuse region 21 melts, vaporizes, and breaks, causing the resistive layer 2 to break, thus disconnecting the circuit for overload protection. Since the width of the narrow neck fuse region 21 is narrower than that of the normal resistive layer 2, the current density at the narrow neck fuse region 21 increases inversely to the square, thereby increasing the heat generated per unit volume at the narrow neck fuse region 21 by several times. This results in a millisecond-level response time for the melting of the resistive layer 2 when the circuit is overloaded, greatly improving the reaction rate of the resistor melting response.

[0033] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0034] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A miniature fusible resistor, characterized in that, include: Ceramic substrate; A resistive layer is formed on the upper surface of a ceramic substrate, and a narrow neck fusion region is provided on the resistive layer; A protective layer covers the resistive layer, and stress relief grooves are provided on the protective layer; The electrode plates are provided in pairs and are respectively disposed at both ends of the ceramic substrate. A pair of pressing parts are integrally formed on the pair of electrode plates, and the pair of pressing parts are respectively pressed onto the top sidewalls at both ends of the resistive layer. A heat dissipation layer is wrapped around the exposed sidewalls of the ceramic substrate.

2. A miniature fusible resistor according to claim 1, characterized in that, The upper surface of the ceramic substrate has a pre-cracked groove at the bottom of the narrow neck melting zone, and the pre-cracked groove is V-shaped.

3. A miniature fusible resistor according to claim 2, characterized in that, The narrow neck fusion zone is located on the side biased towards the negative electrode, and the narrow neck fusion zone is arranged in a three-level gradient from the center side of the resistive layer to the negative electrode side.

4. A miniature fusible resistor according to claim 3, characterized in that, The widths of the three-level gradient of the narrow neck fuse zone are set to 60%, 40%, and 30% of the width of the normal resistance layer, respectively, and the length ratio of the three levels is 3:2:

1.

5. A miniature fusible resistor according to claim 4, characterized in that, The stress relief groove is located above the narrow neck fracturing zone, and the stress relief groove is arranged in a cross grid pattern.

6. A miniature fusible resistor according to claim 1, characterized in that, A silicon dioxide buffer layer is provided between the resistive layer and the protective layer, and a plurality of crimping grooves are provided on the silicon dioxide buffer layer.

7. A miniature fusible resistor according to claim 6, characterized in that, The thickness of the silica buffer layer is set to 0.5-2μm, and the porosity of the crimping groove is 30%-50%.

8. A miniature fusible resistor according to claim 7, characterized in that, The bottom of both ends of the silicon dioxide buffer layer is provided with a pressing groove, and the pressing part is embedded in the pressing groove and pressed onto the resistive layer.

9. A miniature fusible resistor according to claim 1, characterized in that, The heat dissipation layer is made of aluminum nitride.

10. A miniature fusible resistor according to claim 9, characterized in that, The heat dissipation layer contains a microchannel array.

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