Primary-side control device and flyback power charging system

Abstract

This application provides a primary-side control device and a flyback power supply charging system. The primary-side control device includes a detection unit and a forced control module, wherein: the detection unit is used to detect the startup state of the flyback power supply charging system, wherein the startup state includes startup incomplete or startup completed; the forced control module is used to forcibly control the flyback power supply charging system to operate in DCM mode when the startup state detected by the detection unit is startup incomplete, thereby enabling the primary-side current Ipri to increase from zero, correspondingly reducing the primary and secondary-side shoot-through current, resulting in lower VDS voltage stress on the secondary-side power transistor M1, thus solving the problems in the prior art.

Description

Technical Field

[0001] This application relates to the field of power supply technology, specifically to primary-side control devices and flyback power charging systems. Background Technology

[0002] In the field of power supply technology, flyback switching power supplies are widely used in various chargers and adapters due to their advantages such as simple structure and low cost. With the continuous upgrading of international energy efficiency standards, the requirements for power conversion efficiency are becoming increasingly stringent. On the secondary side of flyback switching power supplies, using secondary-side synchronous rectification control to replace traditional diode rectification has become a key means to improve efficiency, and even a mandatory solution to meet standards.

[0003] like Figure 1 The diagram shows the current structure of a flyback power supply charging system, which includes a primary-side controller 1 and a secondary-side controller 2. The primary-side controller 1 includes a clock generation module 11, a demagnetization and valley detection module 12, a control module 13, and a drive circuit 14. The clock generation module 11 outputs a system clock clk at a preset frequency, providing a time reference for the entire flyback power supply charging system. The demagnetization and valley detection module 12 detects relevant information through corresponding pins, thereby generating a demagnetization completion signal (demag) and a valley indication signal (valley). The control module 13 performs logical operations based on information input from multiple pins, generating a primary-side switch control signal ON. The drive circuit 14 amplifies the primary-side switch control signal ON and outputs a GATE signal to control the on / off state of the power device M0.

[0004] In current flyback power supply charging systems, the switching control typically begins with a unified system clock clk. Specifically, within each PWM cycle, the system clock clk output by the clock generation module 11 is processed by the strong control module 13 to generate a primary-side switching control signal ON, thereby turning on the primary-side power transistor M0. At this time, the primary-side current Ipri increases linearly. Subsequently, the secondary-side controller 2 turns on the secondary-side synchronous rectifier MOSFET (i.e., the secondary-side power transistor M1) to charge the output capacitor, and the secondary-side current Isec decreases linearly.

[0005] At this point, if the secondary current Isec decays to zero before the system clock clk arrives in the next cycle, the flyback power supply charging system operates in DCM (Discontinuous Conduction Mode). Figure 2 The diagram shown is a key waveform illustration of a current flyback power supply charging system in DCM mode. Figure 2As can be seen from this, after the system clock clk arrives in the next cycle, the control primary current Ipri increases from zero. There is no primary-secondary shoot-through current, which makes the drain-source voltage (VDS) stress of the secondary power transistor M1 low.

[0006] Conversely, if the secondary current Isec fails to decay to zero before the system clock clk arrives in the next cycle, the flyback power supply charging system will operate in CCM (Continuous Conduction Mode), such as... Figure 3 The diagram shown is a key waveform illustration of the current flyback power supply charging system in CCM mode. Figure 3 As can be seen from the data, after the system clock clk arrives in the next cycle, the primary current Ipri will increase from an initial current greater than 0. Therefore, there is a primary-secondary shoot-through current, which will significantly increase the Vds voltage stress of the secondary power transistor M1. The deeper the CCM, the greater the Vds voltage stress of the secondary power transistor M1.

[0007] The current flyback power charging system, whose switching cycle is basically determined by a unified system clock clk, is prone to adverse conditions during the startup phase. For example, when the output voltage Vout is at a low level during startup and gradually builds up, the decay rate of the secondary current Isec slows down significantly. Therefore, before the next system clock clk arrives, the secondary current Isec often cannot decay to zero, causing the system to easily enter CCM mode. In CCM mode, when the primary power transistor M0 is turned on, a large primary-secondary shoot-through current is generated. This primary-secondary shoot-through current directly acts on the secondary power transistor M1, causing a huge VDS voltage stress on it, which can easily lead to the breakdown and damage of the secondary power transistor M1. Utility Model Content

[0008] The main objective of this invention is to provide a primary-side control device and a flyback power charging system to solve the technical problems in the prior art.

[0009] To achieve the above objectives, the technical solution provided by this utility model is to provide a primary-side control device, comprising: a detection unit and a control module, wherein: The detection unit is used to detect the startup status of the flyback power charging system, wherein the startup status includes startup incomplete or startup completed. The forced control module is used to force the flyback power charging system to operate in DCM mode when the start-up status detected by the detection unit is that the start-up is not completed; and to cancel the forced control of the flyback power charging system to operate in DCM mode when the start-up status detected by the detection unit is that the start-up is completed.

[0010] As a preferred technical solution, the detection unit is further configured to output a corresponding startup status indication signal based on the detected startup status of the flyback power charging system, wherein the startup status indication signal includes a low-level signal and a high-level signal, which are used to indicate that the startup is not completed and the startup is completed, respectively.

[0011] As a preferred technical solution, the forced control module is used to force the flyback power charging system to operate in DCM mode when the start-up status indication signal is a low-level signal.

[0012] As a preferred technical solution, the forced control module is also used to cancel the forced control of the flyback power charging system to work in DCM mode when the detection unit detects that the startup state is completed.

[0013] As a preferred technical solution, the detection unit includes a comparator, an SR latch, and a delay circuit, wherein: The positive input terminal of the comparator is connected to a reference voltage; The negative input terminal of the comparator is connected to the COMP pin voltage of the primary-side control device; The S-input terminal of the SR latch is connected to the output terminal of the comparator; The R input terminal of the SR latch is connected to the system reset signal terminal, wherein the system reset signal terminal is used to output a low-level reset signal; The input terminal of the delay circuit is connected to the Q output terminal of the SR latch; The output of the delay circuit is connected to the control module.

[0014] As a preferred technical solution, the delay circuit includes multiple D flip-flops connected in series, wherein: The reset terminals of each D flip-flop are connected to the Q output terminal of the SR latch; The clock input of the first D flip-flop in series is connected to the clock generation module in the primary-side control device, and the clock inputs of each of the other D flip-flops are connected to the D output of the preceding D flip-flop. Output terminal; The D output of the last D flip-flop in series and The output terminal is connected to the control module.

[0015] As a preferred technical solution, the detection unit includes a sample-and-hold circuit, a second comparator, a second SR latch, and a second delay circuit, wherein: The sample-and-hold circuit is used to sample and hold the input voltage of the DEM pin of the primary-side control device and output the sampled voltage signal. The positive input terminal of the second comparator is connected to the output terminal of the sample-and-hold circuit; The negative input terminal of the second comparator is connected to a reference voltage; The S-input terminal of the second SR latch is connected to the output terminal of the second comparator; The R input terminal of the second SR latch is connected to the system reset signal terminal, wherein the system reset signal terminal is used to output a low-level reset signal; The input terminal of the second delay circuit is connected to the Q output terminal of the second SR latch; The output of the second delay circuit is connected to the control module.

[0016] As a preferred technical solution, the second delay circuit includes an inverter, a reference current output terminal, a PMOS transistor, an NMOS transistor, a capacitor, and a buffer, wherein: The input terminal of the inverter is connected to the Q output terminal of the second SR latch; The output terminal of the inverter is connected to the gate of the PMOS transistor and the gate of the NMOS transistor; The drain of the NMOS transistor is grounded; The source of the PMOS transistor is connected to the reference current output terminal; The source of the NMOS transistor is connected in series with the drain of the PMOS transistor, and is connected to one end of the capacitor and the input terminal of the buffer. The other end of the capacitor is grounded. The output of the buffer is connected to the control module.

[0017] As a preferred technical solution, during the startup process of the flyback power supply charging system, the sampling voltage signal output by the sample-and-hold circuit gradually increases with the output voltage Vout and the voltage of the DEM pin. After startup is completed, when the sampling voltage signal rises above the reference voltage, the second comparator outputs a pre-completion signal; the second SR latch outputs the pre-completion signal to the second delay circuit module, and after a delay, a startup completion indication signal is generated.

[0018] This application also provides a flyback power charging system, which includes the primary-side control device provided in this application and a secondary-side control device matched with the primary-side control device.

[0019] The primary-side control device provided in this application includes a detection unit and a forced control module. The detection unit is used to detect the startup state of the flyback power charging system, which includes startup incomplete or startup completed. The forced control module is used to forcibly control the flyback power charging system to operate in DCM mode when the startup state detected by the detection unit is startup incomplete. This allows the primary-side current Ipri to increase from zero, thereby reducing the primary and secondary-side direct current and lowering the VDS voltage stress of the secondary-side power transistor M1. This solves the problems in the prior art. Attached Figure Description

[0020] To further reveal the specific technical content of this case, please first refer to the accompanying drawings, in which: Figure 1 A schematic diagram of the specific structure of a flyback power charging system in the prior art; Figure 2 A schematic diagram of key waveforms for a flyback power supply charging system in DCM mode; Figure 3 A schematic diagram of key waveforms for a flyback power supply charging system in CCM mode; Figure 4 A schematic diagram of the specific structure of the flyback power supply charging system provided in the embodiments of this application; Figure 5 A schematic diagram of the specific structure of the detection unit in the primary-side control device provided in the embodiments of this application; Figure 6 A schematic diagram of the specific structure of the delay circuit module in the detection unit of the primary-side control device provided in the embodiments of this application; Figure 7 A schematic diagram of key waveforms of the primary-side control device during the startup process, provided for embodiments of this application; Figure 8 A schematic diagram of the specific structure of the detection unit in the primary-side control device provided in another embodiment of this application; Figure 9 A schematic diagram of the specific structure of the delay circuit module in the detection unit of the primary-side control device provided in another embodiment of this application; Figure 10 This is a schematic diagram of key waveforms of the primary-side control device during the startup process, provided for another embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. In the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance or order.

[0022] As mentioned earlier, current flyback power charging systems are basically determined by a unified system clock clk during their switching cycle. This makes the flyback power charging system prone to adverse conditions during the startup phase. For example, when the output voltage Vout is at a low level during startup and is gradually building up, the decay rate of the secondary current Isec will be significantly slower. Therefore, before the next system clock clk arrives, the secondary current Isec often cannot decay to zero, causing the system to easily enter CCM mode. In CCM mode, when the primary power transistor M0 is turned on, a large primary-secondary shoot-through current will be generated. This primary-secondary shoot-through current will directly act on the secondary power transistor M1, causing a huge VDS voltage stress on it, which can easily lead to the breakdown and damage of the secondary power transistor M1.

[0023] In view of this, embodiments of this application provide a primary-side control device and a flyback power charging system, which can be used to solve the problems in the prior art.

[0024] To facilitate understanding, a simple analysis of the technical solution provided in this application's embodiments can be performed first. As shown above, in the prior art, the switching cycle of the flyback power charging system is basically determined by a unified system clock clk. This causes the secondary current Isec to often fail to decay to zero during the startup process, when the output voltage Vout is at a low level and gradually building up. Consequently, it is easy to enter CCM mode, ultimately resulting in a huge VDS voltage stress on the secondary power transistor M1 during startup. In response to this situation, this application adds a detection unit to the primary-side control device to detect the startup status of the flyback power charging system. Correspondingly, if the startup status is incomplete, it indicates that the output voltage Vout is at a low level and gradually building up. Therefore, through the strong control module, the flyback power charging system is forced to operate in DCM mode, thereby controlling the primary-side current Ipri to increase from zero. Consequently, there is no primary-secondary shoot-through current, resulting in a lower VDS voltage stress on the secondary power transistor M1. Therefore, this application solves the problem that the secondary power transistor M1 is prone to breakdown and damage during the startup process of the existing flyback power charging system by setting a detection unit in the primary-side control device to detect the startup status of the flyback power charging system and optimizing the control method of the forced control module accordingly. This adds a control means to force the flyback power charging system to work in DCM mode.

[0025] like Figure 4The diagram shows a specific structural schematic of the flyback power charging system provided in this embodiment. The flyback power charging system includes a primary-side control device 3 and a matching secondary-side control device 4. The structure of the secondary-side control device 4 can be substantially the same as that of secondary-side control devices in existing flyback power charging systems. For example, the secondary-side control device 4 may include a secondary-side power transistor M1, a secondary-side control module, a capacitor Cout, and a secondary-side coil Ns.

[0026] Here, we can focus on describing the structure of the primary-side control device 3 in the flyback power charging system provided in this application embodiment. In addition to the clock generation module 31, demagnetization and valley detection module 32, strong control module 33, and drive circuit 34 included in prior art primary-side control devices, the primary-side control device 3 also includes a detection unit 35. Of course, in practical applications, besides the detection unit 35, the primary-side control device 3 may also include other devices such as the main-side coil Np, power device M0, and Na coil, which will not be described in detail here.

[0027] The clock generation module 31, the demagnetization and valley detection module 32, and the drive circuit 34 can function in the same way (or essentially the same way) as the corresponding modules in the primary-side control device in the prior art. For example, the clock generation module 31 can output a system clock clk with a preset frequency to provide a time reference for the operation of the entire flyback power charging system. The demagnetization and valley detection module 32 detects relevant information through corresponding pins and then generates a demagnetization completion signal demag and a valley indication signal valley. The drive circuit 34 amplifies the primary-side switch control signal ON output by the drive circuit 34 and outputs a GATE signal to control the on / off state of the power device M0.

[0028] The key point is that the detection unit 35 provided in this application embodiment can be used to detect the start-up state of the flyback power charging system. The start-up state includes start-up incomplete or start-up completed. If the start-up state of the flyback power charging system is start-up incomplete, it means that the flyback power charging system is still in the process of starting up and has not completed the start-up. Therefore, the output voltage Vout of the secondary control device 4 is at a low level and is gradually being built up. If the start-up state of the flyback power charging system is start-up completed, it means that the flyback power charging system has completed the start-up and can then work normally.

[0029] The output of the detection unit 35 is connected to the control module 33, enabling the control module 33 to determine the startup state of the flyback power charging system detected by the detection unit 35. Thus, when the startup state detected by the detection unit is incomplete, the control module 33 can force the flyback power charging system to operate in DCM mode, thereby enabling the primary current Ipri to increase from zero, and correspondingly reducing the primary and secondary currents (in practical applications, it can be reduced to almost zero), resulting in lower VDS voltage stress on the secondary power transistor M1, thus solving the problems in the prior art.

[0030] In practical applications, the detection unit 33 can also output a corresponding start-up status indication signal (STend) based on the detected start-up status of the flyback power charging system. The start-up status indication signal STend includes a low-level signal and a high-level signal, which are used to indicate that the start-up is not completed and the start-up is completed, respectively. For example, if the detection unit 33 detects that the start-up status of the flyback power charging system is not completed, it outputs the corresponding start-up status indication signal STend, which is a low-level signal. Conversely, if the detection unit 33 detects that the start-up status of the flyback power charging system is completed, it outputs the corresponding start-up status indication signal STend, which is a high-level signal. In this way, the forced control module 33 can directly detect whether the start-up status indication signal STend is a low-level signal or a high-level signal, thereby determining the start-up status of the flyback power charging system. And when the start-up status indication signal STend is a low-level signal, it forces the flyback power charging system to work in DCM mode.

[0031] Of course, in practical applications, the start-up status indication signal STend output by the detection unit 33 can also be a digital signal. For example, if the detection unit 33 detects that the start-up status of the flyback power charging system is not completed, it outputs 0; if the detection unit 33 detects that the start-up status of the flyback power charging system is completed, it outputs 1.

[0032] The specific structure of the detection unit 35 provided in this application embodiment can be implemented in various ways in practical applications. Several of these methods are listed here for illustration. Figure 5 The diagram shown illustrates the specific structure of the detection unit 35 in the first implementation. The detection unit 35 includes a comparator ( Figure 5 COMP0), SR latch ( Figure 5 SR0 in the middle) and delay circuit ( Figure 5 (351 in the middle).

[0033] Regarding the connection method of these modules, the positive input terminal of the comparator COMP0 is connected to the reference voltage VREFst, and the negative input terminal of the comparator COMP0 is connected to the COMP voltage pin of the primary-side control device; the S input terminal of the SR latch SR0 is connected to the output terminal of the comparator COMP0, and the R input terminal of the SR latch SR0 is connected to the system reset signal terminal, which is used to output a low-level reset signal; the input terminal of the delay circuit 351 is connected to the Q output terminal of the SR latch SR0, and the output terminal of the delay circuit 351 is connected to the strong control module 33.

[0034] Based on the detection unit 35, comparator COMP0 compares the voltage at the COMP voltage pin (referred to as the COMP voltage) with the reference voltage VREFst, and outputs a pre-completion signal COMPlow from its output terminal according to the comparison result. During the startup process of the flyback power charging system (i.e., before startup and completion), the COMP voltage remains high, and since the COMP voltage is greater than the reference voltage VREFst, the pre-completion signal COMPlow output by comparator COMP0 is low. After the flyback power charging system has completed startup, the COMP voltage in the primary-side control device is gradually pulled down. When it drops below the reference voltage VREFst, the pre-completion signal COMPlow output by comparator COMP0 becomes high.

[0035] The S input of the SR latch SR0 is connected to the output of the comparator COMP0, and the R input of the SR latch SR0 is connected to the system reset signal terminal. During the startup of the flyback power charging system, the system reset signal terminal will output a low-level reset signal reset, resetting the initial indication signal STend0 output by the SR latch SR0 to a low level. After the flyback power charging system has finished starting, since the pre-completion signal COMPlow output by the comparator COMP0 is high, the initial indication signal STend0 can be set to a high level through the logic processing of the SR latch SR0 itself and output to the delay circuit module 351. At this time, the delay circuit module 351 generates the final startup completion indication signal STend after a delay period of time. The reason for adding the delay circuit module 351 to the detection unit 35 is to switch when it is closer to the steady-state operating state.

[0036] Regarding the specific structure of the delay circuit module 351, for example, the delay circuit module 351 may include multiple series-connected D flip-flops. The reset terminal R of each D flip-flop is connected to the Q output terminal of the SR latch SR0, thereby receiving the signal output by the Q output terminal of the SR latch SR0. The clock input terminal of the first series-connected D flip-flop is connected to the clock generation module 31 in the primary-side control device 3, thereby receiving the system clock clk sent by the clock generation module 31. Furthermore, the clock input terminals of the other D flip-flops are connected to the D output terminal of the preceding D flip-flop and... Output terminal; the D output terminal of the last D flip-flop in series and The output end is connected to the control module 33.

[0037] For example, Figure 6 The diagram shown is a structural schematic of the delay circuit module 351. Figure 6 The delay circuit module 351 shown includes eight D flip-flops connected in series, namely DEF0, DEF1, DEF2...DEF7. These eight D flip-flops are connected in series to form the delay circuit module 351. The clock input terminal of the first D flip-flop (DEF0) is connected to the clock generation module 31 in the primary-side control device 3. The clock input terminal of DEF1 is connected to the D output terminal of DEF0. At the output terminal, the clock input terminal of DEF2 is connected to the D output terminal of DEF1 and... The output terminals follow the same logic: the clock input of DEF7 is connected to the D output of DEF6 and... Output terminal. And the D output terminal of this DEF7 and... The output end is connected to the control module 33.

[0038] like Figure 7 The diagram shows key waveforms of the primary-side control device 3 during startup in this first implementation. Before the startup completion indicator signal STend output by the detection unit 35 goes high, the forced control module 33 forces the flyback power charging system to operate in DCM mode. At this time, each new switching cycle needs to wait for the valley indicator signal (valley) generated after the secondary current decays to zero to start, thus ensuring relatively low VDS voltage stress on the secondary power transistor throughout the startup process of the flyback power charging system. The COMP voltage of the primary-side control device 3 remains high during startup. As the startup process nears its end, the COMP voltage is gradually pulled down by the system until it falls below the reference voltage VREFst. After a delay, the startup completion indicator signal STend goes high, and the system then switches to normal control mode.

[0039] Therefore, the forced control module 33 is also used to cancel the forced control of the flyback power charging system to work in DCM mode when the detection unit detects that the startup state is completed. At this time, the flyback power charging system can work in both DCM mode and CCM mode since it has completed the startup.

[0040] Regarding the specific structure of the detection unit 35 provided in the embodiments of this application, as follows: Figure 8 The structure shown is that of the second implementation method. In this case, the detection unit 35 includes a sample and hold circuit 352, a second comparator COMP1, a second SR latch SP1, and a second delay circuit 353.

[0041] The sample-and-hold circuit 352 is used to sample and hold the input voltage of the DEM pin of the primary-side control device 3 and output the sampled voltage signal DEMsmpl. The positive input of the second comparator COMP1 is connected to the output of the sample-and-hold circuit 352. The negative input of the second comparator COMP1 is connected to the reference voltage VREFst. The S input of the second SR latch SR1 is connected to the output of the second comparator COMP1. The R input of the second SR latch SR1 is connected to the system reset signal. The input of the second delay circuit 353 is connected to the Q output of the second SR latch SR1. The output of the second delay circuit 353 is connected to the strong control module 33.

[0042] In this second implementation, the detection unit 35 and the sample-and-hold circuit 352 can input a sampled voltage signal DEMsmpl to the positive input terminal of the second comparator COMP1, so that the second comparator COMP1 compares the sampled voltage signal DEMsmpl with the reference voltage VREFst input at the negative input terminal, and then outputs a pre-completion signal DEMhigh from the output terminal according to the comparison result.

[0043] During the startup process of the flyback power supply charging system, the sampling voltage signal DEMsmpl output by the sample-and-hold circuit 352 gradually increases with the output voltage Vout and the voltage of the DEM pin. After startup is complete, when the sampling voltage signal DEMsmpl rises above the reference voltage VREFst (i.e., greater than the reference voltage VREFst), the pre-completion signal DEMhigh of the second comparator COMP1 becomes high. Correspondingly, since the S input of the second SR latch SR1 is connected to the output of the second comparator COMP1, the S input of the second SR latch SR1 can receive the high-level pre-completion signal DEMhigh. The R input of the second SR latch SR1 is connected to the system reset signal, so it will be reset to a low level during startup. Thus, after startup is complete, through the logic processing of the second SR latch SR1, the high-level pre-completion signal DEMhigh is output to the second delay circuit module 353, and after a delay, the final startup completion indication signal STend is generated.

[0044] like Figure 9 The diagram shown illustrates the specific structure of the second delay circuit 353. The structure of the second delay circuit 353 may include an inverter INV0, a ​​reference current output terminal IB, and a PMOS transistor (…). Figure 9 MP0 and NMOS transistors (in the middle) Figure 9 The following components are included: MN0, capacitor C0, and buffer BUF0. The input of inverter INV0 is connected to the Q output of the second SR latch SR1; the output of inverter INV0 is connected to the gates of the PMOS and NMOS transistors; the drain of the NMOS transistor is grounded; the source of the PMOS transistor is connected to the reference current output IB; the source of the NMOS transistor and the drain of the PMOS transistor are connected in series and connected to one end of capacitor C0 and the input of buffer BUF0; the other end of capacitor C0 is grounded; and the output of buffer BUF0 is connected to the strong control module 33.

[0045] During the startup process of the flyback power supply charging system, the STend0 output from the Q output of the second SR latch SR1 is low, while the pre-completion signal N0 generated by the inverter INV0 is high. The PMOS transistor is turned off while the NMOS transistor is turned on, thus discharging the upper plate voltage N1 of capacitor C0 to ground, thereby keeping the STend signal output through buffer BUF0 low. After startup is complete, the STend0 signal becomes high, the inverter output N0 becomes low, the NMOS transistor turns off while the PMOS transistor turns on, and capacitor C0 is charged through the reference current IB. The upper plate voltage N1 gradually increases, and when it reaches the flip-flop threshold voltage of buffer BUF0, the output STend signal becomes high. Figure 9In the second delay circuit 353 shown, the specific delay time can be set by adjusting the reference current IB and the capacitor C0. After the timing is completed, the startup completion indicator signal STend is set to a high level, indicating that the system startup has been completed and can be switched to normal working mode.

[0046] like Figure 10 The diagram shows key waveforms of the primary-side control device 3 during the startup process in this second implementation. Before the startup completion indicator signal STend output by the detection unit 35 goes high, the forced control module 33 forces the flyback power charging system to operate in DCM mode. At this time, each new switching cycle needs to wait for the valley indicator signal generated after the secondary current decays to zero to start, so the voltage stress of the secondary power transistor VDS is very low throughout the startup process. During startup, the sampling voltage signal DEMsmpl gradually increases with the output voltage Vout and the DEM pin voltage. After startup is complete, the sampling voltage signal DEMsmpl rises above the reference voltage VREFst and after a delay, the startup completion indicator signal STend goes high, after which the system switches to normal control mode.

[0047] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A primary-side control device, characterized by comprising: include: The detection unit and the control module include: The detection unit is used to detect the startup status of the flyback power charging system, wherein the startup status includes startup incomplete or startup completed. The forced control module is used to force the flyback power charging system to operate in DCM mode when the start-up status detected by the detection unit is that the start-up is not completed; and to cancel the forced control of the flyback power charging system to operate in DCM mode when the start-up status detected by the detection unit is that the start-up is completed.

2. The primary-side control device according to claim 1, wherein The detection unit is further configured to output a corresponding startup status indication signal based on the detected startup status of the flyback power charging system, wherein the startup status indication signal includes a low-level signal and a high-level signal, which are used to indicate that the startup is not completed and the startup is completed, respectively.

3. The primary-side control device according to claim 2, wherein The forced control module is used to force the flyback power charging system to operate in DCM mode when the start-up status indication signal is a low-level signal.

4. The primary-side control device according to claim 1, wherein The forced control module is also used to cancel the forced control of the flyback power charging system to operate in DCM mode when the detection unit detects that the startup state is completed.

5. The primary-side control device according to claim 1, wherein The detection unit includes a comparator, an SR latch, and a delay circuit, wherein: The positive input terminal of the comparator is connected to a reference voltage; The negative input terminal of the comparator is connected to the COMP pin voltage of the primary-side control device; The S-input terminal of the SR latch is connected to the output terminal of the comparator; The R input terminal of the SR latch is connected to the system reset signal terminal, wherein the system reset signal terminal is used to output a low-level reset signal; The input terminal of the delay circuit is connected to the Q output terminal of the SR latch; The output of the delay circuit is connected to the control module.

6. The primary-side control device according to claim 5, wherein The delay circuit includes multiple D flip-flops connected in series, wherein: The reset terminals of each D flip-flop are connected to the Q output terminal of the SR latch; The clock input end of the first D flip-flop in series is connected with the clock generation module in the primary side control device, and the clock input end of each of the other D flip-flops is connected with the D output end of the previous D flip-flop and an output end; the D output terminal of the last D flip-flop in series and an output terminal connected to the strong control module.

7. The primary-side control device according to claim 1, wherein The detection unit includes a sample-and-hold circuit, a second comparator, a second SR latch, and a second delay circuit, wherein: The sample-and-hold circuit is used to sample and hold the input voltage of the DEM pin of the primary-side control device and output the sampled voltage signal. The positive input terminal of the second comparator is connected to the output terminal of the sample-and-hold circuit; The negative input terminal of the second comparator is connected to a reference voltage; The S-input terminal of the second SR latch is connected to the output terminal of the second comparator; The R input terminal of the second SR latch is connected to the system reset signal terminal, wherein the system reset signal terminal is used to output a low-level reset signal; The input terminal of the second delay circuit is connected to the Q output terminal of the second SR latch; The output of the second delay circuit is connected to the control module.

8. The primary side control device according to claim 7, wherein The second delay circuit includes an inverter, a reference current output terminal, a PMOS transistor, an NMOS transistor, a capacitor, and a buffer, wherein: The input terminal of the inverter is connected to the Q output terminal of the second SR latch; The output terminal of the inverter is connected to the gate of the PMOS transistor and the gate of the NMOS transistor; The drain of the NMOS transistor is grounded; The source of the PMOS transistor is connected to the reference current output terminal; The source of the NMOS transistor is connected in series with the drain of the PMOS transistor, and is connected to one end of the capacitor and the input terminal of the buffer. The other end of the capacitor is grounded. The output of the buffer is connected to the control module.

9. The primary-side control device according to claim 7, wherein During the startup process of the flyback power supply charging system, the sampling voltage signal output by the sample-and-hold circuit gradually increases with the output voltage Vout and the voltage of the DEM pin. After startup is complete, when the sampling voltage signal rises above the reference voltage, the second comparator outputs a pre-completion signal; the second SR latch outputs the pre-completion signal to the second delay circuit module, and after a delay, a startup completion indication signal is generated.

10. A flyback power supply charging system, characterized in that, The flyback power supply charging system includes a primary-side control device as described in any one of claims 1 to 9, and a secondary-side control device matched with the primary-side control device.

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