An input buffer circuit and a logic circuit

Abstract

This application provides an input buffer circuit and a logic circuit. The input buffer circuit includes a first inverter, a second inverter, and a voltage compensation circuit. The input terminal of the first inverter receives the input voltage. The output terminal of the first inverter is connected to the input terminal of the voltage compensation circuit. The output terminal of the voltage compensation circuit is connected to the input terminal of the second inverter. The output terminal of the voltage compensation circuit is also connected to its input terminal. The output terminal of the second inverter is connected to the power supply terminal of the logic function circuit in the logic circuit to supply power to the logic function circuit. By inverting the input voltage twice through the first and second inverters, noise and interference of the input voltage can be removed, ensuring the accuracy of the output voltage. In addition, the voltage compensation circuit compensates for the output voltage of the first inverter, preventing the logic function received by the logic function circuit from being disordered due to the instability of the first inverter's output voltage.

Description

Technical Field

[0001] This utility model relates to the field of logic circuit technology, and more specifically, to an input buffer circuit and a logic circuit. Background Technology

[0002] Currently, most metal-oxide-semiconductor (CMOS) logic circuit input structures use inverters composed of MOSFETs with their gates and drains shorted, in order to solve the problems of low noise margin and asymmetrical and non-steep output waveforms caused by the series-parallel relationship of MOSFETs when other logic gates are directly used as input terminals.

[0003] However, with the diversification of logic circuit applications, when the input circuit signal of a logic circuit is affected by noise and interference, causing the input voltage to be between the low and high level threshold voltages, both MOSFETs of the inverter may be partially turned on, resulting in an increase in power supply current, unstable output voltage at the output terminal, and consequently, disorder of the logic function received by the back-end circuit, making the circuit unable to work properly. Utility Model Content

[0004] The purpose of this invention is to address the shortcomings of the prior art by providing an input buffer circuit and a logic circuit, so as to output an accurate voltage through the first inverter, the second inverter and the voltage compensation circuit, thereby avoiding the malfunction of the logic function received by the logic function circuit.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide an input buffer circuit, the input buffer circuit comprising: a first inverter, a second inverter, and a voltage compensation circuit;

[0007] The input terminal of the first inverter is used to receive the input voltage. The output terminal of the first inverter is connected to the input terminal of the voltage compensation circuit. The output terminal of the voltage compensation circuit is connected to the input terminal of the second inverter. The output terminal of the voltage compensation circuit is also connected to the input terminal of the voltage compensation circuit. The output terminal of the second inverter is used to connect to the power supply terminal of the logic function circuit in the logic circuit to supply power to the logic function circuit.

[0008] In an optional implementation, the voltage compensation circuit includes: a third inverter and a pull-up unit;

[0009] The input terminal of the third inverter serves as the input terminal of the voltage compensation circuit and is connected to the output terminal of the first inverter; the output terminal of the third inverter is connected to the control terminal of the pull-up unit, the first terminal of the pull-up unit is used to connect to a preset power supply, and the second terminal of the pull-up unit serves as the output terminal of the voltage compensation circuit.

[0010] In an optional embodiment, the pull-up unit is a first P-type field-effect transistor, the control terminal of the pull-up unit is the gate of the first P-type field-effect transistor, the first terminal of the pull-up unit is the source of the first P-type field-effect transistor, and the second terminal of the pull-up unit is the drain of the first P-type field-effect transistor.

[0011] In an optional implementation, the third inverter includes a second P-type field-effect transistor and a first N-type field-effect transistor;

[0012] The connection point between the input terminal of the second P-type field-effect transistor and the input terminal of the first N-type field-effect transistor serves as the input terminal of the third inverter and is connected to the output terminal of the first inverter; the connection point between the output terminal of the second P-type field-effect transistor and the output terminal of the first N-type field-effect transistor serves as the output terminal of the third inverter and is connected to the control terminal of the pull-up unit.

[0013] In an optional embodiment, the input terminal of the second P-type field-effect transistor is the gate of the second P-type field-effect transistor, and the input terminal of the first N-type field-effect transistor is the gate of the first N-type field-effect transistor; the output terminal of the second P-type field-effect transistor is the drain of the second P-type field-effect transistor, and the output terminal of the first N-type field-effect transistor is the drain of the first N-type field-effect transistor; the source of the second P-type field-effect transistor is connected to the preset power supply, and the source of the first N-type field-effect transistor is grounded.

[0014] In an optional implementation, the first inverter includes: a third P-type field-effect transistor and a second N-type field-effect transistor;

[0015] The connection point between the input terminal of the third P-type field-effect transistor and the input terminal of the second N-type field-effect transistor serves as the input terminal of the first inverter, used to receive the input voltage; the connection point between the output terminal of the third P-type field-effect transistor and the output terminal of the second N-type field-effect transistor serves as the output terminal of the first inverter, connected to the input terminal of the voltage compensation circuit.

[0016] In an optional embodiment, the input terminal of the third P-type field-effect transistor is the gate of the third P-type field-effect transistor, and the input terminal of the second N-type field-effect transistor is the gate of the second N-type field-effect transistor; the output terminal of the third P-type field-effect transistor is the drain of the third P-type field-effect transistor, and the output terminal of the second N-type field-effect transistor is the drain of the second N-type field-effect transistor; the source of the third P-type field-effect transistor is connected to a preset power supply, and the source of the second N-type field-effect transistor is grounded.

[0017] In an optional embodiment, the second inverter includes: a fourth P-type field-effect transistor and a third N-type field-effect transistor;

[0018] The connection point between the input terminal of the fourth P-type field-effect transistor and the input terminal of the third N-type field-effect transistor serves as the input terminal of the second inverter and is connected to the output terminal of the voltage compensation circuit; the connection point between the output terminal of the fourth P-type field-effect transistor and the output terminal of the third N-type field-effect transistor serves as the output terminal of the second inverter and is used to connect to the logic function circuit.

[0019] In an optional embodiment, the input terminal of the fourth P-type field-effect transistor is the gate of the fourth P-type field-effect transistor, and the input terminal of the third N-type field-effect transistor is the gate of the third N-type field-effect transistor; the output terminal of the fourth P-type field-effect transistor is the drain of the fourth P-type field-effect transistor, and the output terminal of the third N-type field-effect transistor is the drain of the third N-type field-effect transistor; the source of the fourth P-type field-effect transistor is connected to a preset power supply, and the source of the third N-type field-effect transistor is grounded.

[0020] Secondly, embodiments of this application also provide a logic circuit, the logic circuit including: a logic function circuit and an input buffer circuit as described in any of the first aspects above, wherein the output terminal of the input buffer circuit is connected to the power supply terminal of the logic function circuit.

[0021] The beneficial effects of this application are:

[0022] This application provides an input buffer circuit and a logic circuit. The input buffer circuit includes a first inverter, a second inverter, and a voltage compensation circuit. The input terminal of the first inverter receives the input voltage. The output terminal of the first inverter is connected to the input terminal of the voltage compensation circuit. The output terminal of the voltage compensation circuit is connected to the input terminal of the second inverter. The output terminal of the voltage compensation circuit is also connected to its input terminal. The output terminal of the second inverter is connected to the power supply terminal of the logic function circuit in the logic circuit to supply power to the logic function circuit. By inverting the input voltage twice using the first and second inverters, noise and interference in the input voltage can be removed, ensuring the accuracy of the output voltage. In addition, the voltage compensation circuit compensates for the output voltage of the first inverter by pulling the low level low and the high level high, so that the voltage signal received by the second inverter remains in the original logic state. That is, if the output of the first inverter is high, the second inverter receives a high level; if the output of the first inverter is low, the second inverter outputs a low level. This avoids the logic function received by the logic function circuit from being disordered due to the instability of the output voltage of the first inverter. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of an input buffer circuit provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram of another input buffer circuit provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of a logic circuit provided in an embodiment of this application.

[0027] Key component symbols: 100 - Input buffer circuit; 110 - First inverter; 120 - Second inverter; 130 - Voltage compensation circuit; 131 - Third inverter; 132 - Pull-up unit; P1 - First P-type field-effect transistor; P2 - Second P-type field-effect transistor; P3 - Third P-type field-effect transistor; P4 - Fourth P-type field-effect transistor; N1 - First N-type field-effect transistor; N2 - Second N-type field-effect transistor; N3 - Third N-type field-effect transistor; 200 - Logic function circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this utility model, but not all embodiments.

[0029] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0031] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0033] The following examples, in conjunction with the accompanying drawings, provide specific illustrations of the input buffer circuit provided in this application.

[0034] Figure 1 This is a schematic diagram of an input buffer circuit provided in an embodiment of this application; as shown. Figure 1 As shown, the input buffer circuit 100 includes: a first inverter 110, a second inverter 120, and a voltage compensation circuit 130;

[0035] The input terminal of the first inverter 110 is used to receive the input voltage. The output terminal of the first inverter 110 is connected to the input terminal of the voltage compensation circuit 130. The output terminal of the voltage compensation circuit 130 is connected to the input terminal of the second inverter 120. The output terminal of the voltage compensation circuit 130 is also connected to the input terminal of the voltage compensation circuit 130. The output terminal of the second inverter 120 is used to connect to the power supply terminal of the logic function circuit 200 in the logic circuit to supply power to the logic function circuit 200.

[0036] In this embodiment, the first inverter 110 and the second inverter 120 are inverters in the input structure of a CMOS logic circuit. After receiving the input voltage, the input terminal of the first inverter 110 inverts the input voltage to obtain the inverted voltage. Since the output terminal of the first inverter 110 is connected to the input terminal of the voltage compensation circuit 130, the first inverter 110 outputs the inverted voltage to the voltage compensation circuit 130. The voltage compensation circuit 130 compensates for the received inverted voltage and further increases the voltage. Since the output terminal of the voltage compensation circuit 130 is connected to the input terminal of the second inverter 120, the voltage compensation circuit 130 outputs the compensated voltage to the second inverter 120. The second inverter 120 inverts the received compensated voltage to obtain the output voltage and outputs the output voltage to the power supply terminal of the logic function circuit 200.

[0037] In one example, when the input voltage received by the first inverter 110 is low, the first inverter 110 inverts the low level and outputs a high level. The voltage compensation circuit 130 pulls the high level high, so that the second inverter 120 receives a high level. The second inverter 120 inverts the high level and outputs a low level to the logic function circuit 200. At this time, the high level output by the first inverter 110 will be attenuated to a certain extent after passing through the first inverter 110. The voltage compensation circuit 130 compensates for this, so that the second inverter 120 receives a high level. This avoids the second inverter 120 mistakenly receiving an attenuated low level due to attenuation, which would cause the logic function circuit 200 to malfunction.

[0038] In another example, when the input voltage received by the first inverter 110 is high, the first inverter 110 inverts the high level and outputs a low level. The low level is pulled low by the voltage compensation circuit 130, so that the second inverter 120 receives a low level. The second inverter 120 inverts the low level and outputs a high level to the logic function circuit 200. At this time, the low level output by the first inverter 110 will be attenuated to a certain extent after passing through the first inverter 110. After compensation by the voltage compensation circuit 130, the second inverter 120 also receives a low level, which will not cause the logic function received by the logic function circuit 200 to be disordered.

[0039] In summary, this application provides an input buffer circuit, which includes a first inverter, a second inverter, and a voltage compensation circuit. The input terminal of the first inverter receives the input voltage, and the output terminal of the first inverter is connected to the input terminal of the voltage compensation circuit. The output terminal of the voltage compensation circuit is connected to the input terminal of the second inverter, and the output terminal of the voltage compensation circuit is also connected to its input terminal. The output terminal of the second inverter is connected to the power supply terminal of the logic function circuit in the logic circuit to supply power to the logic function circuit. By inverting the input voltage twice using the first and second inverters, noise and interference in the input voltage can be removed, ensuring the accuracy of the output voltage. In addition, the voltage compensation circuit compensates for the output voltage of the first inverter by pulling the low level low and the high level high, so that the voltage signal received by the second inverter remains in the original logic state. That is, if the output of the first inverter is high, the second inverter receives a high level; if the output of the first inverter is low, the second inverter outputs a low level. This avoids the logic function received by the logic function circuit from being disordered due to the instability of the output voltage of the first inverter.

[0040] Based on the above embodiments, this application also provides another possible implementation of the input buffer circuit, which can be referred to further. Figure 1 The voltage compensation circuit 130 includes a third inverter 131 and a pull-up unit 132. The input terminal of the third inverter 131 serves as the input terminal of the voltage compensation circuit 130 and is connected to the output terminal of the first inverter 110. The output terminal of the third inverter 131 is connected to the control terminal of the pull-up unit 132. The first terminal of the pull-up unit 132 is used to connect to a preset power supply, and the second terminal of the pull-up unit 132 serves as the output terminal of the voltage compensation circuit 130.

[0041] In this embodiment, the input terminal of the third inverter 131 is connected to the output terminal of the first inverter 110. When the first inverter 110 outputs a high level, the third inverter 131 inverts the high level to obtain a low level. Since the output terminal of the third inverter 131 is connected to the control terminal of the pull-up unit 132, when the control terminal of the pull-up unit 132 receives a low level, the pull-up unit 132 is turned on. Since the first terminal of the pull-up unit 132 is used to connect to the preset power supply, and the second terminal of the pull-up unit 132 serves as the output terminal of the voltage compensation circuit 130, the preset power supply outputs a high level to the input terminal of the second inverter 120 through the pull-up unit 132. The voltage compensation circuit 130 further pulls up the high level output by the first inverter 110, so that the high level received by the input terminal of the second inverter 120 is close to the preset power supply voltage.

[0042] When the first inverter 110 outputs a low level, the third inverter 131 inverts the low level to obtain a high level. Since the output of the third inverter 131 is connected to the control terminal of the pull-up unit 132, the pull-up unit 132 is turned off when the control terminal of the pull-up unit 132 receives a high level. Since the output of the voltage compensation circuit 130 is also connected to the input of the voltage compensation circuit 130, the input of the second inverter 120 receives a low level at this time.

[0043] Based on the above embodiments, this application also provides another possible implementation of the input buffer circuit 100. Figure 2 A schematic diagram of another input buffer circuit provided in an embodiment of this application is shown below. Figure 2 As shown, the pull-up unit 132 is the first P-type field-effect transistor P1, the control terminal of the pull-up unit 132 is the gate of the first P-type field-effect transistor P1, the first terminal of the pull-up unit 132 is the source of the first P-type field-effect transistor P1, and the second terminal of the pull-up unit 132 is the drain of the first P-type field-effect transistor P1.

[0044] Specifically, when the gate of the first P-type field-effect transistor P1 receives a high level, the first P-type field-effect transistor P1 is turned off; when the gate of the first P-type field-effect transistor P1 receives a low level, the first P-type field-effect transistor P1 is turned on.

[0045] Continue to refer to Figure 2 The third inverter 131 includes a second P-type field-effect transistor P2 and a first N-type field-effect transistor N1.

[0046] The connection point between the input terminal of the second P-type field-effect transistor P2 and the input terminal of the first N-type field-effect transistor N1 serves as the input terminal of the third inverter 131 and is connected to the output terminal of the first inverter 110; the connection point between the output terminal of the second P-type field-effect transistor P2 and the output terminal of the first N-type field-effect transistor N1 serves as the output terminal of the third inverter 131 and is connected to the control terminal of the pull-up unit 132.

[0047] Optionally, the input terminal of the second P-type field-effect transistor P2 is the gate of the second P-type field-effect transistor P2, and the input terminal of the first N-type field-effect transistor N1 is the gate of the first N-type field-effect transistor N1; the output terminal of the second P-type field-effect transistor P2 is the drain of the second P-type field-effect transistor P2, and the output terminal of the first N-type field-effect transistor N1 is the drain of the first N-type field-effect transistor N1; the source of the second P-type field-effect transistor P2 is connected to a preset power supply, and the source of the first N-type field-effect transistor N1 is grounded.

[0048] Specifically, when the input terminal of the third inverter 131 receives a high level, that is, when the gates of the second P-type field-effect transistor P2 and the first N-type field-effect transistor N1 receive a high level, the first N-type field-effect transistor N1 is turned on, the second P-type field-effect transistor P2 is turned off, and the output terminal of the third inverter 131 outputs a low level.

[0049] When the input terminal of the third inverter 131 receives a low level, that is, when the gates of the second P-type field-effect transistor P2 and the first N-type field-effect transistor N1 receive a low level, the first N-type field-effect transistor N1 is turned off, the second P-type field-effect transistor P2 is turned on, and the output terminal of the third inverter 131 outputs a high level.

[0050] Continue to refer to Figure 2 The first inverter 110 includes: a third P-type field-effect transistor P3 and a second N-type field-effect transistor N2.

[0051] The connection point between the input terminal of the third P-type field-effect transistor P3 and the input terminal of the second N-type field-effect transistor N2 serves as the input terminal of the first inverter 110, used to receive the input voltage; the connection point between the output terminal of the third P-type field-effect transistor P3 and the output terminal of the second N-type field-effect transistor N2 serves as the output terminal of the first inverter 110, connected to the input terminal of the voltage compensation circuit 130.

[0052] Optionally, the input terminal of the third P-type field-effect transistor P3 is the gate of the third P-type field-effect transistor P3, and the input terminal of the second N-type field-effect transistor N2 is the gate of the second N-type field-effect transistor N2; the output terminal of the third P-type field-effect transistor P3 is the drain of the third P-type field-effect transistor P3, and the output terminal of the second N-type field-effect transistor N2 is the drain of the second N-type field-effect transistor N2; the source of the third P-type field-effect transistor P3 is connected to a preset power supply, and the source of the second N-type field-effect transistor N2 is grounded.

[0053] Specifically, when the input terminal of the first inverter 110 receives a high level, that is, when the gate of the third P-type field-effect transistor P3 and the gate of the second N-type field-effect transistor N2 receive a high level, the second N-type field-effect transistor N2 is turned on, the third P-type field-effect transistor P3 is turned off, and the output terminal of the first inverter 110 outputs a low level.

[0054] When the input terminal of the first inverter 110 receives a low level, that is, when the gate of the third P-type field-effect transistor P3 and the gate of the second N-type field-effect transistor N2 receive a low level, the second N-type field-effect transistor N2 is turned off, the third P-type field-effect transistor P3 is turned on, and the output terminal of the first inverter 110 outputs a high level.

[0055] Continue to refer to Figure 2 The second inverter 120 includes a fourth P-type field-effect transistor P4 and a third N-type field-effect transistor N3.

[0056] The connection point between the input terminal of the fourth P-type field-effect transistor P4 and the input terminal of the third N-type field-effect transistor N3 serves as the input terminal of the second inverter 120 and is connected to the output terminal of the voltage compensation circuit 130; the connection point between the output terminal of the fourth P-type field-effect transistor P4 and the output terminal of the third N-type field-effect transistor N3 serves as the output terminal of the second inverter 120 and is used to connect to the logic function circuit 200.

[0057] Optionally, the input terminal of the fourth P-type field-effect transistor P4 is the gate of the fourth P-type field-effect transistor P4, and the input terminal of the third N-type field-effect transistor N3 is the gate of the third N-type field-effect transistor N3; the output terminal of the fourth P-type field-effect transistor P4 is the drain of the fourth P-type field-effect transistor P4, and the output terminal of the third N-type field-effect transistor N3 is the drain of the third N-type field-effect transistor N3; the source of the fourth P-type field-effect transistor P4 is connected to a preset power supply, and the source of the third N-type field-effect transistor N3 is grounded.

[0058] Specifically, when the input terminal of the second inverter 120 receives a high level, that is, when the gate of the fourth P-type field-effect transistor P4 and the gate of the third N-type field-effect transistor N3 receive a high level, the third N-type field-effect transistor N3 is turned on, the fourth P-type field-effect transistor P4 is turned off, and the output terminal of the second inverter 120 outputs a low level.

[0059] When the input terminal of the second inverter 120 receives a low level, that is, when the gate of the fourth P-type field-effect transistor P4 and the gate of the third N-type field-effect transistor N3 receive a low level, the third N-type field-effect transistor N3 is turned off, the fourth P-type field-effect transistor P4 is turned on, and the output terminal of the second inverter 120 outputs a high level.

[0060] Based on the above embodiments, this application also provides a possible implementation of a logic circuit. Figure 3 A schematic diagram of a logic circuit provided in an embodiment of this application, such as... Figure 3 As shown, the logic circuit includes a logic function circuit 200 and an input buffer circuit 100, with the output terminal of the input buffer circuit 100 connected to the power supply terminal of the logic function circuit 200.

[0061] Specifically, the input buffer circuit 100 outputs a stable voltage to the logic function circuit 200 to ensure the stable and reliable function of the logic circuit. The contents of each module in the input buffer circuit 100 will not be described in detail here.

[0062] The above are merely specific embodiments of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. An input buffer circuit, characterized in that, The input buffer circuit includes: a first inverter, a second inverter, and a voltage compensation circuit; The input terminal of the first inverter is used to receive the input voltage. The output terminal of the first inverter is connected to the input terminal of the voltage compensation circuit. The output terminal of the voltage compensation circuit is connected to the input terminal of the second inverter. The output terminal of the voltage compensation circuit is also connected to the input terminal of the voltage compensation circuit. The output terminal of the second inverter is used to connect to the power supply terminal of the logic function circuit in the logic circuit to supply power to the logic function circuit.

2. The circuit as described in claim 1, characterized in that, The voltage compensation circuit includes: a third inverter and a pull-up unit; The input terminal of the third inverter serves as the input terminal of the voltage compensation circuit and is connected to the output terminal of the first inverter; the output terminal of the third inverter is connected to the control terminal of the pull-up unit, the first terminal of the pull-up unit is used to connect to a preset power supply, and the second terminal of the pull-up unit serves as the output terminal of the voltage compensation circuit.

3. The circuit as described in claim 2, characterized in that, The pull-up unit is a first P-type field-effect transistor, the control terminal of the pull-up unit is the gate of the first P-type field-effect transistor, the first terminal of the pull-up unit is the source of the first P-type field-effect transistor, and the second terminal of the pull-up unit is the drain of the first P-type field-effect transistor.

4. The circuit as described in claim 2, characterized in that, The third inverter includes: a second P-type field-effect transistor and a first N-type field-effect transistor; The connection point between the input terminal of the second P-type field-effect transistor and the input terminal of the first N-type field-effect transistor serves as the input terminal of the third inverter and is connected to the output terminal of the first inverter; the connection point between the output terminal of the second P-type field-effect transistor and the output terminal of the first N-type field-effect transistor serves as the output terminal of the third inverter and is connected to the control terminal of the pull-up unit.

5. The circuit as described in claim 4, characterized in that, The input terminal of the second P-type field-effect transistor is the gate of the second P-type field-effect transistor, and the input terminal of the first N-type field-effect transistor is the gate of the first N-type field-effect transistor; the output terminal of the second P-type field-effect transistor is the drain of the second P-type field-effect transistor, and the output terminal of the first N-type field-effect transistor is the drain of the first N-type field-effect transistor. The source of the second P-type field-effect transistor is connected to the preset power supply, and the source of the first N-type field-effect transistor is grounded.

6. The circuit as described in claim 1, characterized in that, The first inverter includes: a third P-type field-effect transistor and a second N-type field-effect transistor; The connection point between the input terminal of the third P-type field-effect transistor and the input terminal of the second N-type field-effect transistor serves as the input terminal of the first inverter, used to receive the input voltage; the connection point between the output terminal of the third P-type field-effect transistor and the output terminal of the second N-type field-effect transistor serves as the output terminal of the first inverter, connected to the input terminal of the voltage compensation circuit.

7. The circuit as described in claim 6, characterized in that, The input terminal of the third P-type field-effect transistor is the gate of the third P-type field-effect transistor, and the input terminal of the second N-type field-effect transistor is the gate of the second N-type field-effect transistor; the output terminal of the third P-type field-effect transistor is the drain of the third P-type field-effect transistor, and the output terminal of the second N-type field-effect transistor is the drain of the second N-type field-effect transistor; the source of the third P-type field-effect transistor is connected to a preset power supply, and the source of the second N-type field-effect transistor is grounded.

8. The circuit as described in claim 1, characterized in that, The second inverter includes: a fourth P-type field-effect transistor and a third N-type field-effect transistor; The connection point between the input terminal of the fourth P-type field-effect transistor and the input terminal of the third N-type field-effect transistor serves as the input terminal of the second inverter and is connected to the output terminal of the voltage compensation circuit; the connection point between the output terminal of the fourth P-type field-effect transistor and the output terminal of the third N-type field-effect transistor serves as the output terminal of the second inverter and is used to connect to the logic function circuit.

9. The circuit as described in claim 8, characterized in that, The input terminal of the fourth P-type field-effect transistor is the gate of the fourth P-type field-effect transistor, and the input terminal of the third N-type field-effect transistor is the gate of the third N-type field-effect transistor; the output terminal of the fourth P-type field-effect transistor is the drain of the fourth P-type field-effect transistor, and the output terminal of the third N-type field-effect transistor is the drain of the third N-type field-effect transistor. The source of the fourth P-type field-effect transistor is connected to a preset power supply, and the source of the third N-type field-effect transistor is grounded.

10. A logic circuit, characterized in that, The logic circuit includes: a logic function circuit and an input buffer circuit as described in any one of claims 1-9, wherein the output terminal of the input buffer circuit is connected to the power supply terminal of the logic function circuit.

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