A wideband voltage-controlled oscillator based on a PLL chip
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-04
- Publication Date
- 2026-08-14
AI Technical Summary
[0007]本实用新型的目的是提供一种基于PLL芯片的宽带压控振荡装置，解决了通过外部PLL芯片锁定集成VCO并结合电压预置与双环混频结构，实现频率切换速度快、相位噪声差及输出杂散低的技术问题
[0027]本实用新型所述的一种基于PLL芯片的宽带压控振荡装置，解决了通过外部PLL芯片锁定集成VCO并结合电压预置与双环混频结构，实现频率切换速度快、相位噪声差及输出杂散低的技术问题，本实用新型避免PLL与VCO集成带来的寄生耦合，提升频谱纯度，减小杂散，可引入外部FPGA提供的电压预置(V1/V2)，可实现快速VCO频段选择与锁定，跳频时间明显缩短，通过双环(大步进环+小步进环)架构，以及锁相环内置混频器降低反馈分频比，有效减小相位噪声，利用LMX2594的宽带特性，同时通过分立环路设计实现带宽与相噪的兼顾，通过大步进环替代多个点频源，避免多源配置，节省硬件资源。
Smart Images
Figure CN224638044U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of radio frequency microwave electronics technology, and in particular relates to a broadband voltage-controlled oscillator based on a PLL chip. Background Technology
[0002] In the design of broadband signal sources and microwave frequency synthesizers, there is often a trade-off between the bandwidth and phase noise of the voltage-controlled oscillator (VCO). To achieve a wide tuning range, broadband VCOs typically require a lower resonant cavity Q value and a higher KVCO, which leads to a deterioration in phase noise performance, often exceeding that of narrowband products by several decibels.
[0003] Existing common solutions include:
[0004] Wideband VCO direct implementation: Although it can cover a wide frequency range, its phase noise performance is poor and it is difficult to meet the requirements of high-performance systems.
[0005] YIG tuned resonant oscillators (YTOs) have extremely high unloaded Q values and can achieve good phase noise performance, but they are bulky, expensive, and due to the hysteresis effect, the frequency switching speed is usually in the millisecond range, which cannot meet the needs of agile applications.
[0006] Integrated PLL+VCO solution (such as integrated LMX2594): The VCO core and frequency band are selected through internal self-calibration. The structure is compact and easy to control, but the self-calibration time may be on the order of milliseconds. At the same time, since the phase-locked loop and VCO are integrated on the same chip, the circuit coupling is severe, the spurious performance is poor, and it is difficult to balance low phase noise and fast frequency hopping. Utility Model Content
[0007] The purpose of this invention is to provide a broadband voltage-controlled oscillator based on a PLL chip, which solves the technical problem of achieving fast frequency switching speed, poor phase noise, and low output spurious emissions by locking the integrated VCO with an external PLL chip and combining voltage preset with a dual-ring mixing structure.
[0008] To achieve the above objectives, the present invention adopts the following technical solution:
[0009] A broadband voltage-controlled oscillator based on a PLL chip includes a small stepping loop unit, a large stepping loop unit, a power divider PD1, a spectrum generator, a frequency selection switch, and a power divider PD2.
[0010] The small stepping loop unit includes a clock generator chip IC1, a low-pass filter LPF1, an adder SUM1, a voltage-controlled oscillator VCO1, an amplifier A1, a frequency divider DIV1, a mixer X1, a low-pass filter LPF_X1, and an amplifier A2.
[0011] The large stepping ring unit includes a clock generator chip IC3, a low-pass filter LPF2, an adder SUM2, a voltage-controlled oscillator VCO2, a power divider PD3, an amplifier A3, a frequency divider DIV2, a mixer X2, a low-pass filter LPF_X2, and an amplifier A4.
[0012] Power divider PD1 is connected to an external reference clock Fref. Power divider PD1 outputs one signal F1 and one signal F2. Signal F1 is input to clock generator chip IC1 and clock generator chip IC3 respectively. Clock generator chip IC1 is connected to low-pass filter LPF1. Low-pass filter LPF1 is connected to adder SUM1. Adder SUM1 is connected to voltage-controlled oscillator VCO1. VCO1 outputs the Foutx1 signal. The Foutx1 signal is input to power divider PD2. Power divider PD2 outputs one Fout signal and one signal F5. Signal F5 is output to amplifier A1. Amplifier A1 is connected to frequency divider DIV1. Frequency divider DIV1 is connected to mixer X1. Mixer X1 is connected to low-pass filter LPF_X1. Low-pass filter LPF_X1 is connected to amplifier A2. Amplifier A2 is connected to clock generator chip IC1.
[0013] Clock generator chip IC3 is connected to low-pass filter LPF2, low-pass filter LPF2 is connected to adder SUM2, adder SUM2 is connected to voltage-controlled oscillator VCO2, voltage-controlled oscillator VCO2 outputs signal Foutx2, signal Foutx2 is input to power divider PD3, PD3 outputs one signal F3 and one signal F4, signal F3 is input to mixer X1, signal F4 is input to amplifier A3, amplifier A3 is connected to frequency divider DIV2, frequency divider DIV2 is connected to mixer X2, mixer X2 is connected to low-pass filter LPF_X2, low-pass filter LPF_X2 is connected to amplifier A4, amplifier A4 is connected to clock generator chip IC3;
[0014] Signal F2 is connected to the comb pattern generator, the comb pattern generator is connected to the frequency selector switch, and the frequency selector switch is connected to mixer X2;
[0015] Adder SUM1 is connected to the preset voltage V1; adder SUM2 is connected to the preset voltage V2.
[0016] Preferably, the clock generator chip IC1 includes an R divider FD1, a phase detector PFD1, and a loop divider N1;
[0017] Signal F1 is input to R divider FD1, R divider FD1 is connected to phase detector PFD1, phase detector PFD1 outputs signal CPout1, signal CPout1 is input to low-pass filter LPF1;
[0018] Amplifier A2 is connected to loop divider N1, and loop divider N1 is connected to R divider FD1;
[0019] The clock generator chip IC3 includes an R divider FD2, a phase detector PFD2, and a loop divider N2.
[0020] Signal F1 is input to R divider FD2, R divider FD2 is connected to phase detector PFD2, phase detector PFD2 outputs signal CPout2, signal CPout2 is input to low-pass filter LPF2;
[0021] Amplifier A4 is connected to loop divider N2, and loop divider N2 is connected to phase detector PFD2.
[0022] Preferably, both the clock generator chip IC1 and the clock generator chip IC2 are HMC704.
[0023] Preferably, both the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 are model LMX2594.
[0024] Preferably, both the pre-set voltage V1 and the pre-set voltage V2 are provided by an external FPGA.
[0025] Preferably, the FPGA outputs the pre-set voltage V1 and the pre-set voltage V2 through an analog-to-digital converter (DA) chip.
[0026] Preferably, the mixers X1 and X2 are both HMC220B; the frequency dividers DIV1 and DIV2 are both HMC361; the low-pass filters LPF1 and LPF2 are ALF-12000, and the low-pass filters LPF_X1 and LPF_X2 are both LFCN-5500; the amplifiers A1, A2, A3, and A4 are all HMC998; the adders SUM1 and SUM2 are ADA4528-2; the power dividers PD1, PD2, and PD3 are all IPD-0118-PQ5; and the comb pattern generator is WZD000045-B50-H.
[0027] This invention discloses a broadband voltage-controlled oscillator based on a PLL chip, which solves the technical problem of achieving fast frequency switching, poor phase noise, and low output spurious emissions by locking an integrated VCO with an external PLL chip and combining voltage preset with a dual-loop mixer structure. This invention avoids parasitic coupling caused by the integration of PLL and VCO, improves spectral purity, and reduces spurious emissions. It can introduce voltage presets (V1 / V2) provided by an external FPGA to achieve fast VCO frequency band selection and locking, significantly shortening the frequency hopping time. Through a dual-loop (large stepping loop + small stepping loop) architecture and a PLL-built-in mixer to reduce the feedback division ratio, it effectively reduces phase noise. It utilizes the broadband characteristics of the LMX2594 and achieves a balance between bandwidth and phase noise through discrete loop design. By replacing multiple point frequency sources with a large stepping loop, it avoids multi-source configuration and saves hardware resources. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the principle of this utility model;
[0029] Figure 2 This is an equivalent schematic diagram of the signal flow direction of the small stepping loop unit or the large stepping loop unit of this utility model;
[0030] Figure 3 This is a schematic diagram illustrating the chip connection principle between HMC704 and LMX2594 of this utility model. Detailed Implementation
[0031] Depend on Figures 1-3 The broadband voltage-controlled oscillator based on a PLL chip shown includes a small stepping loop unit, a large stepping loop unit, a power divider PD1, a spectrum generator, a frequency selection switch, and a power divider PD2.
[0032] The small stepping loop unit includes a clock generator chip IC1, a low-pass filter LPF1, an adder SUM1, a voltage-controlled oscillator VCO1, an amplifier A1, a frequency divider DIV1, a mixer X1, a low-pass filter LPF_X1, and an amplifier A2.
[0033] The large stepping ring unit includes a clock generator chip IC3, a low-pass filter LPF2, an adder SUM2, a voltage-controlled oscillator VCO2, a power divider PD3, an amplifier A3, a frequency divider DIV2, a mixer X2, a low-pass filter LPF_X2, and an amplifier A4.
[0034] The clock generator chip IC1 includes an R divider FD1, a phase detector PFD1, and a loop divider N1;
[0035] Signal F1 is input to R divider FD1, R divider FD1 is connected to phase detector PFD1, phase detector PFD1 outputs signal CPout1, signal CPout1 is input to low-pass filter LPF1;
[0036] Amplifier A2 is connected to loop divider N1, and loop divider N1 is connected to R divider FD1;
[0037] The clock generator chip IC3 includes an R divider FD2, a phase detector PFD2, and a loop divider N2.
[0038] Signal F1 is input to R divider FD2, R divider FD2 is connected to phase detector PFD2, phase detector PFD2 outputs signal CPout2, signal CPout2 is input to low-pass filter LPF2;
[0039] Amplifier A4 is connected to loop divider N2, and loop divider N2 is connected to phase detector PFD2.
[0040] Power divider PD1 is connected to an external reference clock Fref. Power divider PD1 outputs one signal F1 and one signal F2. Signal F1 is input to clock generator chip IC1 and clock generator chip IC3 respectively. Clock generator chip IC1 is connected to low-pass filter LPF1. Low-pass filter LPF1 is connected to adder SUM1. Adder SUM1 is connected to voltage-controlled oscillator VCO1. VCO1 outputs the Foutx1 signal. The Foutx1 signal is input to power divider PD2. Power divider PD2 outputs one Fout signal and one signal F5. Signal F5 is output to amplifier A1. Amplifier A1 is connected to frequency divider DIV1. Frequency divider DIV1 is connected to mixer X1. Mixer X1 is connected to low-pass filter LPF_X1. Low-pass filter LPF_X1 is connected to amplifier A2. Amplifier A2 is connected to clock generator chip IC1.
[0041] Clock generator chip IC3 is connected to low-pass filter LPF2, low-pass filter LPF2 is connected to adder SUM2, adder SUM2 is connected to voltage-controlled oscillator VCO2, voltage-controlled oscillator VCO2 outputs signal Foutx2, signal Foutx2 is input to power divider PD3, PD3 outputs one signal F3 and one signal F4, signal F3 is input to mixer X1, signal F4 is input to amplifier A3, amplifier A3 is connected to frequency divider DIV2, frequency divider DIV2 is connected to mixer X2, mixer X2 is connected to low-pass filter LPF_X2, low-pass filter LPF_X2 is connected to amplifier A4, amplifier A4 is connected to clock generator chip IC3;
[0042] Signal F2 is connected to the comb pattern generator, the comb pattern generator is connected to the frequency selector switch, and the frequency selector switch is connected to mixer X2;
[0043] Adder SUM1 is connected to the preset voltage V1; adder SUM2 is connected to the preset voltage V2.
[0044] Both the clock generator chip IC1 and the clock generator chip IC2 are HMC704.
[0045] Both the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 are model LMX2594.
[0046] Both the pre-set voltage V1 and the pre-set voltage V2 are provided by an external FPGA.
[0047] The FPGA outputs the pre-set voltage V1 and the pre-set voltage V2 through an analog-to-digital converter (DA) chip.
[0048] The mixers X1 and X2 are both HMC220B; the frequency dividers DIV1 and DIV2 are both HMC361; the low-pass filters LPF1 and LPF2 are ALF-12000, and the low-pass filters LPF_X1 and LPF_X2 are both LFCN-5500; the amplifiers A1, A2, A3, and A4 are all HMC998; the adders SUM1 and SUM2 are ADA4528-2; the power dividers PD1, PD2, and PD3 are all IPD-0118-PQ5; and the comb pattern generator is WZD000045-B50-H.
[0049] In this embodiment, as Figure 2 The external input signal Fref shown is emitted through a crystal oscillator Y1. Figure 2 This is an equivalent schematic diagram of the signal flow of the small stepping loop unit and the large stepping loop unit. The external input signal Fref first enters the PDF (clock generator chip IC1 or clock generator chip IC2), then passes through the low-pass filter LPF (i.e., low-pass filter LPF1 or low-pass filter LPF2), and then enters the adder SUM (SUM1 or SUM2). The input of SUM is also connected to the pre-set voltage Vset issued by the FPGA through DA. After processing by the adder, the signal output by SUM is sent to the voltage-controlled oscillator VCO (VCO1 or VCO2), and finally outputs the signal Foutx (Foutx1 or Foutx2). The voltage-controlled oscillator VCO also outputs a signal to the frequency divider DIV (DIV1 or DIV2), and after distribution, it is fed back to the PDF.
[0050] In this embodiment, the LMX2594 is used only as a voltage-controlled oscillator, and its principle is as follows: Figure 3 The diagram shown illustrates the chip connection between HMC704 and LMX2594. ICA stands for HMC704. Figure 1 IC1 or IC3 corresponds to ICB, which is LMX2594. Figure 1 IC2 or IC4 corresponds to LPF and Figure 1 The low-pass filter LPF1 or low-pass filter LPF2 corresponds to DIV and Figure 1 The frequency divider DIV1 or DIV2 corresponds to this. It can be seen that the signal processing flow of Fref is as follows: First, it enters the HMC704 and is then filtered by the low-pass filter LPF before entering the LMX2594. The LMX2594 outputs the signal Foutx, which is then split into two paths by the splitter PD. One path is the output Fn / Fout, and the other path is Fn, where Fn is F3 / F4 / F5.
[0051] The external reference clock Fref first enters the power divider PD1, and is then split into two signals F1 and F2. Signal F1 is input to the clock generator chip IC1 of the small step-loop unit and the clock generator chip IC3 of the large step-loop unit, respectively. In the small step-loop, F1 is adjusted in frequency by the R divider FD1 and then enters the phase detector PFD1. The control signal CPout1 output by PFD1 is filtered by the low-pass filter LPF1 and then enters the adder SUM1. SUM1 is added to the preset voltage V1 provided by the external FPGA, controlling the voltage-controlled oscillator VCO1 to generate the wideband output signal Foutx1. Foutx1 passes through the power divider PD2, with one output being the final signal Fout, and the other F5 entering amplifier A1. After passing through the frequency divider DIV1 and mixer X1, it is down-converted and then passed through the low-pass filter LPF_X1 and amplifier A2, feeding back to the loop divider N1 of IC1 to realize the phase-locked loop closed-loop control.
[0052] In the large stepping loop, F1, after its frequency is adjusted by the R divider FD2, is input to the phase detector PFD2. The CPout2 signal output by PFD2 passes through the low-pass filter LPF2 and is then input to the adder SUM2. The adder SUM2 is added to the preset voltage V2 provided by the external FPGA and controls the voltage-controlled oscillator VCO2 to output Foutx2. Foutx2 passes through the power divider PD3 and is divided into F3 and F4: F3 is input to the mixer X1 and mixed with the small stepping loop signal for down-conversion. F4 passes through amplifier A3, divider DIV2, mixer X2, low-pass filter LPF_X2, and amplifier A4 and is then fed back to the loop divider N2 of IC3 to form a closed-loop control.
[0053] Signal F2 enters the spectrum generator from the power divider PD1, then selects the desired frequency channel via a frequency selector switch, and is output to mixer X2 to achieve mixing and down-conversion of the large-step loop signal and the small-step loop signal. In the overall system, the small-step loop mainly achieves fine frequency locking, the large-step loop provides wide bandwidth coverage and fast frequency transitions, mixers X1 / X2 perform frequency conversion, adders SUM1 / SUM2 achieve voltage preset locking through preset voltages V1 / V2, amplifiers A1 to A4 provide gain and drive capability, and low-pass filters LPF1 / LPF2 / LPF_X1 / LPF_X2 perform loop noise filtering and signal shaping, thereby completing wideband low-phase-noise frequency synthesis and output.
[0054] In this embodiment, the LMX2594 undergoes some pre-configuration before leaving the factory, enabling it to be used solely as a voltage-controlled oscillator (VCO). Specifically, during use, other components such as the phase detector and charge pump are simply shut down via a control word. VCO control primarily depends on three parameters: the VCO core, the VCO frequency band, and the VCO bias. Therefore, by pre-determining the data written to the register corresponding to the VCO output frequency band, bypass self-calibration can be achieved. The specific operation is as follows:
[0055] Configure the MUXOUT pin of LMX2594 to "readback" mode, lock the VCO through the self-calibration algorithm, provide a clock pulse to the CLK pin, and keep the LE pin at a high level to read back the VCO core and frequency band information from MUXOUT.
[0056] Repeat the above steps to read back the VCO bias code and record the VCO configuration parameters corresponding to the output frequency band in the lookup table for quick lookup next time.
[0057] Disable self-calibration mode, set VCO write mode to write VCO core and frequency band, and write the aforementioned data.
[0058] Set the VCO write mode to write VCO bias code and write the corresponding data.
[0059] Configure the data for the R divider and N divider to complete the frequency output.
[0060] VCO configuration is performed via the SPI serial interface. The initial power-on requires some time to write data, but subsequent frequency transitions only require writing to a small number of registers to complete the update. If a high-speed processor is used, the configuration time is well within acceptable limits.
[0061] This embodiment uses a discrete phase-locked loop (PLL) chip to control the integrated VCO, which effectively reduces the electromagnetic coupling between the PLL and the VCO, thereby significantly reducing the output stray power.
[0062] Table 1 shows a comparison of the phase noise of the LMX2594 single chip with the phase noise of the HMC704 externally locked LMX2594.
[0063]
[0064] Table 1
[0065] It can be seen that, compared to the LMX2594 single-chip, the phase noise values of the HMC704 externally locked LMX2594 are very close within 1MHz when using integer division; however, in the 11.15GHz fractional division mode, it is slightly worse than the LMX2594 single-chip. But the locking time is much faster than the LMX2594.
[0066] This invention discloses a broadband voltage-controlled oscillator based on a PLL chip, which solves the technical problem of achieving fast frequency switching, poor phase noise, and low output spurious emissions by locking an integrated VCO with an external PLL chip and combining voltage preset with a dual-loop mixer structure. This invention avoids parasitic coupling caused by the integration of PLL and VCO, improves spectral purity, and reduces spurious emissions. It can introduce voltage presets (V1 / V2) provided by an external FPGA to achieve fast VCO frequency band selection and locking, significantly shortening the frequency hopping time. Through a dual-loop (large stepping loop + small stepping loop) architecture and a PLL-built-in mixer to reduce the feedback division ratio, it effectively reduces phase noise. It utilizes the broadband characteristics of the LMX2594 and achieves a balance between bandwidth and phase noise through discrete loop design. By replacing multiple point frequency sources with a large stepping loop, it avoids multi-source configuration and saves hardware resources.
Claims
1. A wideband voltage-controlled oscillator device based on a PLL chip, characterized by: It includes a small stepping loop unit, a large stepping loop unit, a power divider PD1, a comb pattern generator, a frequency selection switch, and a power divider PD2; The small stepping loop unit includes a clock generator chip IC1, a low-pass filter LPF1, an adder SUM1, a voltage-controlled oscillator VCO1, an amplifier A1, a frequency divider DIV1, a mixer X1, a low-pass filter LPF_X1, and an amplifier A2. The large stepping ring unit includes a clock generator chip IC3, a low-pass filter LPF2, an adder SUM2, a voltage-controlled oscillator VCO2, a power divider PD3, an amplifier A3, a frequency divider DIV2, a mixer X2, a low-pass filter LPF_X2, and an amplifier A4. Power divider PD1 is connected to an external reference clock Fref. Power divider PD1 outputs one signal F1 and one signal F2. Signal F1 is input to clock generator chip IC1 and clock generator chip IC3 respectively. Clock generator chip IC1 is connected to low-pass filter LPF1. Low-pass filter LPF1 is connected to adder SUM1. Adder SUM1 is connected to voltage-controlled oscillator VCO1. VCO1 outputs the Foutx1 signal. The Foutx1 signal is input to power divider PD2. Power divider PD2 outputs one Fout signal and one signal F5. Signal F5 is output to amplifier A1. Amplifier A1 is connected to frequency divider DIV1. Frequency divider DIV1 is connected to mixer X1. Mixer X1 is connected to low-pass filter LPF_X1. Low-pass filter LPF_X1 is connected to amplifier A2. Amplifier A2 is connected to clock generator chip IC1. Clock generator chip IC3 is connected to low-pass filter LPF2, low-pass filter LPF2 is connected to adder SUM2, adder SUM2 is connected to voltage-controlled oscillator VCO2, voltage-controlled oscillator VCO2 outputs signal Foutx2, signal Foutx2 is input to power divider PD3, PD3 outputs one signal F3 and one signal F4, signal F3 is input to mixer X1, signal F4 is input to amplifier A3, amplifier A3 is connected to frequency divider DIV2, frequency divider DIV2 is connected to mixer X2, mixer X2 is connected to low-pass filter LPF_X2, low-pass filter LPF_X2 is connected to amplifier A4, amplifier A4 is connected to clock generator chip IC3; Signal F2 is connected to the comb pattern generator, the comb pattern generator is connected to the frequency selector switch, and the frequency selector switch is connected to mixer X2; Adder SUM1 is connected to the preset voltage V1; adder SUM2 is connected to the preset voltage V2.
2. A wideband voltage controlled oscillator based on a PLL chip as claimed in claim 1, characterized in that: The clock generator chip IC1 includes an R divider FD1, a phase detector PFD1, and a loop divider N1; Signal F1 is input to R divider FD1, R divider FD1 is connected to phase detector PFD1, phase detector PFD1 outputs signal CPout1, signal CPout1 is input to low-pass filter LPF1; Amplifier A2 is connected to loop divider N1, and loop divider N1 is connected to R divider FD1; The clock generator chip IC3 includes an R divider FD2, a phase detector PFD2, and a loop divider N2. Signal F1 is input to R divider FD2, R divider FD2 is connected to phase detector PFD2, phase detector PFD2 outputs signal CPout2, signal CPout2 is input to low-pass filter LPF2; Amplifier A4 is connected to loop divider N2, and loop divider N2 is connected to phase detector PFD2.
3. The wideband voltage controlled oscillator based on PLL chip according to claim 1, wherein: Both the clock generator chip IC1 and the clock generator chip IC2 are HMC704.
4. The wideband voltage controlled oscillator based on PLL chip according to claim 1, wherein: Both the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 are model LMX2594.
5. The wideband voltage controlled oscillator based on PLL chip according to claim 1, wherein: Both the pre-set voltage V1 and the pre-set voltage V2 are provided by an external FPGA.
6. A wideband voltage controlled oscillator based on a PLL chip as recited in claim 5, characterized in that: The FPGA outputs the pre-set voltage V1 and the pre-set voltage V2 through an analog-to-digital converter (DA) chip.
7. A broadband voltage-controlled oscillator based on a PLL chip as described in claim 1, characterized in that: The mixers X1 and X2 are both HMC220B; the frequency dividers DIV1 and DIV2 are both HMC361; the low-pass filters LPF1 and LPF2 are ALF-12000, and the low-pass filters LPF_X1 and LPF_X2 are both LFCN-5500; the amplifiers A1, A2, A3, and A4 are all HMC998; the adders SUM1 and SUM2 are ADA4528-2; the power dividers PD1, PD2, and PD3 are all IPD-0118-PQ5; and the comb pattern generator is WZD000045-B50-H.