Semiconductor devices

Abstract

Embodiments of this utility model provide a semiconductor device including a plurality of back dielectric layers and a transistor structure in the back dielectric layers. The transistor structure includes a first source / drain, a second source / drain above the first source / drain, a channel layer extending vertically between the first source / drain and the second source / drain, a gate laterally surrounding the channel layer, and one or more hydrogen barrier columns extending along one or more sides of the gate to prevent, minimize, and / or otherwise reduce hydrogen diffusion into the channel layer of the transistor structure.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor device, and more particularly to a semiconductor device that includes a hydrogen barrier column in a memory array. Background Technology

[0002] A non-volatile memory cell is a type of memory cell that may include transistors connected in series with memory components such as capacitors, phase change material layers, resistive layers, and / or magnetic layers. This may be referred to as a single transistor-single memory module (1T-1X) cell. In a 1T-1X cell, the memory components selectively store data (e.g., logic "1" or logic "0" values) based on factors such as charge, resistivity, capacitance, and / or magnetic fields. The state of the memory components can be selectively modified and / or read by charging or discharging the memory components using transistors. Utility Model Content

[0003] An embodiment of the present invention provides a semiconductor device including a plurality of back dielectric layers and a transistor structure in the back dielectric layers. The transistor structure includes a first source / drain, a second source / drain above the first source / drain, a channel layer extending vertically between the first source / drain and the second source / drain, a gate laterally surrounding the channel layer, and one or more hydrogen barrier columns extending along one or more sides of the gate.

[0004] An embodiment of this utility model provides a semiconductor device including a plurality of back-end dielectric layers and a memory cell structure in the back-end dielectric layers. The memory cell structure includes a storage structure and a transistor structure on the storage structure. The transistor structure includes a first source / drain, a second source / drain on the first source / drain, a channel layer extending vertically between the first source / drain and the second source / drain, a gate laterally surrounding the channel layer, a first hydrogen barrier column extending along a first side of the gate, and a second hydrogen barrier column extending along a second side of the gate opposite to the first side.

[0005] Based on the above, the semiconductor device of an embodiment of this utility model includes a hydrogen barrier array, which may be contained between the gate and one or more other layers of the semiconductor device to prevent, minimize, and / or otherwise reduce hydrogen diffusion into the vertical channel layer of the transistor structure. The hydrogen barrier array includes one or more materials that resist hydrogen absorption, which prevents, minimizes, and / or otherwise reduces the possibility of hydrogen diffusion into the vertical channel layer of the transistor structure. In this way, the hydrogen barrier array prevents, minimizes, and / or otherwise reduces the possibility of hydrogen contamination in the oxide semiconductor material of the vertical channel layer, which enables the memory cell structure to achieve low current leakage and reduces the possibility of data corruption and / or failure of the memory cell structure, etc.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a diagram of an exemplary semiconductor device described herein.

[0008] Figure 2A and Figure 2B This is a diagram of an exemplary embodiment of the memory cell structure described herein.

[0009] Figure 3A and Figure 3B This is a diagram of an exemplary embodiment of the memory cell structure described herein.

[0010] Figure 4A-4P This is a diagram of an exemplary embodiment of a memory array forming the semiconductor device described herein.

[0011] Figure 5A-5K This is a diagram of an exemplary embodiment of forming hydrogen barrier columns in a memory array of a semiconductor device as described herein.

[0012] Figure 6 This is a diagram illustrating examples of temperature offset instability in various memory cell structures.

[0013] Figure 7 This is a flowchart of an example process related to forming the memory cell structure described herein. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0015] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0016] In some cases, the transistors in a 1T-1X memory cell structure may include oxide semiconductor channels (e.g., channel layers comprising oxide semiconductor material). The use of oxide semiconductor channels, compared to elemental semiconductor channels or group III-V compound semiconductor channels, can provide reduced current leakage in a 1T-1X memory cell structure, which improves charge retention (and therefore data retention) in the memory components of the 1T-1X memory cell structure.

[0017] However, oxide semiconductor materials are highly susceptible to hydrogen contamination. If hydrogen diffuses into the oxide semiconductor channels of a 1T-1X memory cell structure, the charge carrier concentration in the oxide semiconductor channels may increase. This increased charge carrier concentration can lead to increased turn-off current leakage, increased positive bias temperature instability (PBTI), and / or increased negative bias temperature instability (NBTI) in the 1T-1X memory cell structure. Increased turn-off current leakage may increase the rate at which charge is depleted in the memory component, resulting in an increased refresh rate to replenish the charge in the memory component to prevent data loss. This increases the power consumption of the 1T-1X memory cell structure, thereby reducing its power efficiency. Additionally and / or alternatively, hydrogen contamination in the oxide semiconductor channels may increase the charge carrier concentration to the point that the 1T-1X memory cell structure falls into a normally-on configuration, rendering it inoperable. Increasing the gate length of the transistor can reduce current leakage through the transistor at the cost of reducing the memory cell density in a semiconductor device including the 1T-1X memory cell structure.

[0018] In some embodiments described herein, a semiconductor device includes a memory cell structure (e.g., a 1T-1X memory cell structure) comprising a transistor structure and a storage structure corresponding to a memory component of the memory cell structure. The channel layer of the transistor structure extends in a vertical direction of the semiconductor device (e.g., in the z-direction approximately perpendicular to the surface of the substrate of the semiconductor device), and a gate and a corresponding gate dielectric layer each surround the channel layer. This allows for an increase in gate length with minimal to no increase in the horizontal or lateral (e.g., xy-direction) size of the memory cell structure. The vertical alignment of the channel layer increases the channel area of ​​the transistor structure, enabling the memory cell structure to achieve low leakage current and high horizontal or lateral density of memory cell structures within the semiconductor device. The low current leakage of the memory cell structure allows data stored in the storage structure of the memory cell structure to remain for a longer duration between refreshes, thereby reducing the power consumption of the memory cell structure and improving its power efficiency.

[0019] A hydrogen-blocking column can be included between the gate and one or more other layers of a semiconductor device to prevent, minimize, and / or otherwise reduce hydrogen diffusion into the vertical channel layer of a transistor structure. The hydrogen-blocking column comprises one or more materials that resist hydrogen absorption, which prevents, minimizes, and / or otherwise reduces the likelihood of hydrogen diffusion into the vertical channel layer of the transistor structure. In this way, the hydrogen-blocking column prevents, minimizes, and / or otherwise reduces the possibility of hydrogen contamination in the oxide semiconductor material of the vertical channel layer, which enables memory cell structures to achieve low current leakage and reduces the likelihood of data corruption and / or failure in the memory cell structure.

[0020] Figure 1 This is a diagram of the exemplary semiconductor device 100 described herein. Semiconductor device 100 may include a semiconductor memory device or another type of semiconductor device, which includes a memory array 102 comprising a plurality of memory cell structures 104. In some embodiments, memory array 102 is contained in a back-end region (e.g., a back-end of line (BEOL) region) of semiconductor device 100. In some embodiments, memory array 102 is contained in another region of semiconductor device 100.

[0021] In some embodiments, the memory cell structures 104 are arranged in a grid within the memory array 102. For example, the memory array 102 may include multiple rows and columns, with each memory cell structure 104 located at the intersection of a row and a column in the memory array 102. The rows may extend in the x-direction within the semiconductor device 100, and the columns may extend in the y-direction within the semiconductor device 100. In some embodiments, the memory cell structures 104 are configured in the memory array in another arrangement.

[0022] The memory cell structure 104 may be a 1T-1X memory cell including a transistor structure 106 electrically coupled to the storage structure 108. As described above, the memory array 102 may be included in the back-end region of the semiconductor device 100. Therefore, the transistor structure 106 of the memory cell structure 104 may be referred to as a back-end transistor structure, and the memory cell structure 104 may be referred to as a back-end memory cell structure.

[0023] The transistor structure 106 of the memory cell structure 104 may be vertically positioned in the z-direction above the storage structure 108 of the memory cell structure 104 in the semiconductor device 100. Alternatively, the storage structure 108 may be positioned above the transistor structure 106. The transistor structure 106 may be configured to be selectively activated and provide access to the associated storage structure 108, enabling one or more types of memory operations to be performed on the memory cell structure 104. Examples of such memory operations include write operations (or programming operations) (e.g., where the storage structure 108 is programmed to store a specific logic value), read operations (e.g., where a logic value is read from the storage structure 108), and / or erase operations (e.g., where a logic value is erased from the storage structure 108).

[0024] Storage structure 108 includes capacitor structures (e.g., deep trench capacitor (DTC) structures, thin-film capacitor structures), ferroelectric storage structures, magnetic storage structures, resistive storage structures, phase change material storage structures, and / or another type of storage structure that can be configured to correspond to two or more states corresponding to one or more logic values. For example, a first state (e.g., a first charge, a first polarity, a first resistance) may correspond to a logic value of "0", and a second state (e.g., a second charge, a second polarity, a second resistance) may correspond to a logic value of "1". In some embodiments, storage structure 108 may be configured to have more than two candidate states.

[0025] Storage structure 108 is contained vertically below (e.g., in the z-direction) of transistor structure 106 and electrically coupled to the source / drain 110 (e.g., bottom source / drain) of transistor structure 106. "Source / drain" may refer to either the source or the drain individually or collectively, depending on the context. In some embodiments, the source / drain may be the source of a first transistor structure and the drain of a second transistor structure, such that the source of the first transistor structure and the drain of the second transistor structure are connected and implemented through the same physical structure. Transistor structure 106 also includes another source / drain 112 (e.g., top source / drain) located above the source / drain 110 in the z-direction.

[0026] The channel layer 114 of transistor structure 106 may be vertically located between source / drain 110 and source / drain 112 (and may extend vertically between source / drain 110 and source / drain 112). Therefore, source / drain 110, channel layer 114 (vertical channel layer), and source / drain 112 are vertically arranged in the z-direction of transistor structure 106. The source / drain (110 and 112) may be located at opposite ends of channel layer 114.

[0027] Transistor structure 106 includes a gate 116 and a gate dielectric layer 118, both of which are laterally adjacent to one or more sides of a channel layer 114 between the source and drain (110 and 112). In some embodiments, both the gate 116 and the gate dielectric layer 118 are laterally surrounded on at least three sides of the channel layer 114, thereby providing greater gate control over the conductivity of the channel layer 114. In some embodiments, both the gate 116 and the gate dielectric layer 118 are completely laterally surrounded on all sides of the channel layer 114, which provides further gate control over the conductivity of the channel layer 114. This can reduce current leakage through the channel layer 114 between the source and drain (110 and 112) and / or increase the drive current through the channel layer 114.

[0028] In some embodiments, gates 116 extend in a column in the y-direction of semiconductor device 100 and are electrically connected to a plurality of transistor structures 106 in a column of memory cell structures 104 in memory array 102. Each transistor structure 106 in memory cell structure 104 may include a gate dielectric layer 118 between a gate and a channel layer 114, and the gate dielectric layer 118 surrounds one or more sides of the channel layer 114.

[0029] like Figure 1As further shown, a hydrogen barrier array 120 is included on one or more sides of the gate 116 of the transistor structure 106 along the memory cell structure 104 and laterally adjacent to one or more sides of the gate 116. The hydrogen barrier array 120 may be included laterally adjacent to the gate 116 of the transistor structure 106 in the memory array 102 to prevent, minimize, and / or reduce hydrogen diffusion from other layers and / or structures in the semiconductor device 100 into the channel layer 114 (e.g., through the gate 116). The hydrogen barrier array 120 may extend along the gate 116 in the y-direction, and one or more hydrogen barrier arrays 120 are located between adjacent gates 116. In other words, the hydrogen barrier array 120 and the gate 116 may each extend in the y-direction and may be arranged alternately in the x-direction of the memory array 102. Therefore, the hydrogen barrier array 120 may be located next to the gate 116 and may extend along opposite sides of the gate 116. The hydrogen barrier array 120 may extend continuously along the gate 116 in the y direction (e.g., as opposed to being composed of multiple discontinuous segments), such that the hydrogen barrier array 120 provides hydrogen diffusion barrier along the entire length of the gate 116.

[0030] In some embodiments, the hydrogen barrier columns 120 are discrete rows that are not connected together. In some embodiments, the hydrogen barrier columns 120 are connected together at their ends by connection segments 120a. In these embodiments, the combination of the hydrogen barrier columns 120 and the connection segments 120a may surround the gate 116 in the memory array 102 to provide hydrogen diffusion barrier along all sides of the gate 116.

[0031] Additionally, the hydrogen barrier array 120 along the side of the gate 116 may have a bottom surface approximately coplanar with the bottom surface of the gate 116, and a top surface approximately coplanar with the top surface of the gate 116. This may be attributed to the hydrogen barrier array 120 being used as a self-aligned shield to form the gate 116 and / or to the hydrogen barrier array 120 and the gate 116 being planarized in the same planarization operation.

[0032] In some embodiments, the hydrogen barrier column 120 may have a lateral width ranging from about 10 nanometers to about 100 nanometers. Figure 1(The size is indicated as D1). If the lateral width of the hydrogen barrier column 120 is less than about 10 nanometers, the hydrogen barrier column 120 may not be able to effectively prevent hydrogen diffusion into the channel layer 114. Furthermore, the likelihood of the hydrogen barrier column 120 collapsing (e.g., due to stress from planarization and / or other processing operations) increases at lateral widths less than about 10 nanometers. If the lateral width of the hydrogen barrier column 120 is greater than about 100 nanometers, the hydrogen barrier column 120 may occupy too much space in the memory array 102, preventing sufficient density of the memory cell structure 104. Alternatively, the lateral size of the gate 116 can be reduced to accommodate a larger hydrogen barrier column 120, thereby reducing channel control and / or increasing channel leakage. If the lateral width of the hydrogen barrier column 120 is contained within the range of about 10 nanometers to about 100 nanometers, the hydrogen barrier column 120 can effectively prevent hydrogen diffusion into the channel layer 114 with minimal possibility of collapse, while still enabling high density of the memory cell structure 104 in the memory array 102. However, other values ​​and ranges besides approximately 10 nanometers to approximately 100 nanometers are also within the scope of this disclosure.

[0033] The source / drain 112 of the transistor structure 106 of the memory cell structure 104 may be electrically coupled in the z-direction to a bit line conductive structure 122 above the source / drain 112. The bit line conductive structure 122 may extend in the x-direction of the semiconductor device 100 and may be approximately perpendicular to the hydrogen barrier column 120 in the memory array 102. In some embodiments, the source / drain 112 of the transistor structure 106 included in the same x-direction row of the memory array 102 may be electrically coupled to the same bit line conductive structure 122. The bit line conductive structure 122 may each include a metallization layer, a trench, a conductive trace, and / or another type of conductive structure.

[0034] The memory cell structure 104 may include a source / drain interconnect structure 124 that electrically couples the storage structure 108 of the memory cell structure 104 to the source / drain 110 of the transistor structure 106 of the memory cell structure 104. The source / drain interconnect structure 124 may include vias, pillars, struts, and / or another type of elongated structure in the z-direction. The source / drain interconnect structure 124 may be located below the source / drain 110 and above the storage structure 108 in the z-direction.

[0035] The gate 116 of the transistor structure 106 of the memory cell structure 104 may be electrically and / or physically coupled to the word line interconnect structure 126. The word line interconnect structure 126 electrically couples the gate 116 to the word line conductive structure 128 in the memory array 102. The word line interconnect structure 126 may include vias, pillars, struts, and / or another type of elongated structure in the z-direction. The word line interconnect structure 126 may be located perpendicularly in the z-direction between the gate 116 and the word line conductive structure 128. The word line conductive structure 128 may extend in the y-direction of the semiconductor device 100, substantially parallel to the hydrogen barrier column 120. The word line conductive structure 128 may include a metallization layer, trenches, conductive traces, and / or another type of elongated conductive structure.

[0036] In some embodiments, the gates 116 of transistor structures 106 included in the same y-direction column of the memory array 102 may be electrically coupled to the same word line conductor structure 128. The bit line conductor structure 122 and the word line conductor structure 128 may each be coupled to circuitry, including control circuitry, read buffers, write buffers, and / or other types of circuitry in the semiconductor device 100.

[0037] As mentioned above, Figure 1 This is provided as an example. Other examples are available. Figure 1 The differences described in [the original text].

[0038] Figure 2A and Figure 2B This is a figure of an exemplary embodiment 200 of the memory cell structure 104 described herein. Figure 2A This is a top view of an exemplary embodiment 200 of the memory cell structure 104 and Figure 2B It is along Figure 2A The sectional view of line AA in the diagram.

[0039] like Figure 2A As shown, the gate 116 of the transistor structure 106 of the memory cell structure 104 may laterally surround the channel layer 114. The gate dielectric layer 118 of the transistor structure 106 of the memory cell structure 104 may also laterally surround the channel layer 114 and may be included between the channel layer 114 and the gate 116. A hydrogen barrier column 120 may be included along and laterally adjacent to the opposite side of the gate 116. In some embodiments, a connection segment 120a is laterally adjacent to the end of the gate 116 and connects to the hydrogen barrier column 120 included along the opposite side of the gate 116.

[0040] like Figure 2BAs shown, channel layer 114 extends vertically between source / drain (110 and 112). Storage structure 108 is located vertically below transistor structure 106 and is electrically coupled to source / drain 110 of transistor structure 106 via source / drain interconnect structure 124.

[0041] The source / drain (110 and 112) may each include polysilicon, indium tin oxide (ITO), copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W) and / or aluminum (Al), tantalum nitride (TaN), titanium nitride (TiN) and / or another electrically conductive material.

[0042] Channel layer 114 may comprise a semiconductor material, such as silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), a group III-V semiconductor compound, and / or another semiconductor material. Additionally and / or alternatively, channel layer 114 may comprise an oxide semiconductor material. Therefore, transistor structure 106 may be referred to as an oxide-semiconductor field-effect transistor (OSFET). In some embodiments, channel layer 114 comprises an n-type oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO or IGZO), zinc oxide (ZnO), indium oxide (In... x O y Examples of suitable materials include In₂O₃ and tin dioxide (SnO₂). In some embodiments, channel layer 114 comprises p-type oxide semiconductor materials, such as nickel oxide (NiO) and copper oxide (Cu). x O, such as Cu2O), copper aluminum oxide (CuAlO) x For example, CuAlO2), copper gallium oxide (CuGaO) x For example, CuGaO2), copper indium oxide (CuInO) x For example, CuInO2), strontium copper oxide (SrCu) x O y For example, SrCu2O2 and / or tin oxide (SnO).

[0043] The gate 116 may include polysilicon, indium tin oxide (ITO), copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W) and / or aluminum (Al), tantalum nitride (TaN), titanium nitride (TiN) and / or another electrically conductive material.

[0044] The gate dielectric layer 118 may include one or more dielectric materials. In some embodiments, the gate dielectric layer 118 includes one or more low-k dielectric materials (e.g., dielectric materials having a dielectric constant of about 3.9 or less), such as silicon oxide (SiO2).x Examples of high-k dielectric materials include silicon nitride (SiO2), undoped silicate glass (USG), and / or fluoride-doped silicate glass (FSG). In some embodiments, the gate dielectric layer 118 comprises one or more high-k dielectric materials (e.g., dielectric materials having a dielectric constant greater than about 3.9), such as silicon nitride (SiO2). x N y For example, Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO) x For example, HfO2), aluminum oxide (Al) x O y For example, Al2O3), lanthanum oxide (La x O y For example, La2O3), zirconium oxide (ZrO2), etc. x For example, ZrO2) and / or yttrium oxide (Y) x O y For example, Y2O3, etc.

[0045] Hydrogen barrier columns 120 may each comprise one or more materials that inhibit hydrogen (H) diffusion into and / or through the hydrogen barrier columns 120. Such materials may have strong chemical bonds (e.g., covalent and / or ionic bonds) between their elements, providing a stable barrier for hydrogen diffusion. Additionally and / or alternatively, such materials may have high density, low porosity, and / or a crystalline structure, which can result in low hydrogen permeability. Examples of materials used for hydrogen barrier columns 120 include silicon nitride (Si). x N y For example, Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3) x O y Examples include Al2O3, silicon carbonitride (SiCN), silicon carbonitride (SiCON), aluminum nitride (AlN), aluminum oxynitride (AlON), another nitride-containing dielectric material, and / or another oxide-containing dielectric material.

[0046] As mentioned above, providing Figure 2A and Figure 2B As an example. Other examples may be found related to... Figure 2A and Figure 2B The differences mentioned.

[0047] Figure 3A and Figure 3B This is a figure of an exemplary embodiment 300 of the memory cell structure 104 described herein. Figure 3A This is a top view of an exemplary embodiment 300 of the memory cell structure 104 and Figure 3BIt is along Figure 3A The sectional view of line BB in the middle.

[0048] like Figure 3A and Figure 3B As shown, an exemplary embodiment 300 of the memory cell structure 104 is... Figure 2A and Figure 2B The exemplary embodiment 200 of the memory cell structure 104 shown is similar. However, in the exemplary embodiment 300 of the memory cell structure 104, the transistor structure 106 includes multiple layer channel layers 114. Figure 3A As shown, in an exemplary embodiment 300 of the memory cell structure 104, the channel layer 114 of the transistor structure 106 includes a core segment 302a and an outer segment 302b surrounding the core segment 302a. The outer segment 302b is located between the core segment 302a and the gate dielectric layer 118. Figure 3B As shown, both the core section 302a and the outer section 302b can extend completely and continuously between the source / drain (110 and 112) in the z-direction. Therefore, both the core section 302a and the outer section 302b can physically contact the source / drain (110 and 112) at opposite ends of the core section 302a and the opposite ends of the outer section 302b.

[0049] The core segment 302a and the outer segment 302b may comprise different materials. For example, the core segment 302a and the outer segment 302b may comprise different semiconductor materials, different oxide semiconductor materials, and / or different material compositions and / or other examples. In some embodiments, the core segment 302a comprises a first semiconductor material having a first doping concentration, and the outer segment 302b comprises a second semiconductor material having a second doping concentration different from the first doping concentration (e.g., the same semiconductor material as the first semiconductor material or a different semiconductor material). In some embodiments, the core segment 302a comprises a first oxide semiconductor material having a first doping concentration, and the outer segment 302b comprises a second oxide semiconductor material having a second doping concentration different from the first doping concentration (e.g., the same oxide semiconductor material as the first oxide semiconductor material or a different oxide semiconductor material).

[0050] In some embodiments, the oxide semiconductor material of the core segment 302a and the outer segment 302b may include the same dopant, such as indium (In). In some embodiments, the oxide semiconductor material of the core segment 302a and the outer segment 302b may include different dopants. The second doping concentration in the outer segment 302b may be greater than the first doping concentration in the core segment 302a to provide better carrier transport performance in the outer segment 302b (and thus enhanced gate control), while the lower doping concentration in the core segment 302a provides enhanced resistance to threshold voltage offset in the core segment 302a. In some embodiments, the first doping concentration in the core segment 302a includes approximately 1 × 10⁻⁶ per cubic centimeter. 14 From one dopant atom (e.g., indium atom) to approximately 1 × 10⁻⁶ per cubic centimeter 18 Within the range of dopant atoms, the second doping concentration in the outer segment 302b includes approximately 1 × 10⁻⁶ per cubic centimeter. 17 From one dopant atom (e.g., indium atom) to approximately 1 × 10⁻⁶ per cubic centimeter 21 Within the range of dopant atoms. However, other values ​​and ranges of the first doping concentration in the core section 302a and the second doping concentration in the outer section 302b are also within the scope of this disclosure.

[0051] As mentioned above, providing Figure 3A and Figure 3B As an example. Other examples can be related to... Figure 3A and Figure 3B The differences mentioned.

[0052] Figure 4A-4P This is a diagram of an exemplary embodiment 400 of a memory array 102 forming the semiconductor device 100 described herein. The memory array 102 may be formed to include a plurality of memory cell structures 104 and hydrogen barrier columns 120 to prevent, minimize, and / or otherwise reduce hydrogen diffusion in the memory cell structures 104. In some embodiments, combined with Figure 4A-4P One or more of the semiconductor processing operations can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, and / or ion implantation tools.

[0053] Figure 4A A perspective view of the semiconductor device 100 is shown. Figure 4B It shows along Figure 4A A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4A and Figure 4BAs shown, various dielectric layers can be formed in the semiconductor device 100. For example, an etch stop layer (ESL) 402 can be formed, an interlayer dielectric (ILD) layer 404 can be formed on and / or on the ESL 402, another ESL 406 can be formed on and / or on the ILD layer 404, and another ILD layer 408 can be formed on and / or on the ILD layer 404. The ESL 402, 406 and ILD layers 404, 408 can be formed in the back-end region (or interconnect layer) of the semiconductor device 100 and can therefore be referred to as the back-end dielectric layer. The ESL 402, 406 and ILD layers 404, 408 can each extend in the x and y directions and can be arranged in the z direction. The ESL 402, 406 and ILD layers 404, 408 can each include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluorine-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0054] The deposition tools can be used to deposit ESL 402, 406 and ILD layers 404, 408 using one or more deposition techniques, such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. ESL 402, 406 and ILD layers 404, 408 can be deposited in one or more deposition operations. In some embodiments, planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization (CMP)) after the deposition of ESL 402, 406 and ILD layers 404, 408 to planarize the ESL 402, 406 and ILD layers 404, 408.

[0055] like Figure 4A and Figure 4BAs further shown, the storage structure 108 of the memory cell structure 104 in the memory array 102 can be formed through the ESL 406 and into the ILD layer 404. For example, ESL 402, ILD layer 404 and ESL 406 can be formed, recesses can be formed in and / or through the ESL 406 and ILD layer 404 (e.g., the recess stops on the ESL 402), and the storage structure 108 can be formed in the recesses. The ILD layer 408 can be formed after the storage structure 108 is formed.

[0056] In some embodiments, the pattern in the photoresist layer is used to etch ESL 406 and ILD layer 404 to form recesses in ESL 406 and ILD layer 404. In these embodiments, deposition tools can be used to form the photoresist layer on ESL 406 (e.g., using spin coating and / or another suitable deposition technique). Exposure tools can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tools can be used to develop and remove portions of the photoresist layer to reveal the exposed pattern. Etching tools can be used to etch ESL 406 and ILD layer 404 based on the pattern to form recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, photoresist removal tools can be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-based etching of the ESL 406 and ILD layer 404 to form the depression.

[0057] In some embodiments, forming the storage structure 108 in the recess includes forming a capacitor structure in the ILD layer 404. The capacitor structure may include a thin-film capacitor structure (e.g., a planar capacitor structure), a DTC structure, and / or another type of capacitor structure. The capacitor structure may have a metal-insulator-metal (MIM) arrangement, wherein the bottom electrode and the top electrode are separated by an insulating layer. Additionally and / or alternatively, forming the storage structure 108 may include forming a phase change material structure, forming a resistive structure, forming a ferroelectric structure, and / or forming another type of storage structure.

[0058] like Figure 4A and Figure 4BAs further shown, the word line conductive structure 128 of the memory array 102 may be formed in the ILD layer 408. Therefore, the word line conductive structure 128 may be formed on the storage structure 108 of the memory cell structure 104 of the memory array 102. Forming the word line conductive structure 128 may include forming a recess in the ILD layer 408 and forming the word line conductive structure 128 in the recess. In some embodiments, one or more liners are first formed in the recess, and the word line conductive structure 128 is formed on the liners. The liners may include adhesive liners (e.g., liners included to facilitate adhesion between the word line conductive structure 128 and surrounding layers such as the ILD layer 408 and / or ESL 406), barrier layers (e.g., layers included to reduce or minimize material diffusion from the word line conductive structure 128 into, for example, the surrounding layers of the ILD layer 408 and / or ESL 406), and / or another type of liner. Examples of one or more materials used for linings include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0059] In some embodiments, the ILD layer 408 is etched using an etching tool to form a recess (e.g., a trench) in which the word line conductive structure 128 will be formed. The recess may extend in the y-direction of the semiconductor device 100. Deposition tools may be used to deposit the liner using ALD technology, CVD technology, and / or another type of conformal deposition technology. Deposition tools may be used to deposit the word line conductive structure 128 using CVD technology, PVD technology, ALD technology, electroplating technology, and / or another suitable deposition technology. The word line conductive structure 128 may extend in the y-direction of the semiconductor device 100 and may be aligned in the x-direction of the semiconductor device 100. In some embodiments, a seed layer is first deposited on the liner and the word line conductive structure 128 is deposited on the seed layer. In some embodiments, after the formation of the word line conductive structure 128, a planarization operation (e.g., a CMP operation) is performed using a planarization tool to planarize the word line conductive structure 128. After the planarization operation, the top surface of the word line conductive structure 128 may be substantially coplanar with the top surface of the ILD layer 408.

[0060] Figure 4C Another perspective view of the semiconductor device 100 is shown and Figure 4D It shows along Figure 4C A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4C and Figure 4DAs shown, additional dielectric layers (e.g., additional back-end dielectric layers) may be formed in the semiconductor device 100. For example, another ESL 410 may be formed on the ILD layer 408 and the word line conductive structure 128, another ILD layer 412 may be formed on and / or on the ESL 410, and another ESL 414 may be formed on and / or on the ILD layer 412. ESL 410, 414 and ILD layer 412 may each extend in the x and y directions and may be arranged in the z direction. ESL 410, 414 and ILD layer 412 may each include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluorine-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0061] Deposition tools can be used to deposit ESL 410, 414, and ILD layers 412 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). ESL 410, 414, and ILD layers 412 can be deposited in one or more deposition operations. In some embodiments, after depositing ESL 410, 414, and ILD layers 412, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize the ESL 410, 414, and ILD layers 412.

[0062] like Figure 4C and Figure 4D As further shown, the source / drain interconnect structure 124 may be formed through ESL 414, ILD layer 412, ESL 410, and ILD layer 408, such that the source / drain interconnect structure 124 rests on the storage structure 108. In some embodiments, a source / drain interconnect structure 124 is formed in each storage structure 108 in the memory array 102. In some embodiments, a plurality of source / drain interconnect structures 124 are formed in the storage structures 108 in the memory array 102.

[0063] Forming the source / drain interconnect structure 124 may include forming a recess in and / or through the ESL 414, ILD layer 412, ESL 410, and ILD layer 408, and forming the source / drain interconnect structure 124 within the recess. In some embodiments, the recess is formed by etching through the ESL 414, ILD layer 412, ESL 410, and ILD layer 408 using a pattern in the photoresist layer. In these embodiments, a deposition tool may be used to form a photoresist layer on the ESL 414 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tools can be used to etch patterned etch through ESL 414, ILD layer 412, ESL 410, and ILD layer 408 to form recesses. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for patterned recess formation.

[0064] In some embodiments, one or more liners are first formed on the recess, and a source / drain interconnect structure 124 is formed on the liners. The liners may include an adhesion liner (e.g., including a liner to facilitate adhesion between the source / drain interconnect structure 124 and surrounding layers such as ESL 414, ILD layer 412, ESL 410, and / or ILD layer 408), a barrier layer (e.g., a layer included to reduce or minimize diffusion from the source / drain interconnect structure 124 to surrounding layers such as ESL 414, ILD layer 412, ESL 410, and / or ILD layer 408), and / or another type of liner. Examples of materials used for the liners include tantalum nitride (TaN) and / or titanium nitride (TiN). Deposition tools may be used to deposit the liner in the recess using ALD technology, CVD technology, and / or another type of conformal deposition technology.

[0065] Deposition tools can be used to deposit the source / drain interconnect structure 124 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The source / drain interconnect structure 124 may extend in the z-direction of the semiconductor device 100 and may be positioned on the storage structure 108. In some embodiments, a seed layer is first deposited on the liner, and the source / drain interconnect structure 124 is deposited on the seed layer. In some embodiments, after the formation of the source / drain interconnect structure 124, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the source / drain interconnect structure 124. After the planarization operation, the top surface of the source / drain interconnect structure 124 may be substantially coplanar with the top surface of the ESL 414.

[0066] Figure 4E Another perspective view of the semiconductor device 100 is shown and Figure 4F It shows along Figure 4D A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4E and Figure 4F As shown, additional dielectric layers (e.g., additional back-end dielectric layers) may be formed in the semiconductor device 100. For example, another ILD layer 416 may be formed on and / or on ESL 414, and another ESL 418 may be formed on and / or on ILD layer 416. ILD layer 416 and ESL 418 may each extend in the x and y directions and may be arranged in the z direction. ILD layer 416 and ESL 418 may each include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluorine-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0067] Deposition tools can be used to deposit ILD layers 416 and ESL 418 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). ILD layers 416 and ESL 418 can be deposited in one or more deposition operations. In some embodiments, after depositing ILD layers 416 and ESL 418, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize ILD layers 416 and ESL 418.

[0068] like Figure 4E and Figure 4FAs further shown, the source / drain 110 of the transistor structure 106 of the memory cell structure 104 may be formed through the ILD layer 416 and ESL 418, such that the source / drain 110 rests on the source / drain interconnect structure 124. Forming the source / drain 110 may include forming a recess in and / or through the ILD layer 416 and ESL 418 and forming the source / drain 110 in the recess. In some embodiments, a pattern in the photoresist layer is used to etch through the ILD layer 416 and ESL 418 to form the recess. In these embodiments, a deposition tool may be used to form a photoresist layer on the ESL 418 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tools can be used to etch through ILD layers 416 and ESL 418 in a pattern-based manner to form recesses. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based recess formation.

[0069] In some embodiments, one or more liners are formed on the recess and source / drain electrodes 110 are formed on the liners. The liners may include adhesive liners (e.g., liners included to facilitate adhesion between the source / drain electrode 110 and surrounding layers such as ILD layer 416 and / or ESL 418), barrier layers (e.g., layers included to reduce or minimize diffusion from the source / drain electrode 110 to surrounding layers such as ILD layer 416 and / or ESL 418), and / or another type of liner. Examples of materials used for the liners include tantalum nitride (TaN) and / or titanium nitride (TiN). Deposition tools may be used to deposit the liners in the recess using ALD technology, CVD technology, and / or another type of conformal deposition technology.

[0070] Deposition tools can be used to deposit the source / drain 110 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the liner, and the source / drain 110 is deposited on the seed layer. In some embodiments, after the formation of the source / drain 110, a planarization operation (e.g., CMP operation) is performed using planarization tools to planarize the source / drain 110. After the planarization operation, the top surface of the source / drain 110 may be substantially coplanar with the top surface of the ESL 418.

[0071] Figure 4G Another perspective view of the semiconductor device 100 is shown and Figure 4H It shows along Figure 4G A cross-sectional view of line DD (e.g., along the x-direction). For example... Figure 4G and Figure 4H As shown, an additional dielectric layer (e.g., an additional back-end dielectric layer) may be formed in the semiconductor device 100. For example, another ILD layer 420 may be formed on and / or on the ESL 418. The ILD layer 420 may extend in both the x and y directions. The ILD layer 420 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0072] Deposition tools can be used to deposit the ILD layer 420 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). The ILD layer 420 may be deposited in one or more deposition operations. In some embodiments, after the ILD layer 420 is deposited, a planarization tool may be used to perform a planarization operation (e.g., a CMP operation) to planarize the ILD layer 420.

[0073] like Figure 4G and Figure 4HAs further shown, the word-line interconnect structure 126 of the memory cell structure 104 may be formed through the ILD layer 420, through the ESL 418, through the ILD layer 416, through the ESL 414, through the ILD layer 412 and / or through the ESL 410, such that the word-line interconnect structure 126 rests on the word-line conductive structure 128. Forming the word-line interconnect structure 126 may include forming recesses in and / or through the ILD layers 420, ESL 418, ILD layers 416, ESL 414, ILD layers 412 and / or ESL 410, and forming the word-line interconnect structure 126 in the recesses. In some embodiments, patterning in the photoresist layer is used to etch through ILD layers 420, ESL 418, ILD layers 416, ESL 414, ILD layers 412, and / or ESL 410 to form a recess. In these embodiments, deposition tools can be used to form the photoresist layer on ILD layer 420 (e.g., using spin coating and / or another suitable deposition technique). Exposure tools can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tools can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tools can be used to etch through ILD layers 420, ESL 418, ILD layers 416, ESL 414, ILD layers 412, and / or ESL 410 based on the pattern to form a recess. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some implementations, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based recess formation.

[0074] In some embodiments, one or more liners are first formed on the recess, and word line interconnect structures 126 are formed on the liners. The liners may include adhesive liners (e.g., liners included to facilitate adhesion between the word line interconnect structures 126 and surrounding layers such as ILD layers 420, ESL 418, ILD layers 416, ESL 414, ILD layers 412 and / or ESL 410), barrier layers (e.g., layers included to reduce or minimize diffusion from the word line interconnect structures 126 to surrounding layers such as ILD layers 420, ESL 418, ILD layers 416, ESL 414, ILD layers 412 and / or ESL 410), and / or another type of liner. Examples of materials used for the liners include tantalum nitride (TaN) and / or titanium nitride (TiN). Deposition tools may be used to deposit the liners in the recess using ALD technology, CVD technology, and / or another type of conformal deposition technology.

[0075] Deposition tools can be used to deposit the word-line interconnect structure 126 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the liner, and the word-line interconnect structure 126 is deposited on the seed layer. In some embodiments, after forming the word-line interconnect structure 126, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the word-line interconnect structure 126. After the planarization operation, the top surface of the word-line interconnect structure 126 may be substantially coplanar with the top surface of the ILD layer 420.

[0076] Figure 4I Another perspective view of the semiconductor device 100 is shown and Figure 4J It shows along Figure 4I A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4I and Figure 4J As shown, a hydrogen barrier array 120 may be formed above the ILD layer 420. A channel spacer 422 may also be formed above the ILD layer 420. The gate 116 of the transistor structure 106 of the memory cell structure 104 may be formed around the channel spacer 422. The channel spacer 422 may be formed as a temporary structure to reserve space for the channel layer 114 to be formed of the transistor structure 106. This allows the gate 116 to be formed around the channel spacer 422, allows the channel spacer 422 to be removed after the gate 116 is formed, and allows the channel layer 114 to be formed in the opening through the gate 116 previously occupied by the channel spacer 422. Figure 5A-5K An example process for forming the hydrogen barrier column 120, the gate 116, and the channel spacer 422 is shown and described.

[0077] The channel spacer wall 422 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric material may be silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), a low-dielectric-constant dielectric material, a high-dielectric-constant dielectric material, and / or another suitable dielectric material. Deposition tools may be used to deposit channel spacers 422 using PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique. Channel spacers may be formed above the source / drain 110 of the transistor structure 106.

[0078] In some embodiments, the channel gap wall 422 may be deposited as a blanket layer, patterned, and then etched to form the channel gap wall 422. In some embodiments, after depositing the channel gap wall 422, a planarization tool may be used to perform a planarization operation (e.g., a CMP operation) to planarize the channel gap wall 422.

[0079] Deposition tools can be used to deposit the hydrogen barrier column 120 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The hydrogen barrier column 120 can be deposited in one or more deposition operations. In some embodiments, the hydrogen barrier column 120 can be deposited as a blanket layer, patterned, and then etched to form the hydrogen barrier column 120. In some embodiments, after depositing the hydrogen barrier column 120, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the hydrogen barrier column 120.

[0080] Deposition tools can be used to deposit the gate 116 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The hydrogen barrier column 120 and channel spacer 422 define regions or areas in which the gate 116 is deposited. The gate 116 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, followed by the deposition of the gate 116 on the seed layer. In some embodiments, after the gate 116 is deposited, a planarization tool is used to perform a planarization operation (e.g., CMP operation) to planarize the gate 116.

[0081] Figure 4K Another perspective view of the semiconductor device 100 is shown and Figure 4L It shows along Figure 4K A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4K and Figure 4LAs shown, another back-end dielectric layer, such as ESL 424, may be formed over the gate 116, the hydrogen barrier column 120, and / or the channel spacer 422. ESL 424 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ESL 424 can be deposited using silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), low-dielectric-constant dielectric materials, high-dielectric-constant dielectric materials, and / or other suitable dielectric materials. Deposition tools can be used to deposit ESL 424 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. ESL 424 can be deposited in one or more deposition operations. In some embodiments, after ESL 424 deposition, a planarization tool can be used to perform a planarization operation (e.g., CMP) to planarize the ESL 424.

[0082] like Figure 4K and Figure 4L As further shown, an opening can be formed over the channel spacer 422 via ESL 424, and the channel spacer 422 can be removed through the opening after the formation of the gate 116 and after the formation of the hydrogen barrier array 120. Removal of the channel spacer 422 results in the formation of an opening through the gate 116 over the source / drain 110. The channel spacer 422 can be etched using an etching tool to remove it from the semiconductor device 100. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation.

[0083] like Figure 4K and Figure 4L As further shown, the channel layer 114 and the gate dielectric layer 118 may be formed in the opening through the gate 116 previously occupied by the channel spacer wall 422. In some embodiments, the gate dielectric layer 118 may be formed on the sidewall of the opening, and the channel layer 114 may fill the opening. In some embodiments, the gate dielectric layer 118 may be formed on the sidewall of the opening, the outer segment 302b of the channel layer 114 may be formed on the gate dielectric layer 118 on the sidewall of the opening, and the core segment 302a of the channel layer 302 may fill the remaining area in the opening.

[0084] Deposition tools can be used to deposit the gate dielectric layer 118 using conformal deposition techniques (such as ALD and / or CVD techniques). Deposition tools can be used to deposit the channel layer 114 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The channel layer 114 can be deposited in one or more deposition operations. For example, an outer segment 302b can be deposited in a first deposition operation, and a core segment 302a can be deposited in a second deposition operation. In some embodiments, after depositing the gate dielectric layer 118 and the channel layer 114, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the gate dielectric layer 118 and the channel layer 114.

[0085] Figure 4M Another perspective view of the semiconductor device 100 is shown and Figure 4N It shows along Figure 4M A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4M and Figure 4N As shown, an additional dielectric layer (e.g., an additional back-end dielectric layer) may be formed in the semiconductor device 100. For example, another ILD layer 426 may be formed on and / or on the ESL 424. The ILD layer 426 may extend in both the x and y directions. The ILD layer 426 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0086] Deposition tools can be used to deposit ILD layer 426 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). ILD layer 426 may be deposited in one or more deposition operations. In some embodiments, after depositing ILD layer 426, a planarization tool may be used to perform a planarization operation (e.g., CMP operation) to planarize ILD layer 426.

[0087] like Figure 4M and Figure 4NAs further shown, the source / drain 112 of the transistor structure 106 of the memory cell structure 104 can be formed through the ILD layer 426, such that the source / drain 112 rests on the channel layer 114 of the transistor structure 106. Forming the source / drain 112 may include forming a recess in and / or through the ILD layer 426, and forming the source / drain 112 in the recess. In some embodiments, a pattern in a photoresist layer is used to etch through the ILD layer 426 to form the recess. In these embodiments, a deposition tool may be used to form a photoresist layer on the ILD layer 426 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch through the ILD layer 426 based on the pattern to form the recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative to pattern-based recess formation.

[0088] In some embodiments, one or more liners are first formed on the recess, and source / drain electrodes 112 are formed on the liners. The liners may include adhesive liners (e.g., liners included to facilitate adhesion between the source / drain electrodes 112 and surrounding layers such as ILD layer 426), barrier layers (e.g., layers included to reduce or minimize diffusion from the source / drain electrodes 112 to, for example, the surrounding layers of ILD layer 426), and / or other types of liners. Examples of materials used for the liners include tantalum nitride (TaN) and / or titanium nitride (TiN). Deposition tools may be used to deposit the liners in the recess using ALD technology, CVD technology, and / or another type of conformal deposition technology.

[0089] Deposition tools can be used to deposit the source / drain 112 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the liner, and the source / drain 112 is deposited on the seed layer. In some embodiments, after the formation of the source / drain 110, a planarization tool is used to perform a planarization operation (e.g., CMP) to planarize the source / drain 112. After the planarization operation, the top surface of the source / drain 112 may be substantially coplanar with the top surface of the ILD layer 426.

[0090] Figure 4O Another perspective view of the semiconductor device 100 is shown and Figure 4P It shows along Figure 4O A cross-sectional view along line CC (e.g., along the x-direction). For example... Figure 4O and Figure 4P As shown, an additional dielectric layer (e.g., an additional back-end dielectric layer) may be formed in the semiconductor device 100. For example, another ILD layer 428 may be formed on and / or on ILD layer 426. ILD layer 426 may extend in the x and y directions. ILD layer 426 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), low dielectric constant dielectric material, high dielectric constant dielectric material and / or another suitable dielectric material.

[0091] Deposition tools can be used to deposit ILD layer 428 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). ILD layer 428 may be deposited in one or more deposition operations. In some embodiments, after depositing ILD layer 428, a planarization tool may be used to perform a planarization operation (e.g., CMP) to planarize ILD layer 428.

[0092] like Figure 4O and Figure 4P As further shown, the bit line conductive structure 122 of the memory array 102 can be formed through the ILD layer 428, such that the bit line conductive structure 122 rests on the source / drain 112 of the transistor structure 106 of the memory cell structure 104. The bit line conductive structure 122 can extend in the x direction and can be arranged in the y direction.

[0093] Forming the bitline conductive structure 122 may include forming a recess in and / or through the ILD layer 428 and forming the bitline conductive structure 122 within the recess. In some embodiments, a pattern in a photoresist layer is used to etch through the ILD layer 428 to form the recess. In these embodiments, a deposition tool may be used to form a photoresist layer on the ILD layer 428 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch through the ILD layer 428 based on the pattern to form the recess. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-based recess formation.

[0094] In some embodiments, one or more liners are first formed on the recess, and bitline conductive structures 122 are formed on the liners. The liners may include adhesive liners (e.g., liners included to facilitate adhesion between the bitline conductive structures 122 and surrounding layers such as ILD layer 428), barrier layers (e.g., layers included to reduce or minimize diffusion from the bitline conductive structures 122 to, for example, the surrounding layers of ILD layer 428), and / or other types of liners. Examples of materials used for the liners include tantalum nitride (TaN) and / or titanium nitride (TiN). Deposition tools may be used to deposit the liners in the recess using ALD technology, CVD technology, and / or another type of conformal deposition technology.

[0095] Deposition tools can be used to deposit the bitline conductive structure 122 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the liner, and the bitline conductive structure 122 is deposited on the seed layer. In some embodiments, after the bitline conductive structure 122 is formed, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the bitline conductive structure 122. After the planarization operation, the top surface of the bitline conductive structure 122 may be substantially coplanar with the top surface of the ILD layer 428.

[0096] As mentioned above, providing Figure 4A-4P As an example. Other examples may be found related to... Figure 4A-4P The differences mentioned.

[0097] Figure 5A-5KThis is a diagram of an exemplary embodiment 500 of forming a hydrogen barrier column 120 in a memory array 102 of a semiconductor device 100 as described herein. In some embodiments, combined with Figure 5A-5K One or more of the semiconductor processing operations can be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, and / or ion implantation tools. In some embodiments, combined with Figure 5A-5K The one or more semiconductor processing operations may be performed as part of the process of forming the memory array 102 of the semiconductor device 100, such as in combination with Figure 4A-4P As shown and described.

[0098] like Figure 5A As shown in the perspective view, the combination can be performed. Figures 4A-4F The one or more processing operations are used to form the back dielectric layer (e.g., 402-418) of the semiconductor device 100, the storage structure 108 of the memory cell structure 104, the source / drain 110, the word line conductive structure 128, and the source / drain interconnect structure 124.

[0099] like Figure 5B As shown in the perspective view, an ILD layer 420 may be formed on and / or on an ESL 418, and a dielectric layer 502 may be formed on and / or on an ILD layer 420. The dielectric layer 502 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric layer 502 can be made of silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), low-dielectric-constant dielectric materials, high-dielectric-constant dielectric materials, and / or another suitable dielectric material. Deposition tools can be used to deposit the dielectric layer 502 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). The dielectric layer 502 can be deposited in one or more deposition operations. In some embodiments, after depositing the dielectric layer 502, a planarization tool can be used to perform a planarization operation (e.g., CMP) to planarize the dielectric layer 502.

[0100] like Figure 5CAs shown in the perspective view, the dielectric layer 502 is patterned and etched to define channel spacer walls 422 from the dielectric layer 502. In some embodiments, the dielectric layer 502 is etched using a pattern in a photoresist layer to form the channel spacer walls 422. In these embodiments, deposition tools can be used to form a photoresist layer on the dielectric layer 502 (e.g., using spin coating and / or another suitable deposition technique). Exposure tools can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tools can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tools can be used to etch the dielectric layer 502 based on the pattern to form the channel spacer walls 422. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, photoresist removal tools can be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming channel spacer walls 422 for etching dielectric layer 502.

[0101] like Figure 5D As shown in the perspective view, another dielectric layer 504 can be formed above the ILD layer 420 and the channel spacer 422, such that the channel spacer 422 is covered by the dielectric layer 504. The dielectric layer 504 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric material can be silicon oxynitride (SiON), undoped silicate glass (USG), fluoride-doped silicate glass (FSG), a low-dielectric-constant dielectric material, a high-dielectric-constant dielectric material, and / or another suitable dielectric material. In some embodiments, the material of the dielectric layer 502 may be different from the material of the channel spacer 422, so that the dielectric layer 504 can be subsequently removed without removing (or with minimal removal) the channel spacer 422.

[0102] Deposition tools can be used to deposit dielectric layer 504 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). Dielectric layer 504 can be deposited in one or more deposition operations. In some embodiments, after depositing dielectric layer 504, planarization tools can be used to perform a planarization operation (e.g., CMP operation) to planarize dielectric layer 504.

[0103] like Figure 5EAs shown in the perspective view, dielectric layer 504 can be patterned and etched to define gate spacer 506. Gate spacer 506 can be included above source / drain 110 and channel spacer 422. Gate spacer 506 may include temporary structures occupying the region in which gate 116 will be formed after hydrogen barrier column 120 is formed. In this way, gate spacer 506 also defines the space or region in which hydrogen barrier column 120 will be formed.

[0104] In some embodiments, a pattern in the photoresist layer is used to etch the dielectric layer 504 to form the gate spacer 506. In these embodiments, a deposition tool can be used to form the photoresist layer on the dielectric layer 504 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 504 based on the pattern to define the gate spacer 506. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). For example, a plasma-based etching operation can be performed, where chamber pressure, temperature, plasma bias, and / or another parameter are selected to control the directionality of the etching, thereby achieving vertical etching. In this way, the sidewalls of the trench defined between adjacent gate spacer walls 506 are substantially vertical. In some embodiments, a hard mask layer is used as an alternative technique to etching the dielectric layer 504 to form the gate spacer walls 506 based on a pattern.

[0105] like Figure 5F As shown in the perspective view, a hydrogen barrier layer 508 may be formed in the space between the gate spacer walls 506 (e.g., a trench extending in the y-direction). Therefore, the hydrogen barrier layer 508 may be formed along the sidewalls and top surface of the gate spacer walls 506. Deposition tools may be used to deposit the hydrogen barrier layer 508 using one or more deposition techniques (e.g., PVD, ALD, CVD, oxidation, and / or another suitable deposition technique). The hydrogen barrier layer 508 may be deposited in one or more deposition operations.

[0106] like Figure 5GAs shown in the perspective view, the hydrogen barrier layer 508 can be planarized to define a hydrogen barrier array 120 on opposite sides of the gate spacer wall 506. A planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the hydrogen barrier layer 508 to define the hydrogen barrier array 120. In some embodiments, the planarization operation stops at the gate spacer wall 506. In some embodiments, the planarization operation removes material from the gate spacer wall 506 such that the top surface of the gate spacer wall 506 is substantially flat and coplanar with the top of the hydrogen barrier array 120.

[0107] like Figure 5H As shown in the perspective view, after planarizing the hydrogen barrier layer 508, gate spacer 506 is removed to define the hydrogen barrier array 120. Removal of the gate spacer 506 exposes the channel spacer 422 and the area surrounding the channel spacer 422 between the hydrogen barrier arrays 120. The gate spacer 506 can be etched using an etching tool to remove it from the semiconductor device 100. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. An etchant can be used to remove the gate spacer 506, selectively etching the gate spacer 506 while removing minimal material from the hydrogen barrier array 120 and minimal material from the channel spacer 422, or even not removing the channel spacer 422 at all.

[0108] like Figure 5I As shown in the perspective view, a gate 116 may be formed around the channel spacer 422 and between the hydrogen barrier columns 120 in the region previously occupied by the gate spacer 506. In some embodiments, the gate 116 is deposited as a blanket layer, and the blanket layer and the hydrogen barrier columns 120 are planarized (e.g., using a planarization tool) during a CMP operation and / or another type of planarization operation to define the gate 116. The CMP operation may be stopped at the channel spacer 422, such that the top of the channel spacer 422 is exposed through the gate 116.

[0109] like Figure 5J As shown in the perspective view, the channel spacer 422 is removed after the gate 116 is formed, as in the combination Figure 4K and Figure 4L The removal of the channel spacer 422 results in the formation of an opening 510 above the source / drain 110 of the transistor structure 106 of the memory cell structure 104. Additionally, according to some embodiments, the ILD layer 420 directly below the channel spacer 422 is also removed, exposing the source / drain 110 to the opening 510, as described above. Figure 5J As shown.

[0110] like Figure 5KAs shown in the perspective view, the gate dielectric layer 118 and the channel layer 114 may be formed in the opening 510 above the source / drain 110, as combined Figure 4K and Figure 4L As mentioned above.

[0111] As mentioned above, providing Figure 5A-5K As an example. Other examples may be found related to... Figure 5A-5K The differences mentioned.

[0112] Figure 6 This is a diagram illustrating example 600 of temperature offset instabilities in various memory cell structures. Temperature offset instabilities (e.g., PTBI, NTBI) are shown as a function of threshold voltage offset 602 and stress time 604. Data point 606 corresponds to the threshold voltage offset 602 of the memory cell structure 104 including hydrogen barrier column 120 described herein at stress time 604, and data point 608 corresponds to the threshold voltage offset 602 of the memory cell structure having hydrogen barrier column 120 at stress time 604.

[0113] like Figure 6 As shown at data point 608, without the hydrogen barrier column 120, the memory cell structure experiences a significant (negative) threshold voltage shift 602 as the stress time 604 increases. This occurs because, without the hydrogen barrier column 120, the carrier dose in the channel layer of the memory cell structure increases due to exposure to hydrogen.

[0114] like Figure 6 As shown at data point 606, in the absence of the hydrogen barrier column 120, the memory cell structure 104 described herein experiences a minimum to no-threshold voltage offset 602 as the stress time 604 on the memory cell structure 104 increases. This is because the hydrogen barrier column 120 prevents, minimizes, and / or otherwise reduces the exposure of the channel layer 114 to hydrogen, which allows for a consistent and uniform carrier dose in the channel layer 114 during the stress time 604 of the memory cell structure 104.

[0115] As mentioned above, providing Figure 6 As an example. Other examples can be found with... Figure 6 The differences described in [the original text].

[0116] Figure 7 This is a flowchart of an example process 700 associated with forming the memory cell structure described herein. In some embodiments, one or more semiconductor processing tools are used to perform the process, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or another type of semiconductor processing tool.

[0117] like Figure 7 As shown, process 700 may include forming a first source / drain (block 710) of a back-end transistor structure of a semiconductor device. For example, one or more semiconductor processing tools may be used to form the first source / drain (e.g., source / drain 110) of a back-end transistor structure (e.g., transistor structure 106) of a semiconductor device (e.g., semiconductor device 100), as described herein.

[0118] like Figure 7 As further shown, process 700 may include forming a first hydrogen barrier array and a second hydrogen barrier array (block 720) over the first source / drain. For example, one or more semiconductor processing tools may be used to form the first hydrogen barrier array (e.g., hydrogen barrier array 120) and the second hydrogen barrier array (e.g., hydrogen barrier array 120) over the first source / drain, as described herein.

[0119] like Figure 7 As further shown, process 700 may include forming a gate (block 730) of a back-end transistor structure between the first hydrogen barrier column and the second hydrogen barrier column. For example, one or more semiconductor processing tools may be used to form the gate (e.g., gate 116) of the back-end transistor structure between the first hydrogen barrier column and the second hydrogen barrier column, as described herein.

[0120] like Figure 7 As further shown, process 700 may include forming a gate dielectric layer of a subsequent transistor structure on the sidewall of an opening through the gate above the first source / drain, and forming a channel layer of the subsequent transistor structure on the first source / drain (block 740). For example, one or more semiconductor processing tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 118) of the subsequent transistor structure on the sidewall of an opening (e.g., opening 510) through the gate above the first source / drain, and to form a channel layer of the subsequent transistor structure (e.g., channel layer 114) on the first source / drain, as described herein.

[0121] like Figure 7 As further shown, process 700 may include forming a second source / drain of a back-end transistor structure on the channel layer (block 750). For example, one or more semiconductor processing tools may be used to form the second source / drain of the back-end transistor structure on the channel layer, as described herein.

[0122] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or associated with one or more other processes described elsewhere herein.

[0123] In a first embodiment, forming the gate includes forming a channel gap wall (e.g., channel gap wall 422) over the first source / drain and forming the gate around the channel gap wall.

[0124] In the second embodiment, forming the channel layer, alone or in combination with the first embodiment, includes removing a channel gap wall after forming the gate, the removal of the channel gap wall causing the formation of an opening through the gate, and forming the channel layer in the opening previously occupied by the channel gap wall.

[0125] In the third embodiment, forming the first hydrogen barrier column and the second hydrogen barrier column, alone or in combination with one or more of the first and second embodiments, includes forming a gate spacer wall (e.g., gate spacer wall 506) above the first source / drain, forming a hydrogen barrier layer (e.g., hydrogen barrier layer 508) along the sidewalls and top surface of the gate spacer wall, and planarizing the hydrogen barrier layer to form the first hydrogen barrier column and the second hydrogen barrier column from the hydrogen barrier layer.

[0126] In the fourth embodiment, forming the gate, alone or in combination with one or more of the first to third embodiments, includes removing the gate spacer after planarizing the hydrogen barrier layer, and depositing the gate in the region previously occupied by the gate spacer between the first hydrogen barrier column and the second hydrogen barrier column.

[0127] In the fifth embodiment, forming a channel layer, alone or in combination with one or more of the first to fourth embodiments, includes forming an outer segment (e.g., outer segment 302b) of the channel layer on the gate dielectric layer and filling an opening through the gate with a core segment (e.g., core segment 302a) of the channel layer, wherein the outer segment of the channel layer is located between the core segment of the channel layer and the gate dielectric layer.

[0128] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the outer segment forming the channel layer includes forming an outer segment to include a first oxide semiconductor material having a first dopant concentration, and the core segment forming the channel layer includes forming a core segment to include a second oxide semiconductor material having a second dopant concentration less than the first dopant concentration.

[0129] Although Figure 7 An example block of process 700 is shown, but in some embodiments, process 700 includes... Figure 7 The blocks shown are those that are additional, fewer, different, or arranged differently compared to other blocks. Alternatively, two or more blocks in process 700 can be executed in parallel.

[0130] In this manner, a hydrogen barrier array can be included between the gate of a transistor structure and one or more other layers of the semiconductor device to prevent, minimize, and / or otherwise reduce hydrogen diffusion into the channel layer of the transistor structure. The hydrogen barrier array includes one or more materials that resist hydrogen absorption, which prevents, minimizes, and / or otherwise reduces the likelihood of hydrogen diffusion into the vertical channel layer of the transistor structure. In this way, the hydrogen barrier array prevents, minimizes, and / or otherwise reduces the likelihood of hydrogen contamination in the channel layer, enabling the transistor structure to achieve low current leakage.

[0131] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a transistor structure within the plurality of back-end dielectric layers. The transistor structure includes a first source / drain, a second source / drain above the first source / drain, a channel layer extending vertically between the first and second source / drain, a gate laterally surrounding the channel layer, and one or more hydrogen barrier columns extending along one or more sides of the gate.

[0132] In some embodiments, one or more hydrogen barrier columns comprise at least one of the following: a nitride-containing dielectric material or an oxide-containing dielectric material. In some embodiments, the bottom surface of one or more hydrogen barrier columns is substantially coplanar with the bottom surface of the gate, and the top surface of the one or more hydrogen barrier columns is substantially coplanar with the top surface of the gate. In some embodiments, the channel layer comprises at least one of the following: a p-type oxide semiconductor material or an n-type oxide semiconductor material. In some embodiments, the channel layer comprises: a core segment comprising a first semiconductor material having a first doping concentration; and an outer segment surrounding the core segment, wherein the outer segment comprises a second semiconductor material having a second doping concentration different from the first doping concentration. In some embodiments, the second doping concentration is greater than the first doping concentration. In some embodiments, the one or more hydrogen barrier columns extend continuously along multiple gates of multiple transistor structures in the semiconductor device.

[0133] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first source / drain of a back-end transistor structure of a semiconductor device. The method includes forming a first hydrogen barrier array and a second hydrogen barrier array over the first source / drain. The method includes forming a gate of the back-end transistor structure between the first and second hydrogen barrier arrays. The method includes forming a gate dielectric layer of the back-end transistor structure on a sidewall of an opening through the gate over the first source / drain, and forming a channel layer of the back-end transistor structure over the first source / drain. The method includes forming a second source / drain of the back-end transistor structure on the channel layer.

[0134] In some embodiments, forming the gate includes: forming a channel spacer over the first source / drain; and forming the gate around the channel spacer. In some embodiments, forming the channel layer includes: after forming the gate, removing the channel spacer, wherein the removal of the channel spacer results in forming the opening through the gate; and forming the channel layer in the opening previously occupied by the channel spacer. In some embodiments, forming the first hydrogen barrier column and the second hydrogen barrier column includes: forming a gate spacer over the first source / drain; forming a hydrogen barrier layer along the sidewalls and top surface of the gate spacer; and planarizing the hydrogen barrier layer to form the first hydrogen barrier column and the second hydrogen barrier column. In some embodiments, forming the gate includes: after planarizing the hydrogen barrier layer, removing the gate spacer; and depositing the gate in the region between the first hydrogen barrier column and the second hydrogen barrier column previously occupied by the gate spacer. In some embodiments, forming the channel layer includes: forming an outer segment of the channel layer on the gate dielectric layer; and filling the opening through the gate with a core segment of the channel layer, wherein the outer segment of the channel layer is between the core segment of the channel layer and the gate dielectric layer. In some embodiments, forming the outer segment of the channel layer includes: forming the outer segment to include a first oxide semiconductor material having a first doping concentration; and wherein forming the core segment of the channel layer includes: forming the core segment to include a second oxide semiconductor material having a second doping concentration less than the first doping concentration.

[0135] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure within the plurality of back-end dielectric layers. The memory cell structure includes a storage structure (108) and a transistor structure above the storage structure. The transistor structure includes a first source / drain, a second source / drain above the first source / drain, a channel layer extending vertically between the first and second source / drains, a gate laterally surrounding the channel layer, a first hydrogen barrier column extending along a first side of the gate, and a second hydrogen barrier column extending along a second side of the gate opposite to the first side.

[0136] In some embodiments, the first hydrogen barrier column and the second hydrogen barrier column each comprise at least one of the following: aluminum nitride, aluminum oxynitride, or aluminum oxide. In some embodiments, the lateral width of the first hydrogen barrier column is in the range of about 10 nanometers to about 100 nanometers. In some embodiments, the second source / drain is coupled to a bit line conductive structure above the second source / drain, wherein the bit line conductive structure extends in the semiconductor device along a first lateral direction (x-direction); and wherein the first hydrogen barrier column and the second hydrogen barrier column each extend in the semiconductor device along a second lateral direction substantially perpendicular to the first lateral direction. In some embodiments, the gate is coupled to a word line interconnect structure below the gate; wherein the word line interconnect structure is coupled to a word line conductive structure below a word line via structure; and wherein the word line conductive structure, the first hydrogen barrier column, and the second hydrogen barrier column each extend in a lateral direction in the semiconductor device. In some embodiments, the first hydrogen barrier column and the second hydrogen barrier column each comprise at least one of the following: silicon nitride, silicon carbonitride, or carbonoxynitride.

[0137] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended as limitations. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized by comprising: include: Multiple back-end dielectric layers; as well as A transistor structure, in the back dielectric layer and comprising: First source / drain; The second source / drain is located above the first source / drain; The channel layer extends vertically between the first source / drain and the second source / drain; A gate, laterally surrounding the channel layer; and One or more hydrogen barrier columns extend along one or more sides of the gate.

2. The semiconductor device according to claim 1, wherein The bottom surface of one or more hydrogen barrier columns is coplanar with the bottom surface of the gate.

3. The semiconductor device according to claim 1, wherein The top surface of one or more hydrogen barrier columns is coplanar with the top surface of the gate.

4. The semiconductor device according to claim 1, wherein The channel layer includes: The core section includes a first semiconductor material with a first doping concentration; and An outer segment, surrounding the core segment, wherein the outer segment comprises a second semiconductor material having a second doping concentration different from the first doping concentration.

5. The semiconductor device according to claim 4, wherein The second doping concentration is greater than the first doping concentration.

6. The semiconductor device according to claim 1, wherein The one or more hydrogen barrier columns extend continuously along the multiple gates of multiple transistor structures in the semiconductor device.

7. A semiconductor device, characterized by comprising: include: Multiple back-end dielectric layers; as well as The memory cell structure, in the back dielectric layer, includes: Storage structure; and A transistor structure, on the storage structure, includes: First source / drain; The second source / drain is located above the first source / drain; The channel layer extends vertically between the first source / drain and the second source / drain; A gate, which laterally surrounds the channel layer; A first hydrogen barrier array extends along a first side of the gate; and The second hydrogen barrier column extends along the second side of the gate opposite to the first side.

8. The semiconductor device according to claim 7, wherein The lateral width of the first hydrogen barrier column is in the range of 10 nanometers to 100 nanometers.

9. The semiconductor device according to claim 7, wherein The second source / drain is coupled to a bit line conductive structure above the second source / drain; The bit line conductive structure extends along a first lateral direction in the semiconductor device; and The first hydrogen barrier column and the second hydrogen barrier column each extend in the semiconductor device along a second lateral direction that is substantially perpendicular to the first lateral direction.

10. The semiconductor device according to claim 7, wherein The gate is coupled to the word line interconnect structure below the gate; The word line interconnect structure is coupled to the word line conductive structure beneath the word line via structure; and The word line conductive structure, the first hydrogen barrier column, and the second hydrogen barrier column each extend in the lateral direction of the semiconductor device.

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