An improved stereo-packaged DDR4 SDRAM memory

Abstract

This utility model relates to the field of memory technology and discloses an improved three-dimensional packaged DDR4 SDRAM memory, including a third stacked board, an interlayer interconnect board, and a first stacked board stacked sequentially from top to bottom. At least one first chip is disposed on the first stacked board. Through-holes adapted to the first chip are disposed on the interlayer interconnect board. A third interconnect pad is disposed on the bottom surface of the third stacked board, and the third interconnect pad is shaped to fit the interlayer interconnect board. A second chip is disposed on the upper surface of the stacked board. The first stacked board and the second chip are encapsulated together with potting compound to form a package. A second interconnect pad is disposed on the bottom of the interlayer interconnect board. The first stacked board and the third stacked board are interconnected through the interlayer interconnect board.

Description

Technical Field

[0001] This utility model relates to the field of memory technology, and in particular to an improved stereo-packaged DDR4 SDRAM memory. Background Technology

[0002] With the rapid development of integrated circuits and the improvement of process technology, the density of three-dimensional packaging is getting higher and higher. Many customers have put forward an urgent demand for small-volume high-performance DDR4 SDRAM memory (hereinafter referred to as DDR4). High-performance DDR4 SDRAM memory often has a faster operating frequency, more data bit width, and a wider operating temperature range. It is made up of multiple DDR4 chips of the same type stacked together. The internal components usually include 5 DDR4 chips, multiple filter capacitors, multiple VTT resistors, etc.

[0003] Existing technologies use processes such as laminated board assembly, laminated board stacking, resin potting, cutting, surface metallization, and surface interconnect engraving to form a sealed module. As module integration becomes increasingly complex and the operating frequency of DDR4 SDRAM memory increases, high-frequency signals are interconnected between layers via surface interconnect engraving. However, the operating frequency of DDR4 SDRAM memory can only reach 1.0GHz (surface metallization is a plating process; the lack of a reference plane in the plating can cause impedance discontinuities in high-speed signals), which cannot meet the DDR4 datasheet standards and customer requirements.

[0004] To meet the faster operating frequency performance of DDR4 SDRAM memory and ensure the stability and reliability of module operation, researchers in this field have proposed an improved stereo-packaged DDR4 SDRAM memory. Utility Model Content

[0005] The technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide an improved three-dimensional packaged DDR4 SDRAM memory, which effectively solves the problem of impedance discontinuity of high-speed signals in DDR4 SDRAM memory, and improves the operating frequency of DDR4 SDRAM memory while ensuring signal integrity.

[0006] The technical solution of this utility model is as follows: an improved three-dimensional packaged DDR4 SDRAM memory, comprising a third stacked board, an interlayer interconnect board, and a first stacked board stacked sequentially from top to bottom. At least one first chip is disposed on the first stacked board. Through-holes adapted to the first chip are disposed on the interlayer interconnect board. A third interconnect pad is disposed on the bottom surface of the third stacked board, and the third interconnect pad is shaped to fit the interlayer interconnect board. A second chip is disposed on the upper surface of the stacked board. The first stacked board and the second chip are encapsulated together with potting compound to form a package. A second interconnect pad is disposed on the bottom of the interlayer interconnect board. The first stacked board and the third stacked board are interconnected through the interlayer interconnect board.

[0007] As can be seen from the above scheme, the third stacked board and the first stacked board are interconnected by adding the interlayer interconnect board. The through holes on the interlayer interconnect board are used to adapt to the first DDR4 chip on the third stacked board, thereby reducing the overall module height and package size. This utility model eliminates the bridge line design and surface interconnect engraving of the third stacked board, effectively solving the impedance discontinuity of the high-speed signal of the DDR4 SDRAM memory, ensuring signal integrity, and increasing the operating frequency of the DDR4 SDRAM memory from 1.0GHz to 1.6GHz.

[0008] The second interconnect pad and the third interconnect pad each include a plurality of BGA solder balls. Therefore, the solder balls are used for electrical connections between the third stacked board, the interlayer interconnect board, and the first stacked board, thereby achieving interconnection between the first stacked board and the third stacked board.

[0009] Both the first chip and the second chip are DDR4 chips.

[0010] There are two of the first chips arranged side by side.

[0011] The first laminate, the third laminate, and the interlayer interconnect are all made of high-speed substrate material. Therefore, the high-speed substrate material is used to ensure signal integrity, achieve impedance controllability, and avoid impedance discontinuity issues.

[0012] The thickness of the interlayer interconnect board is between 1.4 mm and 1.8 mm. Therefore, the interlayer interconnect board is used to achieve interconnection between upper and lower layers. Attached Figure Description

[0013] Figure 1 This is an exploded view of this utility model;

[0014] Figure 2 This is a partial structural schematic diagram of the present invention;

[0015] Figure 3 This is a schematic diagram of the structure of this utility model. Detailed Implementation

[0016] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

[0017] like Figures 1 to 3 As shown, this utility model is an improved three-dimensional packaged DDR4 SDRAM memory, including a third stacked board 1, an interlayer interconnect board 2, and a first stacked board 3 stacked sequentially from top to bottom. At least one first chip 4 is disposed on the first stacked board 3. Through-holes 21 adapted to the first chip 4 are disposed on the interlayer interconnect board 2. A third interconnect pad 11 is disposed on the bottom surface of the third stacked board 1, and the third interconnect pad 11 is shaped to match the interlayer interconnect board 2. A second chip 5 is disposed on the upper surface of the stacked board. The first stacked board 3 and the second chip 5 are encapsulated together with potting compound to form a package. A second interconnect pad 22 is disposed on the bottom of the interlayer interconnect board 2. The third interconnect pad 11 and the second interconnect pad 22 are positioned correspondingly. The first stacked board 3 and the third stacked board 1 are interconnected through the interlayer interconnect board 2.

[0018] In this embodiment, a metal shielding layer is provided on the surface of the package to improve the memory's resistance to ionizing radiation. The metal shielding layer is a nickel alloy shielding layer, which can shield most external electromagnetic signal interference. During stacking, with the assistance of a stacking mold, the third stacked board 1, the interlayer interconnect board 2, and the first stacked board 3 are vertically stacked and assembled in three-dimensional space to complete the stacking. The third solder ball layer 11 and the second solder ball layer 22 need to ensure that adjacent high-speed signals are separated by GND to reduce crosstalk between high-speed signals and shorten the signal return path.

[0019] This invention effectively realizes the application of high-speed DDR4 SDRAM memory in three-dimensional packaging. By using an interlayer interconnect board instead of a bridge design, it effectively solves the impedance discontinuity of high-speed signals in DDR4 SDRAM memory, significantly reduces crosstalk problems, ensures signal integrity, and increases the operating frequency of DDR4 SDRAM memory from 1.0GHz to 1.6GHz. The stability and reliability of the module are also significantly improved.

[0020] The second interconnect pad 22 and the third interconnect pad 11 each include a plurality of BGA solder balls. In this embodiment, the layout of the second interconnect pad 22 is consistent with the layout of the third interconnect pad 11.

[0021] Both the first chip 4 and the second chip 5 are DDR4 chips. In this embodiment, there are three second chips 5. Two first chips 4 are arranged side by side. The through holes 21 are two rectangular through holes corresponding to the first chips 4.

[0022] The first laminate 3, the third laminate 1, and the interlayer interconnect plate 2 are all made of high-speed sheet metal. The thickness of the interlayer interconnect plate 2 is between 1.4 mm and 1.8 mm. In this embodiment, the thickness of the interlayer interconnect plate is 1.6 mm.

[0023] Finally, it should be emphasized that the above description is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An improved stereo-packaged DDR4 SDRAM memory, characterized in that: The system includes a third stacked board (1), an interlayer interconnect board (2), and a first stacked board (3) stacked sequentially from top to bottom. At least one first chip (4) is disposed on the first stacked board (3). The interlayer interconnect board (2) is provided with a through hole (21) adapted to the first chip (4). The bottom surface of the third stacked board (1) is provided with a third interconnect pad (11). The third interconnect pad (11) is adapted to the shape of the interlayer interconnect board (2). The upper surface of the stacked board is provided with a second chip (5). The first stacked board (3) and the second chip (5) are used to encapsulate the first stacked board (3) and the second chip (5) into a package by potting compound. The bottom of the interlayer interconnect board (2) is provided with a second interconnect pad (22). The first stacked board (3) and the third stacked board (1) are used to interconnect through the interlayer interconnect board (2).

2. The improved 3D package DDR4 SDRAM memory of claim 1, wherein: The second interconnect pad (22) and the third interconnect pad (11) each include a plurality of BGA solder balls.

3. The improved 3D package DDR4 SDRAM memory of claim 1, wherein: Both the first chip (4) and the second chip (5) are DDR4 chips.

4. The improved 3D package DDR4 SDRAM memory of claim 3, wherein: There are two of the first chips (4) arranged side by side.

5. The improved 3D package DDR4 SDRAM memory as claimed in claim 3, wherein: The first laminate (3), the third laminate (1) and the interlayer interconnection plate (2) are all made of high-speed sheet metal.

6. The improved 3D package DDR4 SDRAM memory as claimed in claim 1, wherein: The thickness of the interlayer interconnect plate (2) is between 1.4 mm and 1.8 mm.

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