A battery management chip and a battery management system

Abstract

This utility model discloses a battery management chip and a battery management system, applicable to the field of electronic chip technology. The battery management chip includes multiple chips; each chip includes at least a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin. The charge / discharge drive pin of the chip is used to connect to an external charge / discharge circuit. The voltage sampling pins of the multiple chips are connected to the cells of a battery pack, which includes multiple strings of cells. The multiple chips are connected in series or parallel, and the differential communication pins of the multiple chips are interconnected. These differential communication pins are used to transmit cell status information detected by the voltage sampling pins. This design eliminates the need for redesigning the battery management chip, effectively saving development costs and time, and improving development efficiency.

Description

Technical Field

[0001] This utility model relates to the field of electronic chip technology, and in particular to a battery management chip and a battery management system. Background Technology

[0002] With the development of the new energy industry, the business development of battery management systems (BMS) has attracted increasing attention. The battery management chip in the battery management system can detect the status of the battery cells in real time and protect the battery cells. The battery management chip can be an analog front-end chip (AFE chip) or a current metering chip.

[0003] Battery management chips are often designed in different types based on varying design requirements. For example, they can be categorized by the number of connected battery cells (3-5, 3-8, 6-14, 6-16, 6-18, or even more). Alternatively, they can be classified according to functional requirements, with or without current sampling, high-side MOS driving, or daisy-chain communication. To meet these diverse design needs, developers often need to redesign the corresponding battery management chip. Since most functions of battery management chips overlap, redesigning the chip requires significant development costs and time, leading to reduced development efficiency. Utility Model Content

[0004] This invention provides a battery management chip and a battery management system, which effectively saves the development cost and time of the battery management chip and improves the development efficiency of the battery management chip.

[0005] This utility model provides a battery management chip, which includes: a plurality of chips;

[0006] Each of the aforementioned chips includes at least: a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin; the charge / discharge drive pin of the chip is used to connect to the charge / discharge circuit outside the battery management chip;

[0007] The voltage sampling pins of multiple of the aforementioned crystals are connected to the cells of the battery pack, which includes multiple strings of cells;

[0008] The multiple chips are connected in series or in parallel, and the differential communication pins of the multiple chips are interconnected. The differential communication pins of the multiple chips are used to transmit cell status information detected by the pins based on the voltage.

[0009] Furthermore, the voltage sampling pins of the multiple crystals are respectively connected to different cell terminals in the battery pack;

[0010] The multiple grains are connected in series, including:

[0011] The voltage input pin of the highest-order crystal among the plurality of crystals is connected to the positive terminal of the battery pack;

[0012] In a plurality of adjacent dies, the ground pin of the upper-level die is connected to the voltage input pin of the lower-level die;

[0013] The ground pin of the lowest-level crystal among the plurality of crystals is connected to the negative terminal of the battery pack.

[0014] Furthermore, the charge / discharge drive pin of the highest-level chip is connected to the charge / discharge circuit outside the battery management chip, and the differential communication pin of the highest-level chip is used to receive the detected cell status information sent by other chips besides the highest-level chip among the multiple chips.

[0015] Furthermore, each of the aforementioned chips also includes: a current detection pin; the current detection pin of the lowest-level chip is connected in parallel with a current detection resistor, and the differential communication pin of the lowest-level chip is used to receive detected cell voltage information sent by other chips other than the lowest-level chip among the plurality of chips.

[0016] Furthermore, voltage sampling pins with the same serial number in multiple of the aforementioned grains are connected to the same cell endpoint in the battery pack;

[0017] The multiple grains are connected in parallel, including:

[0018] The voltage input pins of multiple chips are all connected to the positive terminal of the battery pack, and the ground pins of multiple chips are all connected to the negative terminal of the battery pack.

[0019] Furthermore, the charging and discharging drive pins of the plurality of said chips are interconnected, and the charging and discharging drive pin of any one of the plurality of said chips is connected to the charging and discharging circuit outside the battery management chip.

[0020] Furthermore, each of the aforementioned chips also includes a current sensing pin; the current sensing pins of the plurality of chips are all connected in parallel with a current sensing resistor.

[0021] Furthermore, each of the aforementioned chips also includes: an extended function output pin; the extended function output pins of the plurality of chips are interconnected, and the extended function output pin of any one of the plurality of chips is connected to an external circuit of the battery management chip.

[0022] Furthermore, the differential communication pins of the multiple chips are interconnected via capacitors.

[0023] This utility model also provides a battery management system, including the battery management chip described above.

[0024] As can be seen from the above technical solutions, this utility model has the following advantages:

[0025] In this invention, the battery management chip includes multiple chips; each chip includes at least a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin; the charge / discharge drive pin of the chip is used to connect to an external charge / discharge circuit of the battery management chip; the voltage sampling pins of the multiple chips are connected to the cells of a battery pack, the battery pack including multiple strings of cells; the multiple chips are connected in series or parallel, and the differential communication pins of the multiple chips are interconnected, used to transmit cell status information detected by the voltage sampling pins. By connecting the multiple chips in series or parallel and interconnecting the differential communication pins of the multiple chips, various different design requirements can be achieved without redesigning the battery management chip, effectively saving development costs and time, and improving development efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0027] Figure 1 This is a structural block diagram of a battery management chip disclosed in this utility model;

[0028] Figure 2 This is a circuit diagram of a single-chip battery management chip disclosed in this utility model;

[0029] Figure 3 This is a circuit diagram of a battery management chip with connected chips according to the present invention;

[0030] Figure 4 This is a circuit diagram of a battery management chip with parallel connected chips disclosed in this utility model. Detailed Implementation

[0031] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0032] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0033] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0034] Existing battery management chips are often designed as different types of chips based on different design requirements. For example, they can be categorized by the number of connected battery cells (3-5, 3-8, 6-14, 6-16, 6-18, or even more). Alternatively, they can be classified according to functional requirements, with or without current sampling, high-side MOS driving, or daisy-chain communication. To meet these diverse design requirements, developers often need to redesign the corresponding battery management chip. Since most functions of battery management chips overlap, redesigning the chip requires significant development costs and time, leading to reduced development efficiency. Therefore, this invention provides a battery management chip that effectively saves development costs and time, improving development efficiency. Figure 1 As shown, the details are as follows:

[0035] In this invention, the battery management chip includes multiple dies, which can be two or more dies. Each die is a single semiconductor wafer containing a complete circuit structure, cut from a wafer during the battery management chip manufacturing process, and is the smallest unit with complete circuit functionality; that is, each die has the function of detecting the state of the battery cell and outputting corresponding drive based on the state of the battery cell. This battery management chip can be an analog front-end chip (AFE chip), a power metering chip, or a battery protection chip, and is not specifically limited here.

[0036] Each die includes: a voltage sampling pin Vc, a charge / discharge drive pin Driver, and differential communication pins (high-level terminal COMH and low-level terminal COML). The Driver pin connects to the external charge / discharge circuit of the battery management chip and outputs a drive signal to the circuit to control its charging and discharging process. Multiple die voltage sampling pins Vc are connected to the cells of the battery pack, which consists of multiple strings of cells (8 or 10 strings, depending on the specific configuration). A die can connect to the terminal (positive or negative) of a cell in the battery pack via a single Vc pin to sample its voltage. Dies can be connected in series or parallel. In series, the first and last voltage sampling pins of adjacent dies in the battery management chip are connected in series; in parallel, the voltage sampling pins of multiple dies in the battery management chip are connected in parallel. The differential communication pins of multiple chips are interconnected, that is, the high-level terminals COMH of multiple chips are interconnected, and the low-level terminals COML of multiple chips are interconnected.

[0037] Preferably, the differential communication pins of multiple chips are interconnected via capacitors. By removing DC bias and suppressing low-frequency noise, the capacitors can function as isolated differential communication pins, enabling communication between chips in different voltage domains. These differential communication pins are used to transmit cell status information detected by the pins based on voltage. This cell status information can include voltage, current, and other data. It is understood that, according to different design requirements, multiple chips can be connected in series or parallel, communicating with each other via differential communication pins. For example, if the design requires expanding the number of cell strings in the battery pack, multiple chips can be connected in series, transmitting detected cell status information via differential communication pins to detect more cells in a larger number of strings. If the design requires verifying the detected cell status, multiple chips can be connected in parallel, transmitting detected cell status information via differential communication pins to mutually verify the cell status detected by multiple chips.

[0038] As can be seen, in this utility model, the battery management chip includes: multiple chips; each chip includes at least: a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin; the charge / discharge drive pin of the chip is used to connect to the external charge / discharge circuit of the battery management chip; the voltage sampling pins of the multiple chips are connected to the cells of the battery pack, and the battery pack includes multiple strings of cells; the multiple chips are connected in series or parallel, and the differential communication pins of the multiple chips are interconnected, and the differential communication pins of the multiple chips are used to transmit cell status information detected by the voltage sampling pins. By changing the packaging structure of the multiple chips in the battery management chip, and connecting the multiple chips in series or parallel, and interconnecting the differential communication pins of the multiple chips, various different design requirements can be achieved without redesigning the battery management chip, effectively saving the development cost (including human resources cost and material resource cost) and development time of the battery management chip, and improving the development efficiency of the battery management chip. That is, more battery management chips can be produced in a shorter development time with less development cost. The battery management chip concept is simple, the design is convenient, and the chip performance can be enhanced.

[0039] Furthermore, it is understandable that the maximum number of voltage sampling pins that can be set on a single chip in a battery management chip is limited, and the maximum number of cell strings that can be connected to a single chip is also limited. For example, a single chip can connect a maximum of 6 or 8 cell strings, but the specific number is not limited here.

[0040] For example, a maximum of 8 cells can be connected to a single die, while a battery management chip contains only one die, such as... Figure 2As shown in chip 1, the battery pack includes 8 cells in series. The voltage sampling pins on die 1 (including the voltage input pin VBAT, the ground pin VSS, and other voltage sampling pins Vc) are connected in parallel to different cell endpoints to achieve voltage sampling. The current sampling pin on die 1 is connected in parallel with the current sampling resistor Rsense to achieve current sampling. The communication pins (SPI / UART / 12C) on die 1 communicate with the external host to achieve external communication. The charge / discharge drive pins (charge drive pin Driver-CHG and discharge drive pin Driver-DSG) on die 1 are connected to the external charge / discharge circuit to achieve charge / discharge drive. The extended function output pins (Other Function pins) on die 1 are used for custom configuration and can achieve functions such as temperature sampling, midpoint output, GPIO (General Purpose Input / Output) and LDO (Low Dropout Linear Regulator). In addition, unlike the conventional design of battery management chips, the die 1 also includes differential communication pins COMH and COML for communication between different dies.

[0041] In this invention, the battery management chip is representative of chips with multi-channel expansion requirements. Many similar chips exist, such as analog-to-digital converter (ADC) chips, timer chips, GPIO expansion chips, or communication interface expansion chips, etc., and are not specifically limited here. Due to different application environments, the number of battery cells connected to the battery management chip may exceed the maximum number of battery cell strings that can be connected to a single die. For example, the number of battery cell strings connected to the battery management chip may increase to 10, 14, 16, 20, 24, or 26 strings. Existing designs often require redesigning battery management chips with different numbers of voltage sampling pins for different numbers of battery cell strings, increasing development costs and time. To meet the expansion requirements of the number of battery cell strings connected to the battery management chip, this invention allows for the increase of the number of battery cell strings connected to the battery management chip by cascading multiple dies in series. For example, if the maximum number of battery cell strings that can be connected to each die is N strings, M dies can be cascaded, making the maximum number of battery cell strings connected to the battery management chip N×M strings.

[0042] In a battery management chip, multiple chips are connected in series, such as... Figure 3As shown, the battery management chip connects to 24 battery cell strings. The voltage sampling pins of multiple chips are connected to different cell terminals in the battery pack. For example, if the battery management chip contains three chips (die1, die2, die3), each chip is connected to its corresponding 8 battery cell strings. The three chips communicate with each other via isolated differential communication pins. In this case, only one chip's extended function output pin (Other Function pins) needs to be connected to the external circuit. The multiple chips are connected in series, including: the voltage input pin of the highest-level chip is connected to the positive terminal of the battery pack; the ground pin of the higher-level chip in any two adjacent chips is connected to the voltage input pin of the lower-level chip; and the ground pin of the lowest-level chip is connected to the negative terminal of the battery pack. As shown in the figure, the voltage input pin VBAT (i.e., the highest voltage sampling pin) of die1 is connected to the positive terminal of the battery pack (i.e., the positive terminal of the 24th cell); the ground pin VSS of die1 is connected to the voltage input pin VBAT of die2, the ground pin VSS of die2 is connected to the voltage input pin VBAT of die3; and the ground pin VSS of die3 is connected to the negative terminal of the battery pack.

[0043] As can be seen, by connecting multiple chips in series and communicating with each other via differential communication, the number of cell strings connected to the battery management chip can be easily expanded. No redesign is required; simply changing the packaging structure can achieve a transformation from 8 to 16 or even 24 cell strings connected to the battery management chip, greatly improving chip design efficiency. Simultaneously, by utilizing the parallel operation of multiple chips, each chip can sample the voltage of its corresponding cell in parallel, increasing the ADC sampling rate of the battery management chip and enabling the acquisition of voltage information for all connected cells in a shorter time.

[0044] Furthermore, when multiple chips in a battery management chip are connected in series, the charge / discharge drive pin of the highest-level chip is connected to the external charge / discharge circuit of the battery management chip. The differential communication pin of the highest-level chip is used to receive the detected cell status information sent by other chips besides the highest-level chip. The highest-level chip, based on its own detected cell status information and the cell status information detected by other chips, sends drive signals to the external charge / discharge circuit (such as a MOSFET or transistor) through the charge / discharge drive pin to control the charge / discharge process of the circuit. Figure 3In the process, the charging and discharging drive pins Driver-DSG and Driver-CHG of die 1 are connected to the external charging and discharging circuit as the charging and discharging drive pins of chip 2. Die 1 receives the cell status information detected by die 2 and die 3 through the differential communication pins COMH and COML, and drives the external charging and discharging circuit based on the cell status information.

[0045] Furthermore, when multiple chips in a battery management chip are connected in series, for current sampling, each chip also includes: a current detection pin; the current detection pin of the lowest-level chip is connected in parallel with a current detection resistor; the differential communication pin of the lowest-level chip is used to receive the detected cell voltage information sent by other chips besides the lowest-level chip; the lowest-level chip can obtain the current corresponding to the cell detected by other chips through the cell voltage information detected by other chips and the current detection resistor. Figure 3 As shown, the Currentsense pin of Die3 is connected in parallel with the current sensing resistor Rsense. Die3 receives the cell voltage information sent by Die1 and Die2 through the differential communication pin, and can obtain the corresponding cell current information based on the current sensing resistor Rsense.

[0046] Furthermore, in this invention, the battery management chip can also be a chip with redundancy verification function, such as a PGA operational amplifier chip, a feedback chip, etc., and is not specifically limited here. The corresponding battery management chip has design requirements for reliability and functional safety levels, requiring it to have redundancy verification function. In this case, existing designs often require redesigning the battery management chip to have redundancy verification function, increasing development costs and time. To meet the requirement of redundancy verification function in the battery management chip, this invention connects multiple chips in parallel, using each other as redundant backups for information verification, thus realizing the redundancy verification function of the battery management chip and enhancing its reliability.

[0047] Voltage sampling pins with the same serial number in multiple dies are connected to the same cell terminal in the battery pack; the multiple dies are connected in parallel, including: the voltage input pins of multiple dies are all connected to the positive terminal of the battery pack, and the ground pins of multiple dies are all connected to the negative terminal of the battery pack. For example... Figure 4As shown, in chip 3, the voltage sampling pin of die 1 is connected to the cell terminals of the 8-cell battery pack, and the voltage sampling pin of die 2 is connected in parallel with the voltage sampling pin of the same number. The voltage input pins VBAT of both die 1 and die 2 are connected to the positive terminal of the battery pack, and the ground pins VSS of both die 1 and die 2 are connected to the negative terminal of the battery pack. At this time, the voltage of each cell in the battery pack is collected by the analog-to-digital converter (ADC) of die 1 and die 2. The detected voltage information is transmitted through the differential communication pins COMH and COML of die 1 and die 2 for comparison and confirmation. Die 1 and die 2 serve as redundant backups for each other and verify the detected voltage information, realizing the redundancy verification function of the battery management chip and improving the reliability of the battery management chip's functional output.

[0048] As can be seen, by connecting multiple chips in parallel and communicating with each other via differential communication, the redundancy verification function of the battery management chip can be achieved. No redesign is required; only the packaging structure needs to be changed to add redundancy verification functionality, improving chip design efficiency. Simultaneously, in a parallel configuration of multiple chips, functional backup can be used to achieve precise voltage sampling (i.e., multiple chips collect the same voltage, and the collected results are averaged or weighted to offset random errors and improve accuracy), wide-range current sampling (i.e., by configuring some chips to be adapted for small current sampling and others for large current sampling to cover a larger current range), or precise sampling with the same range as a single chip (i.e., the equivalent range of multiple chips remains unchanged, but the sampling accuracy of data collected by multiple chips is higher than that of a single chip).

[0049] Furthermore, when multiple chips are connected in parallel, the charging and discharging drive pins of the multiple chips are interconnected, and the charging and discharging drive pin of any one of the chips is connected to the external charging and discharging circuit of the battery management chip, thus connecting to the external charging and discharging circuit through the charging and discharging drive pin of that chip. Figure 4 As shown, the charging and discharging drive pins Driver-DSG and Driver-CHG of die Die1 and die Die2 are interconnected, and the charging and discharging drive pins Driver-DSG and Driver-CHG of die Die2 are connected to the charging and discharging circuit outside the battery management chip.

[0050] Furthermore, when multiple chips are connected in parallel, for current sampling, each chip also includes: a current detection pin; the current detection pins of multiple chips are all connected in parallel with a current detection resistor, and the current detection pins of multiple chips are connected in parallel with the same current detection resistor to ensure that the multiple chips verify the detected cell current information under the same conditions. Figure 4As shown, the current sense pins of both die1 and die2 are connected in parallel with the current sense resistor Rsense.

[0051] Furthermore, when multiple chips are connected in parallel, each chip also includes an extended function output pin for the extended function output. The extended function output pins of multiple chips are interconnected, and the extended function output pin of any one of the chips is connected to external circuitry of the battery management chip. Information from the extended function output pins of multiple chips is also compared and confirmed via a differential communication pin COMH / L, such as comparing sampled temperature information, input / output information, etc., to verify the extended function information. Figure 4 As shown, the extended function output pins (Other Function pins) of die1 and die2 are interconnected, and the extended function output pins (Other Function pins) of die2 are connected to the external circuitry of the battery management chip.

[0052] This utility model also provides a battery management system, including the battery management chip described above. The battery management chip includes: multiple chips; each chip includes at least: a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin; the multiple chips are connected in series or parallel, and the differential communication pins of the multiple chips are interconnected. The differential communication pins of the multiple chips are used to transmit cell status information detected by the voltage sampling pin. By connecting the multiple chips in series or parallel and interconnecting the differential communication pins of the multiple chips, various different design requirements can be achieved in the battery management system without redesigning the battery management chip, effectively saving development costs and time, and improving the development efficiency of the battery management system.

[0053] In this invention, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0054] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model, and they should all be covered within the scope of the claims and specification of this utility model.

Claims

1. A battery management chip, characterized by, The battery management chip includes: multiple chips; Each of the aforementioned chips includes at least: a voltage sampling pin, a charge / discharge drive pin, and a differential communication pin; the charge / discharge drive pin of the chip is used to connect to the charge / discharge circuit outside the battery management chip; The voltage sampling pins of multiple of the aforementioned crystals are connected to the cells of the battery pack, which includes multiple strings of cells; The multiple chips are connected in series or in parallel, and the differential communication pins of the multiple chips are interconnected. The differential communication pins of the multiple chips are used to transmit cell status information detected by the pins based on the voltage.

2. The battery management chip of claim 1, wherein, The voltage sampling pins of the multiple crystals are respectively connected to different cell terminals in the battery pack; The multiple grains are connected in series, including: The voltage input pin of the highest-order crystal among the plurality of crystals is connected to the positive terminal of the battery pack; In a plurality of such dies, the ground pin of the upper-level die in two adjacent dies is connected to the voltage input pin of the lower-level die; The ground pin of the lowest-level crystal among the plurality of crystals is connected to the negative terminal of the battery pack.

3. The battery management chip of claim 2, wherein, The charge / discharge drive pin of the highest-level chip is connected to the charge / discharge circuit outside the battery management chip. The differential communication pin of the highest-level chip is used to receive the detected cell status information sent by other chips besides the highest-level chip among the multiple chips.

4. The battery management chip of claim 2, wherein, Each of the aforementioned chips further includes: a current detection pin; the current detection pin of the lowest-level chip is connected in parallel with a current detection resistor, and the differential communication pin of the lowest-level chip is used to receive detected cell voltage information sent by other chips other than the lowest-level chip among the plurality of chips.

5. The battery management chip of claim 1, wherein, The voltage sampling pins with the same serial number in multiple of the aforementioned crystals are connected to the same cell terminal in the battery pack; The multiple grains are connected in parallel, including: The voltage input pins of multiple chips are all connected to the positive terminal of the battery pack, and the ground pins of multiple chips are all connected to the negative terminal of the battery pack.

6. The battery management chip of claim 5, wherein, The charging and discharging drive pins of the plurality of said chips are interconnected, and the charging and discharging drive pin of any one of the plurality of said chips is connected to the charging and discharging circuit outside the battery management chip.

7. The battery management chip of claim 5, wherein, Each of the aforementioned chips further includes a current sensing pin; the current sensing pins of the plurality of chips are all connected in parallel with a current sensing resistor.

8. The battery management chip of claim 5, wherein, Each of the aforementioned chips further includes: an extended function output pin; the extended function output pins of the plurality of chips are interconnected, and the extended function output pin of any one of the plurality of chips is connected to external circuitry of the battery management chip.

9. The battery management chip of claim 1, wherein, The differential communication pins of the multiple chips are interconnected via capacitors.

10. A battery management system, characterized by, Includes the battery management chip described in any one of claims 1 to 9.

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