A system-in-package power semiconductor device

Abstract

This utility model relates to a system-in-package (SIP) power semiconductor device, comprising a substrate, a first MOS element, a second MOS element, bonding wires, a metal frame, and a molding portion. Both the first and second MOS elements include a first surface with a drain and a second surface with a source and a gate. The drains of the first and second MOS elements are opposite to and electrically connected. The metal frame is sleeved on the outside of the first and second MOS elements, with one end electrically connected to the source of the second MOS element and the other end electrically connected to the source of the first MOS element via the substrate. One end of the bonding wire is connected to the gate of the second MOS element, and the other end is electrically connected to the gate of the first MOS element via the substrate. The molding portion covers the first MOS element, the second MOS element, the metal frame, the bonding wires, and at least a portion of the substrate to form a package. This utility model can improve current carrying capacity while meeting miniaturization design requirements.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor packaging, and more specifically, to a system-in-package power semiconductor device. Background Technology

[0002] With the widespread adoption of 5G communication, high-power fast charging, and mobile AI applications, the power consumption of smart terminals continues to rise. To meet the high-current operating conditions, lithium battery protection circuits typically use multiple MOSFETs connected in parallel to reduce path impedance and temperature rise. However, placing multiple MOSFETs side-by-side on a plane significantly increases the area occupied on the substrate, which contradicts the trend towards thinner and lighter terminal devices. Furthermore, the more MOSFETs connected in parallel, the higher the requirements for impedance matching in the parallel path become. When impedance mismatch occurs, additional heat sources are generated. Existing parallel connection methods struggle to simultaneously meet the dual requirements of enhanced current carrying capacity and space compression. Utility Model Content

[0003] The purpose of this invention is to provide a system-in-package power semiconductor device that can improve current carrying capacity while meeting the design requirements of miniaturization.

[0004] A system-in-package power semiconductor device includes a substrate, a first MOS element, a second MOS element, bonding wires, a metal frame, and a molding portion; The first MOS element and the second MOS element both include a first surface with a drain and a second surface with a source and a gate. The drain of the first MOS element is opposite to and electrically connected to the drain of the second MOS element. The metal frame is sleeved on the outside of the first MOS element and the second MOS element. One end of the metal frame is electrically connected to the source of the second MOS element, and the other end of the metal frame is electrically connected to the source of the first MOS element through the substrate. One end of the bonding wire is connected to the gate of the second MOS element, and the other end is electrically connected to the gate of the first MOS element through the substrate; The molded portion covers the first MOS element, the second MOS element, the metal frame, the bonding wires, and at least a portion of the substrate to form a package.

[0005] In the above technical solution, by stacking the first MOS element and the second MOS element in the height direction, the drains of the two MOS elements are connected in parallel. Simultaneously, the sources are connected in parallel through a metal frame mating with the substrate, and the gates are connected in parallel through bonding wires mating with the substrate. This significantly reduces the occupied area while improving current carrying capacity, meeting the requirements of miniaturization. Replacing the copper foil connections of traditional PCBs with a metal frame reduces impedance and improves performance; furthermore, it increases the heat dissipation area and improves heat dissipation efficiency.

[0006] Furthermore, the source electrodes are symmetrically disposed on both sides of the second surface, and the gate electrode is located between the two source electrodes.

[0007] In the above technical solution, the symmetrically distributed source structure optimizes the current transmission path and forms a balanced conductive interface with the metal frame, avoiding local current concentration and improving parallel stability and heat distribution uniformity.

[0008] Furthermore, the metal frame has an opening for exposing the gate of the second MOS element, and the bonding wire passes through the opening to connect to the gate of the second MOS element.

[0009] In the above technical solution, the metal frame opening design provides a channel for the connection between the gate and the bonding wire, avoids the frame from interfering with the bonding wire, ensures the reliability of the gate signal connection, and at the same time maintains the complete coverage of the source by the frame to ensure heat dissipation performance.

[0010] Furthermore, the substrate is provided with a first electrical connection portion and a second electrical connection portion that are connected in communication. The gate of the first MOS element is electrically connected to the first electrical connection portion, and the bonding wire is electrically connected to the second electrical connection portion.

[0011] In the above technical solution, the substrate is provided with a first electrical connection portion and a second electrical connection portion, which are respectively connected to the gate and bonding line of the first MOS element, thereby realizing the parallel connection between the gates of the two MOS elements.

[0012] Furthermore, the substrate is provided with a third electrical connection portion, and the source of the first MOS element and the metal frame are both connected to the third electrical connection portion.

[0013] In the above technical solution, the metal frame and the source of the first MOS element are simultaneously connected to the third electrical connection part, so that the metal frame and the first MOS element are stably connected to the substrate, and the sources of the two MOS elements are connected in parallel.

[0014] Furthermore, the metal frame extends horizontally outward from one end near the substrate to form a welded portion.

[0015] In the above technical solution, the horizontally extended electrical connection increases the contact area with the substrate, enhances the mechanical fixation and thermal conductivity interface, reduces the impedance of the connection point, and makes the connection structure stable and reliable.

[0016] Furthermore, the first MOS element and the second MOS element are CSP packaged components.

[0017] In the above technical solution, CSP packaging can reduce the thickness of the first MOS element and the second MOS element, thereby reducing the overall height of the device and meeting the requirements of miniaturization.

[0018] Furthermore, the metal frame is made of copper.

[0019] In the above technical solution, the metal frame is made of copper, which can reduce the path impedance while ensuring heat dissipation performance.

[0020] Furthermore, the thickness of the first MOS element and the second MOS element is 0.05mm-0.15mm.

[0021] Furthermore, the substrate is provided with a plurality of electronic components, and the plurality of electronic components are encapsulated within the molding portion.

[0022] In the above technical solution, the integrated packaging of the molding section incorporates electronic components, which can further reduce the system volume and enhance the overall structural integrity.

[0023] Compared with existing technologies, the advantages of this invention are as follows: By stacking the first and second MOS elements in the height direction, the drains of the two MOS elements are connected in parallel. Simultaneously, the sources are connected in parallel through a metal frame and substrate, and the gates are connected in parallel through bonding wires and substrate. This significantly reduces the occupied area while improving current carrying capacity, meeting the requirements of miniaturization. Replacing the copper foil connection of traditional PCBs with a metal frame reduces impedance and improves performance; it also increases the heat dissipation area and improves heat dissipation efficiency. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a system-in-package power semiconductor device according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the structure of the first MOS element in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the structure of the first MOS element, the second MOS element, and the metal frame in an embodiment of the present invention.

[0027] Explanation of icon numbers: Substrate 1, first electrical connection 11, second electrical connection 12, third electrical connection 13, first MOS element 2a, second MOS element 2b, first surface 21, second surface 22, drain 23, source 24, gate 25, bonding wire 3, metal frame 4, opening 41, welding part 42, molding part 5, electronic components 6. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] Please refer to Figures 1 to 3 In a preferred embodiment, the system-in-package power semiconductor device of this invention mainly includes a substrate 1, a first MOS element 2a, a second MOS element 2b, a bonding wire 3, a metal frame 4, and a molding portion 5. The first MOS element 2a and the second MOS element 2b each include a first surface 21 with a drain 23 and a second surface 22 with a source 24 and a gate 25. The drain 23 of the first MOS element 2a and the drain 23 of the second MOS element 2b are opposite to each other and electrically connected. The metal frame 4 is sleeved on the outside of the first MOS element 2a and the second MOS element 2b. One end of the metal frame 4 is electrically connected to the source 24 of the second MOS element 2b, and the other end of the metal frame 4 is electrically connected to the source 24 of the first MOS element 2a through the substrate 1. One end of the bonding wire 3 is connected to the gate 25 of the second MOS element 2b, and the other end is electrically connected to the gate 25 of the first MOS element 2a through the substrate 1. The molding part 5 encapsulates the first MOS element 2a, the second MOS element 2b, the metal frame 4, the bonding wire 3, and at least part of the substrate 1 to form a package.

[0031] For example, both the first MOS element 2a and the second MOS element 2b are packaged using CSP (Chip Scale Package). CSP packaging can reduce the thickness of the first MOS element 2a and the second MOS element 2b, thereby reducing the overall height of the device and meeting the requirements of miniaturization. Preferably, the thickness of the first MOS element 2a and the second MOS element 2b is 0.05mm-0.15mm. One side surface of the CSP packaged MOS element is the drain 23 formed by the back gold layer. By flipping the second MOS element 2b and stacking it on the first surface 21 of the first MOS element 2a, the drains 23 of the two MOS elements are connected in parallel.

[0032] The metal frame 4 is made of conductive metal. In this embodiment, the metal frame 4 is made of copper, which can reduce the path impedance and ensure heat dissipation performance. The upper end of the metal frame 4 extends horizontally and is electrically connected to the source 24 of the second MOS element 2b. The metal frame 4 bends and extends vertically downward along the outer periphery of the two MOS elements, and is connected to the source 24 of the first MOS element 2a through the substrate 1, thereby realizing the parallel connection between the sources 24 of the two MOS elements.

[0033] As can be seen from the above technical solution, by stacking the first MOS element 2a and the second MOS element 2b in the height direction, the drains 23 of the two MOS elements are connected in parallel. Simultaneously, the sources 24 are connected in parallel through the metal frame 4 and the substrate 1, and the gates 25 are connected in parallel through the bonding wire 3 and the substrate 1. This significantly reduces the occupied area while improving current carrying capacity, meeting the requirements of miniaturization. Replacing the copper foil connection of the traditional PCB with the metal frame 4 reduces impedance and improves performance; it also increases the heat dissipation area and improves heat dissipation efficiency.

[0034] In this embodiment, the source electrodes 24 are symmetrically disposed on both sides of the second surface 22, and the gate electrode 25 is located between the two source electrodes 24. The symmetrically distributed source electrode structure optimizes the current transmission path and, together with the metal frame 4, forms a balanced conductive interface, avoiding local current concentration and improving parallel stability and heat distribution uniformity.

[0035] In this embodiment, the metal frame 4 has an opening 41 for exposing the gate 25 of the second MOS element 2b. The bonding wire 3 passes through the opening 41 and connects to the gate 25 of the second MOS element 2b. The opening 41 of the metal frame 4 is designed to provide a channel for the connection between the gate 25 and the bonding wire 3, avoiding interference of the frame with the bonding wire 3, ensuring the reliability of the signal connection of the gate 25, and maintaining the complete coverage of the source 24 by the frame to ensure heat dissipation performance.

[0036] In this embodiment, the substrate 1 is provided with a first electrical connection portion 11 and a second electrical connection portion 12 that are connected. The gate 25 of the first MOS element 2a is electrically connected to the first electrical connection portion 11, and the bonding wire 3 is electrically connected to the second electrical connection portion 12. In specific implementation, the gate 25 of the first MOS element 2a can be soldered to the first electrical connection portion 11, and the bonding wire 3 can be soldered to the second electrical connection portion 12. By providing the first electrical connection portion 11 and the second electrical connection portion 12 on the substrate 1 and connecting them to the gate 25 of the first MOS element 2a and the bonding wire 3 respectively, the parallel connection between the gates 25 of the two MOS elements is realized.

[0037] In this embodiment, the substrate 1 is provided with a third electrical connection portion 13, and the source 24 of the first MOS element 2a and the metal frame 4 are both connected to the third electrical connection portion 13. In specific implementation, soldering can be used to achieve electrical connection between the source 24 of the first MOS element 2a and the metal frame 4 and the third electrical connection portion 13. The metal frame 4 and the source 24 of the first MOS element 2a are simultaneously connected to the third electrical connection portion 13, so that the metal frame 4 and the first MOS element 2a are stably connected to the substrate 1, and the sources 24 of the two MOS elements are connected in parallel.

[0038] The metal frame 4 extends horizontally outward from one end near the substrate 1 to form a welding portion 42. The horizontally extending welding portion 42 increases the contact area with the substrate 1, enhances the mechanical fixation and thermal conductivity interface, reduces the connection point impedance, and makes the connection structure stable and reliable.

[0039] In this embodiment, a plurality of electronic components 6 are provided on the substrate 1, and the plurality of electronic components 6 are encapsulated within the molding portion 5. It is understood that the molding portion 5 can use existing SIP (System-in-Package) packaging materials. The integrated packaging of the electronic components 6 in the molding portion 5 can further reduce the system volume and enhance the overall structural integrity.

[0040] In the description of this utility model, it should be understood that terms such as "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0042] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power semiconductor device of a system-in-a-package, characterized by, It includes a substrate, a first MOS element, a second MOS element, bonding wires, a metal frame, and a molding part; The first MOS element and the second MOS element both include a first surface with a drain and a second surface with a source and a gate. The drain of the first MOS element is opposite to and electrically connected to the drain of the second MOS element. The metal frame is sleeved on the outside of the first MOS element and the second MOS element. One end of the metal frame is electrically connected to the source of the second MOS element, and the other end of the metal frame is electrically connected to the source of the first MOS element through the substrate. One end of the bonding wire is connected to the gate of the second MOS element, and the other end is electrically connected to the gate of the first MOS element through the substrate; The molded portion covers the first MOS element, the second MOS element, the metal frame, the bonding wires, and at least a portion of the substrate to form a package.

2. The system-in-a-package power semiconductor device of claim 1, wherein, The source electrodes are symmetrically disposed on both sides of the second surface, and the gate electrode is located between the two source electrodes.

3. The system-in-a-package power semiconductor device of claim 2, wherein, The metal frame has an opening for exposing the gate of the second MOS element, and the bonding wire passes through the opening and connects to the gate of the second MOS element.

4. The system-in-a-package power semiconductor device of claim 1, wherein, The substrate has a first electrical connection portion and a second electrical connection portion that are connected in a continuous manner. The gate of the first MOS element is electrically connected to the first electrical connection portion, and the bonding wire is electrically connected to the second electrical connection portion.

5. The system-in-a-package power semiconductor device of claim 1, wherein, The substrate is provided with a third electrical connection portion, and the source of the first MOS element and the metal frame are both connected to the third electrical connection portion.

6. The system-in-a-package power semiconductor device of claim 1, wherein, The metal frame extends horizontally outward from one end near the substrate to form a welded section.

7. The system-in-a-package power semiconductor device of claim 1, wherein, The first MOS element and the second MOS element are CSP packages.

8. The system-in-a-package power semiconductor device of claim 1, wherein, The metal frame is made of copper.

9. The system-in-a-package power semiconductor device of claim 1, wherein, The thickness of the first MOS element and the second MOS element is 0.05mm-0.15mm.

10. The system-in-a-package power semiconductor device of claim 1, wherein, The substrate is provided with a plurality of electronic components, and the plurality of electronic components are encapsulated within the molding portion.

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