Packaging structure and sequencing slide

Abstract

The application provides a packaging structure and a sequencing slide. The packaging structure comprises a glass substrate, a plurality of chips and conductive columns. The surface of each chip is provided with a biological functional layer, and the chip is used for biochemical substance analysis. The glass substrate is provided with a plurality of grooves and a through hole surrounding each groove. At least one chip is arranged in each groove, and the biological functional layer is exposed from the opening of the groove. The conductive column is arranged in the through hole, and the conductive column is electrically connected with the chip and electrically leads out the chip. The packaging structure integrates and packages a plurality of chips in the same glass substrate, forms the conductive column in the glass through hole, realizes the electrical leading-out of the chip, forms a large-array planar packaging structure, improves the flux, reduces the cost, and reduces the risk of reagent corrosion of the circuit, short circuit of the circuit and chip failure.

Description

Technical Field

[0001] This application relates to the field of biochemical analysis technology, and in particular to a packaging structure and sequencing substrate. Background Technology

[0002] Currently, gene sequencing typically employs low-throughput targeted sequencing. The sequencing chip is packaged using traditional wire bonding to connect to the circuit board, then the wires are protected with glue, and finally a cover plate is fixed on top of the chip to form a complete device.

[0003] However, current sequencing chips have low throughput, low sequencing efficiency, high error rate, and high cost; in addition, the bonding wires are easily corroded by reagents, and the inside of the chip is easily contaminated by glue, causing chip failure. Utility Model Content

[0004] To address at least one of the above-mentioned shortcomings, it is necessary to propose a packaging structure and a sequencing substrate using this packaging structure.

[0005] In a first aspect, embodiments of this application provide a packaging structure comprising: a glass substrate, a plurality of chips, and conductive pillars. The glass substrate includes a first surface and a second surface disposed opposite to each other. The first surface is recessed toward the second surface to form a plurality of grooves. At least one through-hole is provided through the first surface and the second surface surrounding each groove. Each chip has a biofunctional layer on its surface. The chip is used for biochemical analysis. At least one chip is disposed in each groove, and the biofunctional layer is exposed through the opening of the groove. The conductive pillar is located in the through-hole. One end of the conductive pillar near the first surface is electrically connected to the chip, and one end of the conductive pillar near the second surface is electrically connected to a conductive part.

[0006] In some possible embodiments, the chip includes a functional area and a peripheral area surrounding the functional area, the biofunctional layer is located in the functional area, and the chip also includes pins located in the peripheral area, with one end of the conductive post near the first surface electrically connected to the pins through a conductive layer.

[0007] In some possible embodiments, the surface of the functional area is lower than the surface of the peripheral area, and the surface of the peripheral area is flush with the first surface.

[0008] In some possible embodiments, the encapsulation structure further includes a protective layer disposed on the surface of the conductive layer.

[0009] In some possible embodiments, the second surface is provided with a redistribution layer, the conductive portion is located on the side of the redistribution layer away from the second surface, and the conductive post is electrically connected to the conductive portion through the redistribution layer.

[0010] In some possible embodiments, the redistribution layer includes redistribution lines located on the second surface and an insulating layer located on the surface of the redistribution lines, the redistribution lines being electrically connected to the conductive pillars, and the conductive portion being located on the surface of the insulating layer and electrically connected to the redistribution lines.

[0011] In some possible embodiments, the plurality of chips are arranged in an array.

[0012] In some possible embodiments, a single conductive post is electrically connected to a single chip, and conductive posts connecting different chips are independent of each other.

[0013] In some possible embodiments, the glass substrate having the plurality of said grooves is formed by casting.

[0014] Secondly, embodiments of this application provide a sequencing wafer, which includes a cover plate and the encapsulation structure as described above. The cover plate is disposed on the first surface, and the cover plate and the glass substrate form at least one flow channel, with at least one chip in each flow channel.

[0015] The packaging structure provided in this application integrates multiple chips for biochemical analysis (such as sequencing chips) into the same glass substrate, forming a large-array planar packaging structure. This significantly improves throughput, increases the accuracy of biochemical analysis, and reduces costs. Electrical leads of the chips are achieved by forming through-holes in the glass substrate and conductive pillars within those holes. Therefore, the electrical leads are not exposed, effectively reducing the risks of reagent corrosion, short circuits, and chip failure. The electrical lead-out method does not use adhesive, further reducing the impact of adhesive on the chip's biochemical performance and improving the accuracy of biochemical analysis. Furthermore, multiple chips in the packaging structure can be independently controlled, and the failure of a few chips will not affect the use of the entire large array. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the packaging structure according to an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the structure of a chip according to an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the packaging structure according to another embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the structure of a glass substrate according to an embodiment of this application.

[0021] Figure 5 In order to be in Figure 4 A schematic diagram of the structure in which the chip is mounted in the groove.

[0022] Figure 6 In order to be in Figure 5 A schematic diagram of a structure in which through holes are formed around the groove.

[0023] Figure 7 In order to be in Figure 6 A schematic diagram of a structure in which a conductive pillar is formed inside a through-hole.

[0024] Figure 8 In order to be in Figure 7 A schematic diagram of a structure in which a conductive layer is formed on the first surface of a glass substrate.

[0025] Figure 9 In order to be in Figure 8 A schematic diagram of a structure in which a protective layer is formed on the surface of the conductive layer.

[0026] Figure 10 In order to be in Figure 9 A schematic diagram of a structure in which a redistribution layer is formed on the second surface of a glass substrate.

[0027] Figure 11 This is a schematic diagram of the structure of a sequencing slide provided in one embodiment of this application.

[0028] Explanation of main component symbols The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that when a component is described as "fixed to" or "mounted to" another component, it can be directly on the other component or may be interspersed with an intermediate component. When a component is described as "set to" another component, it can be directly set on the other component or may be interspersed with an intermediate component. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0031] Please see Figure 1 As shown in the figure, this application embodiment provides a packaging structure 100, which includes: multiple chips 1, a glass substrate 2, conductive pillars 3, and conductive portions 7. Each chip 1 has a biofunctional layer 11 on its surface, and the chip 1 is used for biochemical analysis (e.g., gene sequencing, where the chip 1 can be a sequencing chip). The glass substrate 2 includes a first surface 21 and a second surface 22 disposed opposite to each other. The first surface 21 is recessed towards the second surface 22 to form multiple grooves 23. At least one through-hole 24 is provided around each groove 23, and at least one chip 1 is disposed in each groove 23. The biofunctional layer 11 is exposed through the opening of the groove 23. The conductive pillar 3 is located in the through-hole 24. One end of the conductive pillar 3 near the first surface 21 is electrically connected to the chip 1, and the other end of the conductive pillar 3 near the second surface 22 is electrically connected to the conductive portion 7. The conductive portion 7 can be connected to an external circuit, thereby realizing the electrical lead-out of the chip 1.

[0032] Understandably, in the process of setting the electrical connection between the conductive post 3 and the chip 1, a single conductive post 3 is electrically connected to a single chip 1, that is, a single chip 1 is electrically connected to a single conductive post 3 located around the chip 1. The conductive posts 3 connecting different chips 1 are independent of each other, that is, the chips 1 are electrically insulated from each other, so that multiple chips 1 will not interfere with each other, and thus the independent control of multiple chips 1 can be realized.

[0033] Please see Figure 1 and Figure 2As shown, the side of chip 1 with the biofunctional layer 11 is defined as the front side 14, and the side opposite to the front side 14 is defined as the back side 15. After chip 1 is mounted in the groove 23 of glass substrate 2, the front side 14 of chip 1 is exposed, facilitating the loading of samples into the biofunctional layer 11. Specifically, chip 1 for biochemical analysis, such as a sequencing chip, mainly includes the biofunctional layer 11 and a sensor layer 12 located below the biofunctional layer 11. The biofunctional layer 11 is used to fix the sample to be tested (e.g., biological material), and the biofunctional layer 11 is exposed from the groove 23 to facilitate the loading of the sample to be tested. The sensor layer 12 is configured to recognize the signal generated after the sample to be tested reacts with the corresponding reagent. For example, the sensor layer 12 may include one or more image sensors, and may also include other sensors.

[0034] In some embodiments, the biofunctional layer 11 may include a plurality of microstructures (not shown) recessed toward the sensor layer 12, which may be used to immobilize the sample to be tested.

[0035] like Figure 1 and Figure 2 As shown, the chip 1 includes a functional area A and a peripheral area B surrounding the functional area A. The biofunctional layer 11 is located in the functional area A. The chip 1 also includes pins 13 located in the peripheral area B. One end of the conductive post 3 near the first surface 21 is electrically connected to the pin 13 through a conductive layer 5. That is, the front surface 14 of the chip 1 has pins 13 around its periphery, which facilitates the electrical connection between the conductive post 3 and the chip 1 during the formation of the conductive post 3.

[0036] In some embodiments, the surfaces of functional area A and peripheral area B are both flush with the first surface 21, meaning the front surface 14 of chip 1 is a plane. It is understood that in other embodiments, such as... Figure 3 As shown, the surface of functional region A is lower than the surface of peripheral region B, and the surface of peripheral region B is flush with the first surface 21. That is, the front surface 14 of chip 1 is not flat, but rather a channel cavity 16 is formed by a recess in the biofunctional layer 11 portion facing the back surface 15. The channel cavity 16 has multiple array sites near the bottom surface of the sensor layer 12, which are used to fix the sample to be detected. By setting the surface of peripheral region B to be flush with the first surface 21, a flat surface is provided for the conductive layer 5. By setting the surface of functional region A to be lower than peripheral region B, a channel cavity 16 with a certain depth is formed, which can accommodate a larger volume of sample and also confine the sample within the channel cavity 16, improving the binding efficiency between the array sites and the sample.

[0037] In some embodiments, multiple chips 1 can be arranged in an array, and multiple chips 1 can also have different functions. Multiple chips 1 are mounted in a glass substrate 2 to form a large array planar packaging structure 100, which can significantly improve the throughput of biochemical analysis (e.g., sequencing throughput), increase the diversity of functions, reduce costs, and be applicable to more application scenarios.

[0038] Please refer to it again. Figure 1 As shown, the glass substrate 2 with grooves 23 can be pre-formed by casting. After the chip 1 is mounted in the grooves 23, a through-hole 24 can be formed through the first surface 21 and the second surface 22 using the TGV process. The depth of the grooves 23 can be designed according to the thickness of the mounted chip 1. By directly forming the grooves 23 for mounting the chip 1 on the glass substrate 2, the chip 1 is directly mounted in the grooves 23 during the packaging process, simplifying the packaging process, reducing costs, and improving the reliability of the packaging structure 100 due to the high strength and flatness of the glass substrate 2.

[0039] Please refer to it again. Figure 1 As shown, a protective layer 6 is provided on the surface of the conductive layer 5. By adding a protective layer 6 locally, the conductive layer 5 can be protected, avoiding the risk of short circuits caused by reagent corrosion during use. It is understandable that if the conductive layer 5 does not completely cover the pin 13 during electrical connection, the protective layer 6 can also cover the pin 13 to prevent it from being corroded by reagents.

[0040] Please refer to it again. Figure 1 As shown, the conductive pillar 3 can be made of metal (e.g., copper) or conductive paste. The conductive pillar 3 can be formed in the through hole 24 by electroplating metal or by filling and curing conductive paste.

[0041] Please refer to it again. Figure 1 As shown, the second surface 22 of the glass substrate 2 is provided with a redistribution layer 4, and the conductive portion 7 is located on the side of the redistribution layer 4 away from the second surface 22. The conductive post 3 is electrically connected to the conductive portion 7 through the redistribution layer 4. Furthermore, the conductive portion 7 can be electrically connected to the motherboard, thereby realizing the electrical lead-out of the chip 1.

[0042] In some embodiments, the redistribution layer 4 includes redistribution lines 41 located on the second surface 22 and an insulating layer 42 located on the surface of the redistribution lines 41. The redistribution lines 41 are electrically connected to the conductive posts 3, and the conductive portion 7 is located on the surface of the insulating layer 42 and is electrically connected to the redistribution lines 41. The redistribution lines 41 may be one layer or multiple layers. When multiple layers of redistribution lines 41 are included, an insulating layer is provided between adjacent redistribution lines 41.

[0043] In some embodiments, the conductive portion 7 may be a solder ball.

[0044] Please see Figures 4 to 10 As shown, the method for preparing the aforementioned packaging structure 100 includes the following steps: Step 1, as follows Figure 4 As shown, a glass substrate 2 with a plurality of grooves 23 is formed. The glass substrate 2 includes a first surface 21 and a second surface 22 disposed opposite to each other, wherein the grooves 23 are formed by recessing from the first surface 21 toward the second surface 22.

[0045] Specifically, the glass substrate 2 with grooves 23 can be formed by casting process. Understandably, the grooves 23 can also be formed by other methods (such as laser grooving).

[0046] Step 2, as follows Figure 5 As shown, at least one chip 1 is mounted in each groove 23, with the back side 15 of the chip 1 facing down and attached to the groove 23. The front side 14 of the chip 1 has a biofunctional layer 11, which is exposed through the opening of the groove 23.

[0047] The wafer has multiple chips 1. When mounting the chips 1, the wafer needs to be cut to separate the multiple chips 1. In addition, the chips 1 can be mounted in the groove 23 with an adhesive layer.

[0048] Step 3, as follows Figure 6 As shown, a through hole 24 is formed around each groove 23, penetrating the first surface 21 and the second surface 22.

[0049] Among them, the through holes 24 on the glass substrate 2 can be formed by processes such as laser induction, laser drilling, and ion beam etching (IBE) to form TGV holes.

[0050] Step 4, as follows Figures 7 to 9 As shown, a conductive post 3 is formed in the through hole 24, and the conductive post 3 is electrically connected to the chip 1.

[0051] Specifically, the method for forming the conductive pillar 3 includes the following steps: Step 1, as follows Figure 7As shown, a dielectric layer 10 is formed on the first surface 21 of the glass substrate 2, and the dielectric layer 10 extends to the surface of the biofunctional layer 11.

[0052] Extending the dielectric layer 10 to the biological functional layer 11 can serve a protective function, preventing damage to the biological functional layer 11 during subsequent patterning and electroplating processes.

[0053] Step 2, as follows Figure 7 As shown, the patterned dielectric layer 10 exposes the via 24 and the pins 13 of the chip 1.

[0054] Specifically, an opening 20 is formed at the position of the via 24 in the dielectric layer 10, so that the via 24 and the pin 13 of the chip 1 are exposed through the opening 20.

[0055] The patterning of the dielectric layer 10 may include steps such as coating, exposure and development, and etching.

[0056] Step 3, as follows Figure 7 and Figure 8 As shown, a conductive post 3 is formed in the through hole 24, and a conductive layer 5 is formed on the first surface 21. The conductive layer 5 electrically connects the conductive post 3 and the pin 13.

[0057] Conductive pillars 3 can be formed within the through-hole 24 using methods such as physical vapor deposition, chemical vapor deposition, or electroplating. Alternatively, conductive pillars 3 can also be formed by filling the through-hole 24 with conductive paste.

[0058] In some embodiments, before forming the conductive pillar 3, a seed layer may be formed on the inner wall of the through hole 24 to improve the bonding force between the conductive pillar 3 and the glass substrate 2.

[0059] Step 4, as follows Figure 9 As shown, a protective layer 6 is formed inside the opening 20, and the protective layer 6 covers the conductive layer 5.

[0060] A protective layer 6 is formed within the opening 20 to cover the conductive layer 5, thereby reducing the risk of the conductive layer 5 being corroded by reagents. Understandably, the protective layer 6 can also cover the exposed pins 13.

[0061] After the conductive layer 5 is formed, the dielectric layer 10 can be removed to expose the biofunctional layer 11. If the biofunctional layer 11 needs to be cleaned, it can be done during this step or after the entire encapsulation structure is fabricated.

[0062] Step 5, as follows Figure 10 As shown, a redistributed circuit 41 is formed on the second surface 22 of the glass substrate 2, and the redistributed circuit 41 is electrically connected to the conductive pillar 3.

[0063] As mentioned above, the redistribution circuit 41 may include one layer of circuit or multiple layers of circuit, and the specific circuit formation method may be electroplating and etching.

[0064] Step 6, as follows Figure 10 As shown, an insulating layer 42 is formed on the surface of the redistributed line 41 to obtain the redistributed line layer 4 located on the second surface 22.

[0065] Step 7, as follows Figure 1 As shown, a conductive portion 7 is formed on the surface of the insulating layer 42, and the conductive portion 7 is electrically connected to the redistributed circuit 41, thereby obtaining the encapsulation structure 100.

[0066] The conductive part 7 can be a solder ball, which can be used to achieve further electrical connection between the package structure 100 and the motherboard.

[0067] Please see Figure 11 As shown, this application embodiment also provides a sequencing substrate 200, which belongs to a specific application scenario of the aforementioned packaging structure 100. The sequencing substrate 200 includes a cover plate 201 and the packaging structure 100 as described above. The cover plate 201 is disposed on the first surface 21 of the glass substrate 2, and the cover plate 201 and the glass substrate 2 form at least one flow channel 30. Each flow channel 30 contains at least one chip 1. A liquid inlet 202 may be provided on the cover plate 201, through which sequencing samples can be loaded into the flow channel 30. It is understood that the entire packaging structure 100 can constitute one flow channel 30 or multiple parallel flow channels 30. For example, according to the function of the chip 1, chips 1 with different functions can be separated into different flow channels 30 to achieve different functions.

[0068] Understandably, this method can also be used for chip packaging in applications such as CMOS sensors, nanopore sequencing, CPUs, and GPUs to improve product performance.

[0069] The packaging structure 100 provided in this application integrates multiple biochemical analysis chips 1 (e.g., sequencing chips) within a glass substrate 2 with specific grooves 23, forming a large-array planar packaging structure 100. This significantly improves throughput, increases the accuracy of biochemical analysis, and reduces costs. Electrical leads of the chips 1 are achieved by forming through-holes 24 on the glass substrate 2 and conductive pillars 3 within those through-holes 24. Therefore, the electrical leads of the chips 1 are not exposed, effectively reducing the risks of reagent corrosion, short circuits, and chip 1 failure. The electrical lead-out method of the chips 1 does not use glue, further reducing the impact of glue on the biochemical performance of the chips 1 and improving the accuracy of biochemical analysis. The circuit connections of multiple chips 1 in the packaging structure 100 do not affect each other; multiple chips 1 can be independently controlled. The failure of a few chips 1 will not affect the use of the entire large array, and the independent control of multiple chips 1 can meet the needs of different reaction processes. In addition, multiple chips 1 can have different functions, thereby enhancing the functional diversity of the package structure 100 and providing room for future upgrades.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A packaging structure, characterized in that, include: A glass substrate includes a first surface and a second surface disposed opposite to each other. The first surface is recessed toward the second surface to form a plurality of grooves, and at least one through hole is provided through the first surface and the second surface around each groove. Multiple chips, each chip having a biofunctional layer on its surface, the chips being used for biochemical analysis, each groove containing at least one chip, the biofunctional layer being exposed through an opening in the groove; as well as A conductive post is located inside the through hole. One end of the conductive post near the first surface is electrically connected to the chip, and the other end of the conductive post near the second surface is electrically connected to a conductive part.

2. The packaging structure as described in claim 1, characterized in that, The chip includes a functional area and a peripheral area surrounding the functional area. The biofunctional layer is located in the functional area. The chip also includes pins located in the peripheral area. One end of the conductive post near the first surface is electrically connected to the pins through a conductive layer.

3. The packaging structure as described in claim 2, characterized in that, The surface of the functional area is lower than the surface of the peripheral area, and the surface of the peripheral area is flush with the first surface.

4. The packaging structure as described in claim 2, characterized in that, The encapsulation structure also includes a protective layer disposed on the surface of the conductive layer.

5. The packaging structure as described in claim 1, characterized in that, The second surface is provided with a redistribution layer, the conductive part is located on the side of the redistribution layer away from the second surface, and the conductive post is electrically connected to the conductive part through the redistribution layer.

6. The packaging structure as described in claim 5, characterized in that, The redistribution layer includes redistribution lines located on the second surface and an insulating layer located on the surface of the redistribution lines. The redistribution lines are electrically connected to the conductive pillars, and the conductive portion is located on the surface of the insulating layer and is electrically connected to the redistribution lines.

7. The packaging structure as described in claim 1, characterized in that, The multiple chips are arranged in an array.

8. The packaging structure as described in claim 1, characterized in that, Each of the conductive posts is electrically connected to a single chip, and the conductive posts connecting different chips are independent of each other.

9. The packaging structure as described in claim 1, characterized in that, The glass substrate having multiple grooves is formed by casting.

10. A sequencing slide, characterized in that, The package includes a cover plate and a packaging structure as described in any one of claims 1 to 9, wherein the cover plate is disposed on the first surface and the cover plate and the glass substrate form at least one flow channel, and each flow channel contains at least one of the chips.

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