Test board for PCB lamination anti-reverse monitoring

Abstract

The present disclosure provides a test board for PCB lamination anti-reverse monitoring, the test board comprising N-1 prepregs, N substrates and a test strip group, the test strip group comprising a top test strip, a bottom test strip and 2N-2 intermediate test strips; the top test strip is provided with an impedance detection A point and 2N-1 impedance detection B points, each intermediate test strip is provided with a signal contact line, and the bottom test strip is provided with a bottom signal line; the test board is provided with the top test strip, the bottom test strip and the intermediate test strip, and the top test strip, the bottom test strip and the intermediate test strip are designed with signal lines, so that two impedance test needle contacts two contact points of the top test strip, thereby testing the impedance values of different layers of test strips, especially the impedance values of two adjacent layers of test strips; the impedance values are affected by the spacing of two test strips, whether there is a wrong stacking situation can be confirmed according to the impedance values between the two test strips, and the product failure rate is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of PCB board testing technology, and in particular to a test board for PCB stack-up anti-reverse monitoring. Background Technology

[0002] PCB (Printed Circuit Board) stack-up design is the central part of circuit board manufacturing, directly affecting signal integrity, power integrity, electromagnetic compatibility (EMC), and manufacturing costs.

[0003] To ensure the accuracy of PCB substrate stacking, a step coupon pattern is generally used as a detection method. Different geometric shapes (such as rectangles, triangles, etc.) are designed with staggered arrangement near the edge of the substrate, and then stacked one by one to form the PCB board. If each PCB substrate is stacked correctly, the cross-section of the pattern should show a continuous step shape; if there is a misalignment of the PCB substrate, it indicates that there is substrate stacking misalignment, and the cross-section of the pattern will show breakage, misalignment, or overlap.

[0004] Currently, the inspection of PCB substrate stack-up structure still relies on manual inspection, such as direct observation by the human eye or observation with a magnifying glass. This method is easily affected by subjective factors, such as eyesight, human fatigue, and human experience. Consequently, the reliability of observing the substrate stack-up by the human eye is low, and there is a risk of producing defective products. Utility Model Content

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a test board for PCB stack-up anti-reverse monitoring that determines the presence of stack-up misalignment through impedance testing without human visual inspection.

[0006] The purpose of this disclosure is achieved through the following technical solution:

[0007] A test board for PCB stack-up anti-reverse monitoring, comprising:

[0008] N-1 prepregs, N substrates, and a test strip group, wherein the test strip group includes a top test strip, a bottom test strip, and 2N-2 intermediate test strips; the substrates and the prepregs are alternately stacked, and adjacent substrates and prepregs are separated by an intermediate test strip; the top test strip is located on the outside of the top substrate among the N substrates, and the bottom test strip is located on the outside of the bottom substrate among the N substrates; the top test strip has one impedance detection point A and 2N-1 impedance detection points B; each intermediate test strip has a signal contact line, and the bottom test strip has a bottom signal line; the signal contact line of each intermediate test strip is electrically connected to one impedance detection point B, and the bottom signal line is electrically connected to one impedance detection point B; wherein, N≥2, and N is an integer, and the impedance detection point A is used to perform impedance testing with any impedance detection point B to obtain the impedance of the corresponding board layer.

[0009] In one embodiment, the top test strip, the bottom test strip, and the middle test strip are all disposed on one edge of the substrate.

[0010] In one embodiment, a plurality of the impedance detection points B are arranged adjacent to the edge portion of the top test strip.

[0011] In one embodiment, the plurality of impedance detection points B are arranged in a straight line on the top test bar.

[0012] In one embodiment, the test strip is a copper strip.

[0013] In one embodiment, the thickness of the top test strip and / or the bottom test strip is 32μm-35μm.

[0014] In one embodiment, the thickness of each intermediate test strip is 32μm-35μm.

[0015] In one embodiment, the thickness of the prepreg is 0.1mm-0.15mm.

[0016] In one embodiment, the thickness of the substrate is 0.6 mm to 0.8 mm.

[0017] Compared with the prior art, this disclosure has at least the following advantages:

[0018] The aforementioned test board for PCB stack-up anti-reverse monitoring is equipped with top test strips, bottom test strips, and intermediate test strips. Signal lines are designed for these top, bottom, and intermediate test strips to allow two impedance test probes to contact the two contact points of the top test strip, thereby testing the impedance values ​​of test strips in different layers, especially adjacent test strips. Since the impedance value is affected by the spacing between the two test strips, the presence of board misalignment can be confirmed based on the impedance value between the two test strips. This eliminates the need for visual inspection, and electrical testing can significantly reduce the product defect rate and ensure the production quality of the PCB board. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a test board used for PCB stack-up anti-reverse monitoring in one embodiment;

[0021] Figure 2 for Figure 1 The diagram shows the specific structure of the test board used for PCB stack-up anti-reverse monitoring.

[0022] Figure 3 for Figure 1 The diagram shows the structure of the test strip group in the test board used for PCB stack-up anti-reverse monitoring.

[0023] Reference numerals: 10, test plate; 100, prepreg; 200, substrate; 300, test strip set; 310, top test strip; 311, impedance detection point A; 312, impedance detection point B; 320, middle test strip; 321, signal contact line; 330, bottom test strip; 331, bottom signal line. Detailed Implementation

[0024] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.

[0025] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] To better understand the technical solutions and beneficial effects of this disclosure, the following detailed description is provided in conjunction with specific embodiments:

[0028] Please see Figure 1 This is a test board 10 for PCB stack-up anti-reverse monitoring according to an embodiment of the present invention. The test board 10 is used to detect the impedance values ​​of its two test strips using an impedance detection device to confirm whether there is a stack-up error. The test board 10 includes N-1 prepreg sheets 100, N substrates 200, and a test strip set 300. (Combined with...) Figure 2 and Figure 3 As shown, the test strip group 300 includes a top test strip 310, 2N-2 intermediate test strips 320, and a bottom test strip 330. The substrate 200 and the prepreg 100 are alternately stacked, with adjacent substrates 200 and prepregs separated by an intermediate test strip 320. The top test strip 310 is located on the outer side of the top substrate among the N substrates 200, and the bottom test strip 330 is located on the outer side of the bottom substrate among the N substrates 200. That is, one substrate 200 has a top test strip 310 and an intermediate test strip 320 on each side, while another substrate 200 has... The test strip 330 has a bottom test strip 330 and a middle test strip 320. The top test strip 310 has an impedance detection point A 311 and 2N-1 impedance detection points B 312. Each middle test strip 320 has a signal contact line 321, and the bottom test strip 330 has a bottom signal line 331. The signal contact line 321 of each middle test strip 320 is electrically connected to an impedance detection point B 312, and the bottom signal line 331 is electrically connected to an impedance detection point B 312. Wherein, N≥2, and N is an integer. The impedance detection point A 311 is used to perform impedance testing with any impedance detection point B 312 to obtain the impedance of the corresponding board layer.

[0029] The aforementioned test board 10 for PCB stack-up anti-reverse monitoring features a top test strip 310, a bottom test strip 330, and several intermediate test strips 320. Signal lines are designed for these test strips 310, 330, and 320, allowing two impedance test probes to contact the two contact points of the top test strip 310. This enables testing of the impedance values ​​of test strips in different layers, particularly adjacent layers. Since the impedance value is affected by the spacing between the two test strips, the presence of board misalignment can be confirmed based on the impedance value between the two test strips. This eliminates the need for visual inspection, significantly reducing product defect rates and ensuring PCB production quality through electrical testing. Furthermore, the aforementioned test strips are coupon strips used for impedance testing.

[0030] It can be understood that impedance detection point A 311 is electrically connected to any impedance detection point B 312 through the conductive part of the substrate 200, so that when the two impedance test probes test the impedance of any board layer, a test circuit is formed between impedance detection point A 311 and any impedance detection point B 312, accurately obtaining the current impedance value, and thus determining whether there is a misalignment of the board layers.

[0031] To facilitate understanding of this solution by those skilled in the art, in one embodiment, N=3, which indicates that the structure is a 6-layer PCB board stack-up structure; and,

[0032] like Figures 1 to 3As shown, in one embodiment, the test board 10 for PCB stack-up anti-reverse monitoring includes two prepregs 100, three substrates 200, and a test strip group 300. The test strip group 300 includes a top test strip 310, four intermediate test strips 320, and a bottom test strip 330. The top test strip 310 has an impedance detection A point 311 and five impedance detection B points 312. Each intermediate test strip 320 has a signal contact line 321. The bottom test strip 330 has a bottom signal line 331. The five impedance detection B points 312 are electrically connected to the signal contact lines 321 of the corresponding intermediate test strips 320, and one of the impedance detection B points 312 is electrically connected to the bottom signal line 331. Furthermore, the top test strip 310 is the L01 layer test strip, the middle test strips 320 are the L02, L03, L04 and L05 layer test strips respectively, and the bottom test strip 330 is the L06 layer test strip. The L02, L03, L04 and L05 layer test strips all have corresponding signal contact lines 321, and the L06 layer test strip has a bottom signal line 331. The corresponding signal contact line 321 is electrically connected to the corresponding impedance detection point B 312, and the bottom signal line 331 is electrically connected to an impedance detection point B 312. Both impedance detection points A (311) and B (312) are used to contact the impedance test probes to collect the impedance value between two test strips. This helps determine if there are any PCB board stacking errors. For example, when collecting the impedance value between test strips L01 and L02, if the stacking is correct, the impedance value between them is 48Ω. However, if the L02 test strip is incorrectly stacked, such as when it is misaligned with L03, the impedance value between them is 75Ω. Since this impedance value varies due to the shielding layer between the test strips, it confirms that the L02 test strip is misaligned. Similarly, the impedance values ​​between L01 and L03, and between L01 and L04, can also be tested to determine the impedance of the corresponding board components.

[0033] In other embodiments, the test board 10 for PCB stack-up anti-reverse monitoring can also adopt a 4-layer PCB stack-up structure, an 8-layer PCB stack-up structure, a 10-layer PCB stack-up structure, etc. The specific implementation methods of other embodiments will not be described here.

[0034] In one embodiment, the top test strip 310, bottom test strip 330, and middle test strip 320 are all disposed at one edge of the substrate 200 (not shown in the figures) to facilitate the impedance testing probe to test the impedance value between the two test strips along the entire edge of the structure without interfering with components in other locations, thus ensuring the accuracy of the impedance value acquisition. Furthermore, portions of the top test strip 310, bottom test strip 330, and middle test strip 320 extend from the edge of the substrate 200, i.e., the edge or process edge, so that the test strips can be trimmed after production without affecting the size and function of the PCB board.

[0035] like Figure 3 As shown, in one embodiment, multiple impedance detection points B 312 are positioned near the edge of the top test strip 310, ensuring that the structure does not interfere with other locations on the substrate 200 during impedance testing. Furthermore, the multiple impedance detection points B 312 are arranged in a straight line on the top test strip 310, resulting in a more standardized arrangement of the test points and facilitating impedance testing.

[0036] In one embodiment, the top test strip 310, and / or the bottom test strip 330, and / or the middle test strip 320 are copper strips. Since copper has good conductivity, whether there is a misalignment of the plates during impedance testing can be reflected in the test interface in the form of an electrical signal, rather than by the human eye.

[0037] In one embodiment, the thickness of the top test strip 310 and / or the bottom test strip 330 is 32 μm-35 μm. In this embodiment, the thickness of the top test strip 310 and / or the bottom test strip 330 is 34.287 μm, i.e., 1 oz.

[0038] In one embodiment, the thickness of each intermediate test strip 320 is 32μm-35μm. In this embodiment, the thickness of the intermediate test strip 320 is 34.287μm, which is 1oz.

[0039] In one embodiment, the thickness of the prepreg 100 is 0.1 mm to 0.15 mm. In this embodiment, the thickness of the prepreg 100 is 0.12 mm.

[0040] In one embodiment, the thickness of the substrate 200 is 0.6 mm to 0.8 mm. In this embodiment, the thickness of the substrate 200 is 0.6 mm.

[0041] This disclosure also provides a PCB board, including a test board 10 for PCB stack-up anti-reverse monitoring according to any of the above embodiments.

[0042] Compared with the prior art, this disclosure has at least the following advantages:

[0043] The aforementioned test board 10 for PCB stack-up anti-reverse monitoring is equipped with a top test strip 310, a bottom test strip 330, and an intermediate test strip 320. Signal lines are designed for the top test strip 310, the bottom test strip 330, and the intermediate test strip 320 to allow two impedance test probes to contact the two contact points of the top test strip 310, thereby testing the test strips of different layers, especially the impedance values ​​of adjacent test strips. Since the impedance value is affected by the distance between the two test strips, the presence of board misalignment can be confirmed based on the impedance value between the two test strips. This eliminates the need for visual inspection, and electrical testing can significantly reduce the product defect rate and ensure the production quality of the PCB board.

[0044] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A test board for PCB lamination anti-reverse monitoring, characterized in that, include: N-1 prepregs, N substrates, and test strip sets, wherein the test strip sets include a top test strip, a bottom test strip, and 2N-2 middle test strips; The substrate and the prepreg are alternately stacked, and adjacent substrates and prepregs are separated by an intermediate test strip. The top test strip is located on the outside of the top substrate among the N substrates, and the bottom test strip is located on the outside of the bottom substrate among the N substrates. The top test strip has one impedance detection point A and 2N-1 impedance detection points B. Each of the middle test strips has a signal contact line, and the bottom test strip has a bottom signal line. The signal contact line of each of the middle test strips is electrically connected to one of the impedance detection points B, and the bottom signal line is electrically connected to one of the impedance detection points B. Wherein, N≥2, and N is an integer. The impedance detection point A is used to perform impedance testing with any one of the impedance detection points B to obtain the impedance of the corresponding board layer.

2. The test board for PCB stack-up anti-reverse monitoring according to claim 1, wherein, The top test strip, the bottom test strip, and the middle test strip are all disposed on one edge of the substrate.

3. The test board for PCB stack-up anti-reverse monitoring according to claim 1, wherein, Multiple impedance detection points B are positioned adjacent to the edge portion of the top test strip.

4. The test board for PCB stack-up anti-reverse monitoring according to claim 3, wherein, The multiple impedance detection points B are arranged in a straight line on the top test bar.

5. The test board for PCB stack-up anti-tum monitoring of claim 1, wherein, The top test strip, and / or the bottom test strip, and / or the middle test strip are copper strips.

6. The test board for PCB stack-up anti-tum-back monitoring of claim 1, wherein, The thickness of the top test strip and / or the bottom test strip is 32μm-35μm.

7. The test board for PCB stack-up anti-reverse monitoring according to claim 6, wherein, The thickness of each intermediate test strip is 32μm-35μm.

8. The test board for PCB stack-up anti-tum monitoring of claim 1, wherein, The thickness of the prepreg is 0.1mm-0.15mm.

9. The test board for PCB stack-up anti-tum monitoring of claim 1, wherein, The thickness of the substrate is 0.6mm-0.8mm.

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