IGBT double pulse test system based on TMS320F28377D

Abstract

The utility model discloses a kind of IGBT double-pulse test system based on TMS320F28377D, voltage division capacitor group and one word type three-level switching bridge arm are parallelly connected between direct-current power supply positive and negative pole, capacitor group neutral point is connected bridge arm middle node through clamping diode group, power conversion circuit is respectively TMS320F28377D chip and the power supply of PWM drive circuit;DC bus voltage sampling circuit comprising voltage division resistor and operational amplifier, output is accessed the ADC interface of PWM generation circuit, chip output signal is sent to PWM drive circuit, driving signal positive and negative terminal is connected respectively one word type three-level double-pulse loop IGBT's gate and emitter;Communication circuit connects chip and configuration screen.

Description

Technical Field

[0001] This utility model belongs to the fields of power electronics technology and analog circuit technology, specifically relating to an IGBT double-pulse test system based on TMS320F28377D. Background Technology

[0002] With the rapid development of power electronics technology, insulated gate bipolar transistors (IGBTs) and silicon carbide field-effect transistors (MOSFETs) are widely used in new energy vehicle electric drive systems, photovoltaic inverters, industrial frequency converters and other fields due to their advantages such as high voltage, high current, easy driving and wide operating frequency.

[0003] In IGBT / silicon carbide applications, device protection is crucial. Due to the high cost of these devices, damage not only increases costs but also severely impacts normal equipment operation. Furthermore, IGBT / silicon carbide applications are diverse and operate in complex environments, demanding extremely high reliability. Therefore, performing double-pulse testing on IGBT / silicon carbide devices during the design phase is essential. This testing allows for the selection of appropriate drive circuits and turn-on / turn-off resistors, optimizing device performance.

[0004] Existing dual-pulse test systems suffer from problems such as complex operation, poor compatibility, and insufficient test accuracy, making it difficult to meet the testing needs of different types of devices and complex topologies. Utility Model Content

[0005] The purpose of this invention is to overcome the problems of complex operation, poor compatibility and insufficient testing accuracy of existing dual-pulse test systems, and to propose an IGBT dual-pulse test system based on TMS320F28377D.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: An IGBT dual-pulse test system based on TMS320F28377D includes an IGBT dual-pulse circuit and a control circuit, wherein the IGBT dual-pulse circuit and the control circuit are connected. The control circuit includes a power conversion circuit, a DC bus voltage sampling circuit, a PWM generation circuit, a PWM drive circuit, and a communication circuit. The PWM generation circuit includes a TMS320F28377D chip. The power conversion circuit is connected to both the TMS320F28377D chip and the PWM drive circuit. The DC bus voltage sampling circuit consists of a voltage divider resistor and an operational amplifier. The voltage divider resistor is connected in parallel between the positive and negative terminals of the DC power supply. The output of the operational amplifier is connected to the ADC interface of the PWM generation circuit. The signal output of the TMS320F28377D chip is connected to the signal input of the PWM drive circuit. One drive signal output of the PWM drive circuit is connected to one IGBT in the IGBT double pulse loop. The positive output of the drive signal is connected to the gate of the IGBT, and the negative output of the drive signal is connected to the emitter of the IGBT. The communication circuit is connected to both the TMS320F28377D chip and the configuration panel.

[0007] Furthermore, the input voltage of the power conversion circuit is +24V, and the output voltage of the power conversion circuit is +15V, +5V, or +3.3V.

[0008] Furthermore, the power supply pins of the TMS320F28377D chip are connected to the +3.3V output voltage of the power conversion circuit, and the signal output terminals of the TMS320F28377D chip output four 3.3V PWM signals.

[0009] Furthermore, the IGBT dual-pulse circuit adopts a one-line three-level IGBT dual-pulse circuit; The single-line three-level IGBT dual-pulse circuit includes a DC power supply, a voltage divider capacitor bank, a single-line three-level IGBT switching bridge arm, and a clamping diode bank; The voltage divider capacitor bank is connected in parallel between the positive and negative terminals of the DC power supply, and the three-level IGBT switch bridge arm is connected in parallel between the positive and negative terminals of the DC power supply. The neutral point of the voltage divider capacitor bank is connected to the middle node of the three-level switch bridge arm through the clamping diode bank. The single-line three-level IGBT switch bridge arm is composed of IGBT1, IGBT2, IGBT3 and IGBT4 connected in series. IGBT1, IGBT2, IGBT3 and IGBT4 are arranged linearly from the positive terminal to the negative terminal of the DC power supply. The voltage divider capacitor bank consists of a first capacitor C1 and a second capacitor C2 connected in series, and the clamping diode bank consists of a first clamping diode D1 and a second clamping diode D2 connected in series.

[0010] Furthermore, the first terminal of the first capacitor C1 is connected to the positive terminal of the DC power supply, and the second terminal of the second capacitor C2 is connected to the negative terminal of the DC power supply. The second terminal of capacitor C1 is connected to the first terminal of capacitor C2, serving as the neutral point of the voltage divider capacitor bank. The emitter of IGBT1 is connected to the collector of IGBT2, serving as the first intermediate node of the IGBT 1-type three-level IGBT switch bridge arm. The emitter of IGBT2 is connected to the collector of IGBT3, serving as the loop output terminal of the one-line three-level IGBT switch bridge arm. The emitter of IGBT3 is connected to the collector of IGBT4, serving as the second intermediate node of the IGBT 3-level IGBT switch bridge arm.

[0011] Furthermore, the anode of the first clamping diode D1 is connected to the first intermediate node of the IGBT switch bridge arm, and the cathode of the first clamping diode D1 is connected to the neutral point of the voltage divider capacitor bank. The anode of the second clamping diode D2 is connected to the second intermediate node of the IGBT switch arm, and the cathode of the second clamping diode D2 is connected to the neutral point of the voltage divider capacitor bank.

[0012] Furthermore, the single-line three-level IGBT dual-pulse circuit also includes a hollow inductor. One end of the hollow inductor is connected to the circuit output terminal of the single-line three-level IGBT switching bridge arm, and the other end of the hollow inductor is connected to the external load terminal.

[0013] Furthermore, the collector of IGBT1 is connected to the positive terminal of the DC power supply, and the emitter of IGBT4 is connected to the negative terminal of the DC power supply.

[0014] Furthermore, the PWM drive circuit includes an SN74LVC16T245 level converter, a CD4504 level converter, a push-pull circuit, an isolation transformer, and a 1EDI60N12AF driver chip connected in sequence. The 1EDI60N12AF chip includes the output terminals of the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal. The positive output terminal of the first drive signal is connected to the gate of IGBT1, and the negative output terminal of the first drive signal is connected to the emitter of IGBT1. The positive output terminal of the second drive signal is connected to the gate of the IGBT2 transistor, and the negative output terminal of the second drive signal is connected to the emitter of the IGBT2 transistor. The positive output terminal of the third drive signal is connected to the gate of the IGBT3 transistor, and the negative output terminal of the third drive signal is connected to the emitter of the IGBT3 transistor. The positive output terminal of the fourth drive signal is connected to the gate of the IGBT4 transistor, and the negative output terminal of the fourth drive signal is connected to the emitter of the IGBT4 transistor.

[0015] Furthermore, the communication circuit uses the MAX3232 chip. The TTL side of the MAX3232 chip is connected to the UART interface of the TMS320F28377D chip, and the RS232 side of the MAX3232 chip is connected to the configuration panel.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: This invention proposes an IGBT dual-pulse test system based on the TMS320F28377D. Through an integrated test interface and automated control module, it achieves one-click parameter configuration and test startup, significantly reducing the complexity of manual intervention and improving test efficiency. It is suitable for IGBT / silicon carbide single-transistor, half-bridge / full-bridge modules, and complex topologies such as linear three-level and T-type three-level circuits. Through programmable load matching and signal conditioning circuits, it flexibly adapts to different package specifications and electrical parameters. It can comprehensively test the conduction loss, turn-off loss, and reverse recovery characteristics of devices under hard switching and soft switching conditions, quantitatively analyze the impact of parasitic parameters on Vce overshoot, and provide accurate data support for optimized design. It can quickly locate parasitic inductance hotspots and drive signal timing deviations in PCB layout. By adjusting parameters such as drive resistors and gate drive voltages, it optimizes the switching speed and EMI performance of devices, improving overall system efficiency and reliability. Attached Figure Description

[0017] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely schematic to aid in understanding the present invention and do not specifically limit the shapes and proportions of the components. In the drawings: Figure 1 This is a schematic diagram of the overall design of an IGBT dual-pulse test system based on TMS320F28377D according to this utility model.

[0018] Figure 2 This invention relates to a single-line three-level dual-pulse loop circuit for an IGBT dual-pulse test system based on TMS320F28377D.

[0019] Figure 3 This invention relates to the pin definitions of the IGBT pins for a dual-pulse IGBT test system based on the TMS320F28377D control chip.

[0020] Figure 4 This invention relates to a +15V circuit for an IGBT dual-pulse test system based on the TMS320F28377D.

[0021] Figure 5This invention relates to a push-pull circuit for an IGBT dual-pulse test system based on the TMS320F28377D.

[0022] Figure 6 This invention relates to a DC voltage ADC sampling circuit for an IGBT dual-pulse test system based on the TMS320F28377D. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0024] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] Example 1 An IGBT dual-pulse test system based on TMS320F28377D includes an IGBT dual-pulse loop and a control circuit, which are connected together. The control circuit includes a power conversion circuit, a DC bus voltage sampling circuit, a PWM generation circuit, a PWM drive circuit, and a communication circuit. The PWM generation circuit includes a TMS320F28377D chip. The power conversion circuit is connected to both the TMS320F28377D chip and the PWM drive circuit. The DC bus voltage sampling circuit consists of a voltage divider resistor and an operational amplifier. The voltage divider resistor is connected in parallel between the positive and negative terminals of the DC power supply. The output of the operational amplifier is connected to the ADC interface of the PWM generation circuit. The signal output of the TMS320F28377D chip is connected to the signal input of the PWM drive circuit. One drive signal output of the PWM drive circuit is connected to one IGBT in the IGBT dual-pulse loop. The positive output of the drive signal is connected to the gate of the IGBT, and the negative output of the drive signal is connected to the emitter of the IGBT. The communication circuit is connected to both the TMS320F28377D chip and the configuration panel.

[0028] This embodiment features a precise DC bus voltage sampling circuit and powerful PWM generation capabilities, enabling accurate voltage acquisition and pulse generation for precise IGBT performance evaluation. In terms of control flexibility, the chip supports multiple PWM modes and can be programmably automated to meet the testing needs of IGBTs of different specifications. The system boasts excellent stability, with a reliable drive circuit providing stable drive for the IGBTs, and the power conversion circuit offering isolation and protection functions. It is highly scalable, with abundant peripheral interfaces facilitating connection to other devices, and a modular design for easy maintenance and upgrades. Human-machine interaction is convenient; connecting to a configuration screen via a communication circuit allows for intuitive display of test parameters and enables remote monitoring and operation, allowing users to monitor the test status without being physically present, improving the safety and flexibility of the testing process and providing an efficient and reliable solution for IGBT testing.

[0029] The input voltage of the power conversion circuit is +24V, and the output voltage of the power conversion circuit is +15V, +5V, or +3.3V. The power supply pin of the TMS320F28377D chip is connected to the +3.3V output voltage of the power conversion circuit, and the signal output terminal of the TMS320F28377D chip outputs four 3.3V PWM signals.

[0030] The IGBT dual-pulse circuit adopts a linear three-level IGBT dual-pulse circuit. The linear three-level IGBT dual-pulse circuit includes a DC power supply, a voltage divider capacitor bank, a linear three-level IGBT switch bridge arm, and a clamping diode bank. The voltage divider capacitor bank is connected in parallel between the positive and negative terminals of the DC power supply, and the linear three-level IGBT switch bridge arm is connected in parallel between the positive and negative terminals of the DC power supply. The neutral point of the voltage divider capacitor bank is connected to the middle node of the linear three-level switch bridge arm through the clamping diode bank. The linear three-level IGBT switch bridge arm is composed of IGBT1, IGBT2, IGBT3, and IGBT4 connected in series. IGBT1, IGBT2, IGBT3, and IGBT4 are arranged linearly from the positive terminal to the negative terminal of the DC power supply. The voltage divider capacitor bank is composed of the first capacitor C1 and the second capacitor C2 connected in series, and the clamping diode bank is composed of the first clamping diode D1 and the second clamping diode D2 connected in series.

[0031] The first terminal of the first capacitor C1 is connected to the positive terminal of the DC power supply, and the second terminal of the second capacitor C2 is connected to the negative terminal of the DC power supply. The second terminal of capacitor C1 is connected to the first terminal of capacitor C2, serving as the neutral point of the voltage divider capacitor group. The emitter of IGBT1 is connected to the collector of IGBT2, serving as the first intermediate node of the I-shaped three-level IGBT switch bridge arm. The emitter of IGBT2 is connected to the collector of IGBT3, serving as the loop output terminal of the I-shaped three-level IGBT switch bridge arm. The emitter of IGBT3 is connected to the collector of IGBT4, serving as the second intermediate node of the I-shaped three-level IGBT switch bridge arm.

[0032] The anode of the first clamping diode D1 is connected to the first intermediate node of the I-type three-level IGBT switch bridge arm, and the cathode of the first clamping diode D1 is connected to the neutral point of the voltage divider capacitor bank; the anode of the second clamping diode D2 is connected to the second intermediate node of the I-type three-level IGBT switch bridge arm, and the cathode of the second clamping diode D2 is connected to the neutral point of the voltage divider capacitor bank.

[0033] The single-line three-level IGBT dual-pulse circuit also includes a hollow inductor. One end of the hollow inductor is connected to the circuit output terminal of the single-line three-level IGBT switching bridge arm, and the other end of the hollow inductor is connected to the external load terminal.

[0034] The collector of IGBT1 is connected to the positive terminal of the DC power supply, and the emitter of IGBT4 is connected to the negative terminal of the DC power supply.

[0035] The PWM drive circuit includes an SN74LVC16T245 level converter, a CD4504 level converter, a push-pull circuit, an isolation transformer, and a 1EDI60N12AF driver chip connected in sequence. The 1EDI60N12AF chip includes output terminals for a first drive signal, a second drive signal, a third drive signal, and a fourth drive signal. The positive output terminal of the first drive signal is connected to the gate of IGBT1, and the negative output terminal is connected to the emitter of IGBT1. The positive output terminal of the second drive signal is connected to the gate of IGBT2, and the negative output terminal is connected to the emitter of IGBT2. The positive output terminal of the third drive signal is connected to the gate of IGBT3, and the negative output terminal is connected to the emitter of IGBT3. The positive output terminal of the fourth drive signal is connected to the gate of IGBT4, and the negative output terminal is connected to the emitter of IGBT4.

[0036] The communication circuit uses the MAX3232 chip. The TTL side of the MAX3232 chip is connected to the UART interface of the TMS320F28377D chip, and the RS232 side of the MAX3232 chip is connected to the configuration panel.

[0037] This embodiment's power conversion circuit can convert a +24V input into various output voltages to meet the needs of different modules and ensure stable power supply. The DC bus voltage sampling circuit accurately acquires the voltage through voltage divider resistors and operational amplifiers and transmits it to the ADC interface, providing a basis for precise control. The PWM generation circuit, based on the TMS320F28377D chip, outputs four 3.3V PWM signals for flexible control. The PWM drive circuit uses multi-stage level conversion and isolation to ensure the drive signal acts stably and reliably on the IGBTs. The communication circuit uses the MAX3232 chip to achieve reliable communication between the chip and the configuration panel, facilitating real-time monitoring and parameter setting. The three-level IGBT dual-pulse circuit adopts a single-line structure, with voltage divider capacitors and clamping diodes ensuring uniform voltage distribution and improving circuit stability. The hollow inductor is connected to the external load terminal to simulate actual operating conditions. Four IGBTs are connected in series, and with the clamping diodes, various switching state combinations can be achieved, comprehensively testing IGBT performance. The test circuit is reasonably designed and its components work together to accurately and stably complete the dual-pulse test of three-level IGBTs, providing strong support for the research and development and optimization of power electronic equipment.

[0038] Example 2 An IGBT dual-pulse test system based on TMS320F28377D, see [link / reference]. Figure 1This system mainly includes a dual-pulse loop circuit, a control circuit, a PWM wave circuit, a dual-pulse trigger program, and a configuration panel program. The control circuit includes a TMS320F28377D control chip, which communicates with the DSP chip via RS232 protocol using the configuration panel to control the dual-pulse trigger. The PWM wave generation circuit includes a level conversion circuit, a push-pull amplifier circuit, a drive power supply circuit, and a custom isolation transformer. The dual-pulse trigger program includes operating status judgment, ADC sampling, chip port configuration, phase and pin selection, and the trigger section. The configuration panel program includes the interface section. This system offers advantages such as simple operation, high efficiency, selectability for different phases and pins, and safety and reliability in testing IGBT / silicon carbide stress and Vce overshoot during dual-pulse testing of IGBTs / silicon carbide. It is highly adaptable to IGBT / silicon carbide single transistors, IGBT / silicon carbide modules, and IGBTs / silicon carbide with different topologies such as single-level and T-type.

[0039] The dual-pulse circuit includes: IGBT, air-core inductor, DC bus, and DC source. The DC source is responsible for providing a stable DC current to the DC bus, and the air-core inductor forms the current loop. Currently, a 20mH air-core inductor is selected, but the inductance value can be changed according to the actual situation. Figure 2 The diagram shows a three-level dual-pulse test circuit. Its DC signal is divided into positive, negative, and N. The dual-pulse circuit mainly consists of IGBT, air-core inductor, DC bus, and DC source. The DC source is responsible for providing a stable DC signal to the DC bus. The DSP is controlled by the configuration panel to generate PWM wave signals. When performing a double-pulse test on IGBT 2, the positive and negative terminals of the DC source are applied to the N and negative terminals of the DC bus. At this time, IGBTs 1 and 4 are normally open, and IGBT 3 is normally closed to ensure freewheeling. When the configuration panel is set to trigger the double pulse, the signal is sent by the DSP, amplified, and then sent to the GE terminals of IGBT 2. When the double pulse signal is high, the CE terminal of IGBT 2 is closed. The voltage difference between CE can be measured as 0V using an oscilloscope. At this time, the current flows from N through diode 1 to IGBT 2, and returns to the negative terminal through the air-core inductor. The current rise can be observed using an oscilloscope. When the double pulse signal is low, the CE terminal of IGBT 2 is open, and a voltage difference is measured between CE. The current stops rising. The process is repeated during the second trigger. The current rises again during the CE closure period. During this process, the voltage overshoot of IGBT 2 at the moment of closing and opening can be measured twice.

[0040] The control circuit and PWM wave circuit include: a DSP core control module, a multi-stage power conversion circuit, a PWM signal conditioning module, an isolated drive unit, and a human-machine interface. The TMS320F28377D is used as the main control chip. A JW5117C DC-DC converter chip converts the voltage from +24V to +15V, followed by a secondary conversion to obtain a +5V intermediate voltage. Finally, an LR1117CS33X linear regulator outputs a precise +3.3V to power the DSP core. The control system generates a basic PWM signal via a programmable GPIO port. An SN74LVC16T245_DL level shifter adapts the voltage from +3.3V to +5V, and a CD4504BM96 boosts the drive voltage from +5V to +15V. The power amplification stage uses a push-pull circuit structure with a custom isolation transformer. A 1EDI60N12AF driver chip outputs a PWM signal with strong drive capability to the IGBT unit. The human-computer interaction section uses the MAX3232EEAE chip to build an RS232 communication link and an operational amplifier to construct an ADC sampling circuit to acquire the DC voltage of the DC bus. The TMS320F28377D is used as the control chip, and an external +24V power supply is connected. Figure 4 As shown, the DC-DC chip JW5117C outputs +15V, which is then output as +5V via the JW5117C. The +5V then outputs as +3.3V via the step-down chip LR1117CS33X to power the DSP chip. The DSP's GPIO ports are defined and their high / low levels are controlled through the program to select the phase / IGBT pins and trigger the dual pulses. A level shifter SN74LVC16T245_DL converts the +3.3V PWM signal output by the DSP to a +5V PWM signal, and then a level shifter CD4504BM96 converts the +5V PWM signal back to a +15V PWM signal. Figure 5 The push-pull circuit amplifies the +15V PWM signal and supplies power to the driver chip 1EDI60N12AF through a custom isolation transformer. The amplified +15V PWM signal is then output as the final PWM signal to the IGBT via the 1EDI60N12AF. An operational amplifier is used to build an ADC sampling circuit to acquire the DC voltage of the DC bus. The DSP communicates with the configuration panel via the RS232 chip MAX3232EEAE. The configuration panel allows observation of the DC bus voltage and setting of the dual-pulse trigger waveform: first turn-on time, second turn-on time, and the interval between the two turn-on cycles. For three-phase four-wire / three-phase three-wire equipment, it can simulate the actual situation and select to trigger any one of the three phases. It can also select to trigger any one of transistors 1 / 2 / 3 / 4.

[0041] The dual-pulse triggering program includes: operation status management and judgment, phase selection logic unit, device gating control module, and human-machine interface. The control system incorporates a RUN_FLAG operation status indicator. When the configuration panel triggers the start command, this flag switches from 0 to 1, serving as the system operation enable condition. Under the condition of successful safety verification (RUN_FLAG=1), the system establishes a physical layer connection between the DSP and IGBTs through GPIO port mapping technology. Phase selection uses a conditional judgment structure to achieve intelligent identification of the A / B / C three-phase channels, while device gating uses a multi-branch selection structure to accurately address IGBTs 1-4, realizing a dual-pulse test mode for any phase-device combination. To prevent accidental triggering, the startup process must first be configured. RUN_FLAG is defined as the running status indicator. After clicking Start on the configuration screen, the RUN_FLAG status changes from 0 to 1. When RUN_FLAG is 1, the DSP can perform subsequent operations. By mapping the DSP's GPIO port to the IGBT pin, the state of the GPIO port is controlled to achieve a double-pulse test for a specific phase and a specific pin. Phase A, phase B, and phase C are selected using an if statement, and IGBT 1, 2, 3, and 4 are selected using a switch statement.

[0042] By adopting the above-mentioned solution, this invention can quickly complete the switching stress testing and dynamic parameter characterization of IGBT / silicon carbide devices, accurately guide the optimization of PCB parasitic parameters and drive loop impedance matching, and effectively improve the switching characteristics and energy efficiency of the devices. Through multi-dimensional parameter synergistic optimization, the operating point of the power devices is brought close to the theoretical limit value, significantly enhancing the overall efficiency of the equipment.

[0043] The principle of an IGBT dual-pulse test system based on TMS320F28377D is as follows: Dual-pulse circuit, such as Figure 2 As shown: This circuit can be adjusted according to the actual situation of R&D, ensuring that the dual-pulse circuit can function and the current direction is normal. The diagram shows the IGBT topology of a three-level linear structure, mainly composed of a DC power supply unit and a main power circuit. The system adopts a three-wire structure with positive, negative, and neutral points. The DC source provides DC voltage to the DC bus through a precision voltage regulator. The main power circuit consists of four IGBTs, including the body diode of the IGBT itself, and is equipped with an air-core inductor as an energy storage element. Its coreless characteristic can effectively avoid the influence of magnetic saturation on the test results.

[0044] The TMS320F28377D control chip defines the IGBT pins as follows: Figure 3As shown: Chip PIN 160 is GPIO 0, corresponding to the GE of 2 phase A IGBT / Silicon Carbide transistors; Chip PIN 161 is GPIO 1, corresponding to the GE of 4 phase A IGBT / Silicon Carbide transistors; Chip PIN 162 is GPIO 2, corresponding to the GE of 1 phase A IGBT / Silicon Carbide transistor; Chip PIN 163 is GPIO 3, corresponding to the GE of 3 phase A IGBT / Silicon Carbide transistors; Chip PIN 164 is GPIO 4, corresponding to the GE of 2 phase B IGBT / Silicon Carbide transistors; Chip PIN 165 is GPIO 5, corresponding to the GE of 4 phase B IGBT / Silicon Carbide transistors; Chip PIN 166 is GPIO 6, corresponding to the GE of 1 phase B IGBT / Silicon Carbide transistor; Chip PIN 167 is GPIO 7, corresponding to the GE of 3 phase B IGBT / Silicon Carbide transistors; Chip PIN 168 is GPIO 8, corresponding to the GE of 2 phase C IGBT / Silicon Carbide transistors; Chip PIN 169 is a GPIO pin. 9 corresponds to the GE of 4 C-phase IGBT / silicon carbide transistors; chip pin 170 is GPIO 10, corresponding to the GE of 1 C-phase IGBT / silicon carbide transistor; chip pin 171 is GPIO 11, corresponding to the GE of 3 C-phase IGBT / silicon carbide transistors. +24V to +15V circuit, such as Figure 4As shown: The diode rectifier network has D46 cathode connected to VDD2 and anode connected to D55 cathode. D55 anode is connected to VEE3, and their midpoint is connected to the secondary output of the isolation transformer. The D46-D55 series structure performs half-wave rectification of the high-frequency AC signal, and combined with the capacitor network, it generates an isolated power supply. The capacitor regulator network has C78 and C5 connected in parallel, with their upper ends connected to VDD3; C79 and C6 connected in parallel, with their lower ends connected to VEE3. The midpoints of these four capacitors are connected to the other secondary output of the isolation transformer, forming a full-bridge rectifier structure. The capacitor bank is used to achieve high-frequency ripple filtering and voltage stabilization. The power supply filtering network has high-voltage side filtering: C10, C62, C109, C108, and C99 connected in parallel, with their upper ends connected to VDD3 and the VDD3-VDD network, and their lower ends connected to AEE3 and IGBT_AE3. AE3 and IGBT_AE3 are shorted by a 0Ω resistor R134, forming the same network (reserved for future design). Low-voltage side filtering: C14, C67, C82, C83, and C98 are connected in parallel, with the lower end connected to VEE3 and the upper end connected to AE3 and IGBT_AE3. C20, C56, and C57 are connected in parallel, with the upper end connected to VDD3 and the lower end connected to VEE3, further suppressing power supply noise. Second-order low-pass filter: The PWM_AG3 signal is input to the left side of R87, and after being divided by R87 and R90, the right side is connected to D13 and R100. R100 and C43 are connected in series to ground, and the midpoint of R87-R90 is grounded through C39, forming an RC filter network to filter out high-frequency interference. Signal isolation and driving: The filtered signal is inverted by the ACT14 logic chip and output to the cathode of the isolation optocoupler ACPL332J to achieve signal isolation and level conversion.

[0045] Push-pull circuits, such as Figure 5As shown: In an NPN-PNP complementary pair structure, Q15 (SS8050 NPN) receives the PWM_B_G2 signal from the FPGA output through resistor R48 at its base, with its emitter directly grounded (GND). Its collector is connected to the load output, acting as a low-side switch. Q18 (SS8550 PNP) has its emitter directly connected to the +15V_IN power supply. Its base may be reverse-coupled to the PWM_B_G2 signal (controlled by logic levels or a voltage divider network), and its collector is connected to the load output, acting as a high-side switch. When PWM_B_G2 is high, Q15 conducts, and the load current path is: +15V_IN to the load, then to Q15, and finally to GND. When PWM_B_G2 is low, Q18 conducts, and the load current path is: +15V_IN to Q18, then to the load, and finally to GND. By alternately switching on complementary transistors, bidirectional drive of the load is achieved, increasing output current capability and reducing power consumption. The PWM_B_G2 signal directly drives the base of Q15 through the current-limiting resistor R48, ensuring fast switching of the NPN transistor. The base of Q18 can receive control signals through internal logic level conversion or external circuitry (such as an inverter), ensuring complementary operation with Q15. Utilizing the characteristics of NPN and PNP transistors, alternating high-side and low-side conduction is achieved, avoiding the risk of shoot-through between the upper and lower transistors. The SS8050 (NPN) and SS8550 (PNP) are medium-power transistors that can support relatively large load currents (typically 1.5A). DC ADC sampling circuit as follows Figure 6As shown, in the power supply filtering and power supply section, positive and negative power supply filters, +15V_A and -15V_A are grounded (GND) through parallel C187 (100nF) and C188 (100nF) respectively, forming a high-frequency decoupling network to suppress power supply noise. AD VDC1 and LGD VDC1_IN may be power input or monitoring nodes, directly coupled to the power supply through capacitors. The operational amplifier core circuit (TLV4170D) has its positive power supply terminal connected to +15V_A and its negative power supply terminal connected to -15V_A, ensuring that the operational amplifier operates in dual-supply mode. In the input network, R29 (10kΩ) and C45 (1100pF) are connected in series to form a low-pass filter or phase compensation network. VDI (input signal) is current-limited by R33 (910Ω) and filtered out for high-frequency interference by C47 (100pF). The feedback and output network consists of resistors R39 (10kΩ) and C50 (680pF) connected in parallel to form a feedback path for stabilizing gain or suppressing oscillations. R43 (200kΩ) and R45 (200kΩ) are connected to diodes LBAV99WT1G and LGAV99WT1G respectively, forming an output protection or limiting circuit to prevent voltage overshoot. A bidirectional diode network, with LBAV99WT1G and LGAV99WT1G (dual diode structure) grounded via C53 (680pF) and C50 (680pF) respectively, may be used for input / output signal clamping protection to suppress transient voltages. The combination of diodes and resistors (R43, R45) can achieve signal level limiting or noise absorption.

[0046] The code for the double pulse trigger program is as follows: To prevent accidental triggering, you need to click "Start" first. Subsequent actions will only occur when "RUN_FLAG" is 1. DSP1to2

[14] represents the trigger signal. When DSP1to2

[14] is 1, a double pulse signal is emitted. DSP1to2[2] represents phase selection. When DSP1to2[2] is 1, phase A is selected; when DSP1to2[2] is 2, phase B is selected; when DSP1to2[2] is 3, phase C is selected. DSP1to2[5] represents the IGBT pin selection. When DSP1to2[5] is 1, 1 IGBT is selected; when DSP1to2[5] is 2, 2 IGBTs are selected; when DSP1to2[5] is 3, 3 IGBTs are selected; and when DSP1to2[5] is 4, 4 IGBTs are selected.

[0047] if (RUN_FLAG == 1) { / / First, shut down all IGBTs GpioDataRegs.GPACLEAR.bit.GPIO0=1; GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; if (DSP1to2

[14] == 1) { / / First block all IGBTs GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; switch(DSP1to2[2]) { case 1: { / / A phase locks B and C phases GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; switch(DSP1to2[5]) { case 1: { / / A phase, 1st transistor GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; GpioDataRegs.GPASET.bit.GPIO0 = 1; DELAY_US(10); GpioDataRegs.GPASET.bit.GPIO2 = 1; DELAY_US(DSP1to2[8]); GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; DELAY_US(DSP1to2

[17] ); GpioDataRegs.GPASET.bit.GPIO2 = 1; DELAY_US(DSP1to2

[11] ); GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; DSP1to2

[14] = 0; break; } case 2: { / / A - phase 2 - tube GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPASET.bit.GPIO3 = 1; DELAY_US(10); GpioDataRegs.GPASET.bit.GPIO0 = 1; DELAY_US(DSP1to2[8]); GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; DELAY_US(DSP1to2

[17] ); GpioDataRegs.GPASET.bit.GPIO0 = 1; DELAY_US(DSP1to2

[11] ); GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; DSP1to2

[14] = 0; break; } case 3: { / / A - phase 3 - tube GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPASET.bit.GPIO0 = 1; DELAY_US(10); GpioDataRegs.GPASET.bit.GPIO3 = 1; DELAY_US(DSP1to2[8]); GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; DELAY_US(DSP1to2

[17] ); GpioDataRegs.GPASET.bit.GPIO3 = 1; DELAY_US(DSP1to2

[11] ); GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; DSP1to2

[14] = 0; break; } case 4: { / / A phase 4 transistors GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; GpioDataRegs.GPASET.bit.GPIO3 = 1; DELAY_US(10); GpioDataRegs.GPASET.bit.GPIO1 = 1; DELAY_US(DSP1to2[8]); GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; DELAY_US(DSP1to2

[17] ); GpioDataRegs.GPASET.bit.GPIO1 = 1; DELAY_US(DSP1to2

[11] ); GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; DSP1to2

[14] = 0; break; } default: { break; } } break } The logic of phases B and C is similar to that of phase A, and will not be described further here.

[0048] This invention is specifically designed for dynamic parameter testing and reliability verification of IGBT and silicon carbide (SiC) power devices, and possesses the following core advantages: Ease of operation: The system, through an integrated test interface and automated control module, enables one-click parameter configuration and test initiation, supporting independent or combined testing of different phases and multiple pins, significantly reducing the complexity of manual intervention, improving testing efficiency, and comprehensively evaluating device stress distribution. Device compatibility: Applicable to IGBT / SiC single-transistor, half-bridge / full-bridge modules, and complex topologies (such as linear three-level, T-type three-level, etc.), it flexibly adapts to different package specifications and electrical parameters through programmable load matching and signal conditioning circuits. Comprehensive dynamic parameter coverage: It can test the conduction loss, turn-off loss, and reverse recovery characteristics of devices under hard switching, soft switching, and other operating conditions, and quantitatively analyze the impact of parasitic parameters (such as stray inductance) on Vce overshoot, quickly locating parasitic inductance hotspots and drive signal timing deviations in PCB layout, providing data support for optimized design. Precise tuning guidance optimizes the switching speed and EMI performance of devices by adjusting the drive resistor (Rg), gate drive voltage (Vge), and snubber circuit parameters (such as RC Snubber), fully leveraging the high-frequency, low-loss advantages of SiC devices to improve overall efficiency and reliability. This system serves high-performance power supply applications such as new energy vehicle electric drive systems, photovoltaic inverters, and industrial frequency converters, meeting the design requirements of high power density and high switching frequency. From device selection and verification in the R&D phase to batch consistency testing in the mass production phase, the system provides full-process testing support, helping companies shorten development cycles and reduce operational risks. This dual-pulse test system, through its efficient and flexible testing capabilities, broad compatibility, and data-driven optimization closed loop, provides a standardized solution for performance mining and reliability improvement of IGBT / SiC devices, making it an indispensable key tool in the field of power electronics design.

[0049] Many embodiments and applications beyond the examples provided will be apparent to those skilled in the art upon reading the foregoing description. Therefore, the scope of this teaching should not be determined by reference to the foregoing description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed utility model subject matter.

[0050] The above content provides a further detailed description of this utility model. It should not be considered that the specific embodiments of this utility model are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of this utility model, and all of these should be considered to fall within the defined protection scope of this utility model.

Claims

1. A dual-pulse test system for IGBTs based on TMS320F28377D, characterized in that, It includes an IGBT dual-pulse circuit and a control circuit, wherein the IGBT dual-pulse circuit and the control circuit are connected. The control circuit includes a power conversion circuit, a DC bus voltage sampling circuit, a PWM generation circuit, a PWM drive circuit, and a communication circuit. The PWM generation circuit includes a TMS320F28377D chip. The power conversion circuit is connected to both the TMS320F28377D chip and the PWM drive circuit. The DC bus voltage sampling circuit consists of a voltage divider resistor and an operational amplifier. The voltage divider resistor is connected in parallel between the positive and negative terminals of the DC power supply. The output terminal of the operational amplifier is connected to the ADC interface of the PWM generation circuit. The signal output terminal of the TMS320F28377D chip is connected to the signal input terminal of the PWM drive circuit. One drive signal output terminal of the PWM drive circuit is connected to an IGBT in the IGBT double pulse loop. The positive output terminal of the drive signal is connected to the gate of the IGBT, and the negative output terminal of the drive signal is connected to the emitter of the IGBT. The communication circuit is connected to both the TMS320F28377D chip and the configuration panel.

2. The IGBT dual-pulse test system based on TMS320F28377D according to claim 1, characterized in that, The input voltage of the power conversion circuit is +24V, and the output voltage of the power conversion circuit is +15V, +5V, or +3.3V.

3. The IGBT dual-pulse test system based on TMS320F28377D according to claim 2, characterized in that, The power supply pin of the TMS320F28377D chip is connected to the +3.3V output voltage of the power conversion circuit, and the signal output terminal of the TMS320F28377D chip outputs four 3.3V PWM signals.

4. The IGBT dual-pulse test system based on TMS320F28377D according to claim 1, characterized in that, The IGBT dual-pulse circuit adopts a one-line three-level IGBT dual-pulse circuit. The single-line three-level IGBT dual-pulse circuit includes a DC power supply, a voltage divider capacitor bank, a single-line three-level IGBT switch bridge arm, and a clamping diode bank. The voltage divider capacitor bank is connected in parallel between the positive and negative terminals of the DC power supply, the three-level IGBT switch bridge arm is connected in parallel between the positive and negative terminals of the DC power supply, and the neutral point of the voltage divider capacitor bank is connected to the middle node of the three-level switch bridge arm through a clamping diode bank. The single-line three-level IGBT switch bridge arm is composed of IGBT1, IGBT2, IGBT3 and IGBT4 connected in series, and the IGBT1, IGBT2, IGBT3 and IGBT4 are arranged linearly along the direction from the positive terminal to the negative terminal of the DC power supply. The voltage divider capacitor group is composed of a first capacitor C1 and a second capacitor C2 connected in series, and the clamping diode group is composed of a first clamping diode D1 and a second clamping diode D2 connected in series.

5. The IGBT dual-pulse test system based on TMS320F28377D according to claim 4, characterized in that, The first terminal of the first capacitor C1 is connected to the positive terminal of the DC power supply, and the second terminal of the second capacitor C2 is connected to the negative terminal of the DC power supply. The second end of capacitor C1 is connected to the first end of capacitor C2, serving as the neutral point of the voltage divider capacitor bank. The emitter of IGBT1 is connected to the collector of IGBT2, serving as the first intermediate node of the IGBT 1 three-level IGBT switch bridge arm. The emitter of IGBT2 is connected to the collector of IGBT3, serving as the loop output terminal of the one-line three-level IGBT switch bridge arm. The emitter of IGBT3 is connected to the collector of IGBT4, serving as the second intermediate node of the IGBT 3-level switch bridge arm.

6. The IGBT dual-pulse test system based on TMS320F28377D according to claim 5, characterized in that, The anode of the first clamping diode D1 is connected to the first intermediate node of the IGBT switch bridge arm, and the cathode of the first clamping diode D1 is connected to the neutral point of the voltage divider capacitor bank. The anode of the second clamping diode D2 is connected to the second intermediate node of the three-level IGBT switch bridge arm, and the cathode of the second clamping diode D2 is connected to the neutral point of the voltage divider capacitor bank.

7. The IGBT dual-pulse test system based on TMS320F28377D according to claim 4, characterized in that, The single-line three-level IGBT dual-pulse circuit also includes a hollow inductor. One end of the hollow inductor is connected to the circuit output terminal of the single-line three-level IGBT switch bridge arm, and the other end of the hollow inductor is connected to the external load terminal.

8. The IGBT dual-pulse test system based on TMS320F28377D according to claim 4, characterized in that, The collector of IGBT1 is connected to the positive terminal of the DC power supply, and the emitter of IGBT4 is connected to the negative terminal of the DC power supply.

9. The IGBT dual-pulse test system based on TMS320F28377D according to claim 4, characterized in that, The PWM drive circuit includes an SN74LVC16T245 level converter, a CD4504 level converter, a push-pull circuit, an isolation transformer, and an 1EDI60N12AF driver chip connected in sequence. The 1EDI60N12AF driver chip includes an output terminal for a first drive signal, an output terminal for a second drive signal, an output terminal for a third drive signal, and an output terminal for a fourth drive signal. The positive output terminal of the first drive signal is connected to the gate of IGBT1, and the negative output terminal of the first drive signal is connected to the emitter of IGBT1. The positive output terminal of the second drive signal is connected to the gate of the IGBT2 transistor, and the negative output terminal of the second drive signal is connected to the emitter of the IGBT2 transistor. The positive output terminal of the third drive signal is connected to the gate of the IGBT3 transistor, and the negative output terminal of the third drive signal is connected to the emitter of the IGBT3 transistor. The positive output terminal of the fourth drive signal is connected to the gate of the IGBT4 transistor, and the negative output terminal of the fourth drive signal is connected to the emitter of the IGBT4 transistor.

10. The IGBT dual-pulse test system based on TMS320F28377D according to claim 1, characterized in that, The communication circuit uses the MAX3232 chip. The TTL side of the MAX3232 chip is connected to the UART interface of the TMS320F28377D chip, and the RS232 side of the MAX3232 chip is connected to the configuration panel.

Images