Chip aging test system based on field programmable gate array

Abstract

The application provides a chip aging test system based on a field programmable gate array. In the system, a drive control board comprises a processor module, a communication interface module and an external connector module. The external connector module comprises a first connector and a second connector. The processor module is configured to receive a test instruction sent by a host computer through the communication interface module, generate a test signal and a control signal, and receive a test result acquisition instruction sent by the host computer after sending response information to the host computer through the communication interface module. A first end of the processor module is further configured to send interrupt information to the host computer through the communication interface module and display the interrupt information. A third end of the processor module is connected with the second connector and configured to output the control signal to a test board. The test signal is output to multiple groups of measured chips on the test board in parallel through the first connector, and the second connector controls a test sequence (flow) of the measured chips on the test board, so that a single drive board is used to drive hundreds of chips and is used for aging test.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuit and chip testing, and in particular to a chip aging test system based on field-programmable gate arrays. Background Technology

[0002] In the chip manufacturing and testing process, aging testing is a critical step to ensure chip reliability and performance. It generally includes manufacturer testing and customer-based testing. Manufacturer testing utilizes pre-programmed code to obtain test status data through chip pins. Customer-based testing involves providing the chip with an stimulus signal and obtaining corresponding feedback data.

[0003] However, based on user-defined chip aging tests, when faced with a large number of chip testing needs (e.g., hundreds at a time), especially for NAND chips, the efficiency of aging tests is insufficient and cannot meet market demands.

[0004] Based on this, this application provides a chip aging test system based on field-programmable gate arrays. Utility Model Content

[0005] To overcome the shortcomings of the above technologies, this application provides a chip aging test system based on field-programmable gate arrays.

[0006] The objective of this application is achieved through the following technical solution: This application provides a chip aging test system based on a field-programmable gate array (FPGA), including a driver control board for receiving aging test commands sent by a host computer, and a test board communicatively connected to the driver control board for executing test control commands sent by the driver control board; the driver control board includes a processor module, a communication interface module, and an external connector module; the external connector module includes a first connector and a second connector. The first end of the processor module is connected to the communication interface module, and is used to receive test instructions sent by the host computer and generate test signals and control signals through the communication interface module, and to receive test result acquisition instructions sent by the host computer after the communication interface module sends response information to the host computer. The second end of the processor module is connected to the first connector and is used to provide the test signal to multiple groups of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test; the first end of the processor module is also used to send the interrupt information to the host computer through the communication interface module and display it. The third end of the processor module is connected to the second connector and is used to output the control signal to the test board. The control signal is used to control the test process of the chip under test on the test board.

[0007] Preferably, the processor module includes a PS unit and a PL unit, wherein the PS unit is an ARM architecture and the PL unit is an FPGA structure, and the two are communicatively connected. The PS unit is connected to the communication interface module and is used to receive test commands sent by the host computer and send commands to the PL unit through the communication interface module. The PL unit is connected to the first connector and is used to provide the generated test signal to multiple groups of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test; the PL unit is also connected to the second connector and is used to output the generated control signal to the test board, the control signal being used to control the test process of the chip under test on the test board.

[0008] Preferably, it further includes a comparator module, wherein the first and second ends of the comparator module are respectively connected to the PL unit, and the third end is respectively connected to the first connector and the second connector.

[0009] Preferably, it also includes a power management module, which includes a power supply unit and multiple power distribution units; the external connector module also includes a third connector, and the power supply unit is connected to the third connector through each power distribution unit.

[0010] Preferably, one end of the third connector is connected to the test board; the other end is connected to the PS unit and connected to the PL unit through a buffer.

[0011] Preferably, the system further includes a signal processing module disposed between the processor module and the external connector module. The signal processing module includes a buffer and a driver. The buffer is used for signal buffering and impedance matching, and the driver is used to enhance the multi-chip driving capability of the signal.

[0012] Preferably, the signal processing module includes a first set of buffers and drivers, and a second set of buffers and drivers. The first set of buffers and drivers is connected in series between the PL unit and the first connector, and the second set of buffers and drivers is connected in series between the PL unit and the second connector.

[0013] Based on the above technical solutions and the technical problems solved, this application provides a chip aging test system based on a field-programmable gate array (FPGA). The processor module parses the host computer instructions and generates test signals (such as clock and data waveform information) and control signals (such as chip select enable, reset, and scan address information). The first connector is used to output test signals to the chip under test (DUT) and receive test feedback data from the DUT. The second connector is used to output control signals (for test process scheduling and mode switching).

[0014] The advantages and positive effects of the technical solution to be protected are as follows: Test signals are output in parallel to multiple groups of chips under test on the test board via the first connector, and the second connector controls the test order (process) of the chips under test on the test board, enabling a single driver board to drive hundreds of chips for aging tests. Simultaneously, addressing the problem of shared channels and signal interference in related technologies, this embodiment dedicates the first connector to high-speed test signals and the second connector to control signals, achieving physical isolation between the two connectors. The technical solution adopts a motherboard-daughterboard architecture, with the driver control board as the motherboard, integrating a general-purpose processor module, communication interface module, and power management module; the test board, as the daughterboard, can be customized according to different chip types. When testing a new chip type, only the corresponding test board needs to be replaced. For example, if the existing test board is adapted for NAND chips, when testing UFS chips, it can be replaced with a test board adapted for UFS, without any modification to the driver control board. This not only reduces the cost of hardware upgrades but also greatly improves system compatibility and flexibility. Attached Figure Description

[0015] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0016] Figure 1 This is a structural block diagram of a chip aging test system provided in an embodiment of this application.

[0017] Figure 2 This is a hardware block diagram of a driver control board provided in an embodiment of this application.

[0018] Figure 3 This is a schematic flowchart of a chip aging test method provided in an embodiment of this application.

[0019] Figure 4 This is a partial flowchart of a chip aging test method provided in an embodiment of this application.

[0020] Figure 5 This is a partial flowchart of a chip aging test method provided in an embodiment of this application.

[0021] Figure 6This is a partial structural schematic diagram of a test board provided in an embodiment of this application. Detailed Implementation

[0022] The present application will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments. The implementation process of the present application will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation procedures, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for illustrating the present application and not for limiting the scope of protection of the present application.

[0023] The following is a brief description of the technical field and related terms of the embodiments of this application, so as to facilitate understanding by those skilled in the art.

[0024] In the chip manufacturing and testing process, aging testing is a critical step in ensuring chip reliability and performance. Traditional testing equipment has shortcomings in terms of temperature range, testing efficiency, and compatibility, and cannot meet the increasingly diverse market demands.

[0025] This high and low temperature aging test chamber supports multiple simultaneous tests, with a temperature range of -45℃ to 125℃ and a temperature uniformity of ≤±3℃. It is compatible with various memory chips such as NAND, UFS, and eMMC. It integrates automated testing and monitoring functions, supports SECS / GEM standards, and seamlessly integrates with MES systems.

[0026] The testing software system supports customizable test logic, data visualization and traceability, and provides real-time monitoring and hierarchical management functions.

[0027] The burn-in board (BIB) supports 128 / 224 / 256 DUTs, is compatible with a variety of memory chips, and significantly reduces the cost of burn-in testing for customers.

[0028] However, none of the above-described chip aging test systems can simultaneously perform aging tests on a large number of chips. Furthermore, traditional chip aging test solutions require specialized aging test designs for different types of memory chips, making them incompatible with various memory chip types and thus increasing user costs.

[0029] Based on this, this application provides a chip aging test system and method based on field-programmable gate arrays. The system will be described first, followed by the method.

[0030] System Implementation Example.

[0031] See Figure 1 and Figure 2 This application provides a chip aging test system based on a field-programmable gate array (FPGA), including a driver control board for receiving aging test commands sent by a host computer, and a test board that is communicatively connected to the driver control board and is used to execute test control commands sent by the driver control board; the driver control board includes a processor module 10, a communication interface module 20, and an external connector module 30; the external connector module 30 includes a first connector and a second connector. The first end of the processor module 10 is connected to the communication interface module 20, and is used to receive test instructions sent by the host computer through the communication interface module 20 and generate test signals and control signals, and receive test result acquisition instructions sent by the host computer after the communication interface module 20 sends response information to the host computer. The second end of the processor module 10 is connected to the first connector and is used to provide the test signal to multiple groups of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test; the first end of the processor module 10 is also used to send the interrupt information to the host computer through the communication interface module 20 and display it. The third terminal of the processor module 10 is connected to the second connector and is used to output the control signal to the test board. The control signal is used to control the test process of the chip under test on the test board.

[0032] Processor module 10 parses instructions from the host computer and generates test signals (such as clock and data waveform information) and control signals (such as chip select enable, reset, and scan address information). The first connector is used to output test signals to the chip under test and receive test feedback data from the chip under test. The second connector is used to output control signals (for test process scheduling and mode switching).

[0033] See Figure 6 The test board includes a test board connection module 70 corresponding to the external connector module 30 of the drive control board, and the test board connection module 70 includes multiple connectors. It also includes a test area 80 for placing the chip under test.

[0034] In related technologies, test signals are output in parallel to multiple groups of chips under test on a test board via a first connector, and the second connector controls the test order (process) of the chips under test on the test board, enabling a single driver board to drive hundreds of chips for aging tests. Furthermore, addressing the issue of test / control signals sharing a channel and causing signal mixing and interference in related technologies, this embodiment dedicates the first connector to high-speed test signals and the second connector to control signals, achieving physical isolation between the two connectors.

[0035] Meanwhile, traditional chip aging test schemes require specialized aging test designs for different types of memory chips, resulting in incompatibility with multiple memory chip types and increased user costs. The technical solution provided in this application adopts a motherboard-daughterboard architecture. The driver control board serves as the motherboard, integrating a general-purpose processor module 10, communication interface module 20, and power management module 50, etc.; the test board serves as the daughterboard, which can be customized according to different chip types. When a new chip type needs to be tested, only the corresponding test board needs to be replaced. For example, if the existing test board is adapted to NAND chips, when testing UFS chips, it is replaced with a test board adapted to UFS, without any modification to the driver control board. This not only reduces the cost of hardware upgrades but also greatly improves system compatibility and flexibility.

[0036] In some embodiments, the processor module 10 includes a PS unit and a PL unit, wherein the PS unit is an ARM architecture and the PL unit is an FPGA structure, and the two are communicatively connected. The PS unit is connected to the communication interface module 20 and is used to receive test commands sent by the host computer through the communication interface module 20 and send commands to the PL unit. The PL unit is connected to the first connector and is used to provide the generated test signals to multiple groups of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test. The PL unit is also connected to the second connector and is used to output the generated control signals to the test board, the control signals being used to control the test process of the chips under test on the test board.

[0037] The PS unit (ARM architecture) receives test commands from the host computer through the communication interface and sends them to the PL unit, and manages the host computer communication (sending responses / uploading results).

[0038] The PL unit (FPGA structure) receives instructions from the PS unit and generates test signals (such as data modes) and control signals (such as CE / RE timing). It then executes operations: outputting test signals to multiple chip groups via the first connector (driving operation); and outputting control signals via the second connector (managing the test process). Feedback data from the test board chips (such as fault status) is sent to the PL unit via the first connector.

[0039] The advantage of this embodiment is that the PL unit, considering the FPGA structure, can generate hundreds of independent test signals simultaneously, while traditional MCUs, limited by port restrictions, can only drive a small number of chips, thus improving testing efficiency. The PS unit focuses on non-real-time tasks such as communication management, while the PL unit focuses on high real-time tasks such as signal generation / acquisition, avoiding real-time tasks blocking the system (such as the inability to process feedback when outputting signals).

[0040] In practical applications, the PS unit is also connected to a storage device, which is used to store firmware or boot code.

[0041] In some embodiments, the processor module includes an XC7Z045-2FFG900I.

[0042] In some embodiments, a comparator module 40 is further included, wherein a first end and a second end of the comparator module 40 are respectively connected to the PL unit, and a third end is respectively connected to the first connector and the second connector.

[0043] A comparator module 4 is added to the drive control board to form a closed-loop self-test link. Specifically, the first end is used to receive the self-test code issued by the PL unit inside the FPGA; the second end is connected to the PL unit and is used to receive the self-test enable signal or real-time reference level; the third end (multiple pins) is connected to the end pins of the first connector and the second connector respectively, and the real level of the connector end is pulled back to the comparator through the loopback line.

[0044] In this embodiment, the comparator is designed to perform a self-test of the board's link. At the connector end, where the signal terminates, a closed loop of the circuit is formed, and the signal is then fed back to the comparator module 40 to detect whether the transmitted information is correctly represented at the connector. This is because the signal will ultimately be output / input to the board under test through the connector. This confirms that the signal emitted by PL functions correctly throughout the entire link on the board and can be correctly represented at the connector end.

[0045] Therefore, the self-test closed loop can verify the health of the board's links online, reducing downtime for maintenance. The self-test process is completed autonomously by the FPGA logic, and is quick.

[0046] In some embodiments, the power management module 50 is further included, which includes a power supply unit and a plurality of power distribution units; the external connector module 30 further includes a third connector, and the power supply unit is connected to the third connector through each power distribution unit.

[0047] The power supply unit is used to convert the input power into the base voltage required by the system. Each of the multiple power distribution units (DPS) is used to independently regulate one power output (such as voltage / current / ripple). The third connector physically connects the driver board and the test board, transmitting independent power supply signals to the test board.

[0048] In some embodiments, one end of the third connector is connected to the test board; the other end is connected to the PS unit and, through a buffer, to the PL unit.

[0049] In practical applications, the function of the circuit structure connected by the third connector is as follows: When one end of the third connector is connected to the test board, it means that the test board sends the AIN signal to the PS unit through the third connector; when connected to the PL unit through the buffer, the test board sends the BIDID signal and R / Bn signal to the PL unit through the third connector and the buffer.

[0050] The BIDID signal is used to read the ID of the test board; the R / Bn signal is used to read the status information of the chip under test on the test board; and the AIN signal is used to transmit the current and voltage values ​​of the chip under test on the test board.

[0051] In some embodiments, a signal processing module 60 is further included, disposed between the processor module 10 and the external connector module 30. The signal processing module 60 includes a buffer and a driver. The buffer is used for signal buffering and impedance matching, and the driver is used to enhance the multi-chip driving capability of the signal.

[0052] After generating test and control signals, the processor module 10 sends them to the buffers in the signal processing module 60. The buffers perform buffering to ensure signal integrity and stability, and perform impedance matching to ensure effective signal transmission to the subsequent drivers. The buffered signals are then sent to the drivers. The drivers enhance the signal's driving capability, enabling the signal to drive multiple chips under test simultaneously. The enhanced signals are transmitted to the test board via the external connector module 30, thereby driving the chips under test to operate according to a predetermined test mode.

[0053] In some embodiments, the signal processing module 60 includes a first set of buffers and drivers, and a second set of buffers and drivers. The first set of buffers and drivers is connected in series between the PL unit and the first connector, and the second set of buffers and drivers is connected in series between the PL unit and the second connector.

[0054] The signal processing module 60 includes two sets of buffers and drivers, which are connected in series between the PL unit and the first connector and the second connector, respectively. The first set of buffers and drivers is located between the PL unit and the first connector and is mainly responsible for processing test signals; the second set of buffers and drivers is located between the PL unit and the second connector and is mainly responsible for processing control signals.

[0055] The buffer performs signal buffering and impedance matching, effectively solving problems such as signal reflection, attenuation, and distortion during transmission, ensuring signal integrity and stability. For high-speed signal transmission applications, it can avoid test errors caused by signal quality issues, thereby improving the accuracy and reliability of test results.

[0056] The driver significantly enhances the signal's drive current and power, enabling the signal to drive multiple chips under test simultaneously. This makes the system suitable for parallel testing of large-scale chips, improving testing efficiency and reducing testing costs. By enhancing the signal's driving capability, the system ensures that each chip under test receives a sufficiently strong signal, guaranteeing the validity of the test.

[0057] Two sets of buffers and drivers are used to process test signals and control signals respectively, and the modular design reduces the complexity of the system. Compared with using a single signal processing module 60 to process all signals, it can more effectively optimize the processing of different types of signals, improving the system's performance and reliability.

[0058] In some embodiments, the first connector includes a plurality of I / O ports and a plurality of DQS ports; the second connector includes a plurality of RE ports, a plurality of CEn ports, and an address latch enable port, a command latch enable port, a write enable port, and a write protection port.

[0059] The first connector includes I / O ports and a DQS port. The I / O ports are responsible for transmitting test signals, while the DQS port is used for data gating, ensuring accurate data acquisition and transmission. The numerous I / O and DQS ports facilitate efficient data transmission, meeting the needs of high-speed chip testing. During chip aging testing, the rich port configuration ensures efficient and real-time data transmission, thereby improving overall system performance.

[0060] The second connector includes multiple RE ports, CEn ports, as well as address latch enable ports, command latch enable ports, write enable ports, and write protection ports. The RE ports are used for chip data reading; the CEn ports are responsible for chip selection, ensuring that test signals are precisely applied to a specific chip; the remaining ports correspond to chip address latching, command latching, data writing, and write protection, respectively. Its diverse control ports provide the system with strong control capabilities, enabling precise management of the chip testing process, improving testing accuracy and reliability, strongly supporting complex testing algorithms and functions, and ultimately enhancing the system's performance competitiveness.

[0061] In some embodiments, the system further includes a storage module and a debug interface module, which are connected to the PS unit.

[0062] The storage module may include Dynamic Random Access Memory (DRAM) and Read-Only Memory (NOR Flash), both connected to the PS unit. NOR Flash stores the system firmware and boot code. During system startup, the PS unit reads the boot code from the NOR Flash and begins execution, loading the operating system and other necessary programs. DRAM stores data during system operation, including data generated during testing, chip status information, and intermediate results. The PS unit continuously writes data to and reads data from the DRAM during operation. This data may be read and written multiple times during testing to support complex test algorithms and data processing tasks.

[0063] The debug interface module includes JTAG and UART interfaces, which connect to the PS unit. The JTAG interface is primarily used for hardware debugging and FPGA programming configuration. During development and debugging, developers can connect to debugging tools via the JTAG interface to debug the internal logic of the FPGA, setting breakpoints, single-stepping, viewing and modifying register values, etc., which helps to quickly locate and fix problems in the hardware design. In addition, the JTAG interface can also be used to program the FPGA and download new configuration files to update system functionality. The UART interface is used for serial communication with external debugging devices. During testing, the PS unit can send debugging information, test results, and system status data to external terminal devices via the UART interface. Developers can view this information in real time to monitor system operation and perform parameter adjustments.

[0064] Method implementation examples.

[0065] See Figure 3This application provides a chip aging test method based on a field-programmable gate array, which is applied to the chip aging test system described in any one of the system embodiments. The specific embodiments are consistent with the embodiments and the technical effects achieved in the above system embodiments, and some contents will not be repeated.

[0066] The method includes the following steps: S100: The processor module 10 receives test commands sent by the host computer through the communication interface module 20, generates test signals and control signals, and provides the test signals to the test board through the first connector and the control signals to the test board through the second connector. The control signals are used to select one or more groups of chips under test from the multiple groups of chips under test on the test board as the target chip group, and the test signals are used by the test board to perform aging tests on the test chips in the target chip group. S200, using the processor module 10, a response message is sent to the host computer through the communication interface module 20; S300, using the processor module 10, the test result acquisition instruction sent by the host computer is received through the communication interface module 20; S400, using the processor module 10, interrupt information is obtained through the first connector. The interrupt information includes test feedback data of each chip under test. The interrupt information is then sent to the host computer and displayed through the communication interface module 20.

[0067] In practical applications, the ARM (PS) first parses the instructions to determine which groups of chips will be aged in this round. The corresponding control words such as "chip select," "address latch," and "command latch" are sent out through the second connector, ensuring the test board only opens the target chip's channels. Simultaneously, test code streams such as "clock," "data," and "data strobe" are pushed to the target chip in parallel through the first connector. The entire process is driven by the FPGA's hardware logic (PL) to run multiple (e.g., 160) I / O channels and multiple (e.g., 32) DQS channels simultaneously, enabling hundreds of chips to undergo parallel aging.

[0068] See Figure 4 In some embodiments, the processor module 10 includes a PS unit and a PL unit, wherein the PS unit is an ARM architecture and the PL unit is an FPGA structure, and the two are communicatively connected; step S100 includes: S110, using the PS unit, the aging test command sent by the host computer is obtained through the communication interface module, parsed, and the command is sent to the PL unit; S120: The PL unit generates test signals and control signals according to the instructions issued by the PS unit. The test signals are provided to the test board through the first connector, and the control signals are provided to the test board through the second connector. The test board is used to perform aging tests on multiple groups of chips under test.

[0069] See Figure 5 In some embodiments, step S400 includes: S410, using the PL unit, the test feedback data of each chip under test sent by the test board is obtained through the external connector module 30. When the acquisition is completed, interrupt information including the test feedback data of each chip under test is generated. S420: When the test result acquisition instruction sent by the host computer is received, the interrupt information of the PL unit is obtained by the PS unit and sent to the host computer through the communication interface module 20, and then displayed by the host computer.

[0070] It should be noted that in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. It is worth noting that "at least one" can also be interpreted as "one or more".

[0071] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are configured to distinguish similar objects and are not necessarily configured to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] This application describes the invention from the perspectives of purpose, performance, progress, and novelty, and it meets the functional enhancement and use requirements emphasized by the Patent Law. The above description and drawings are merely preferred embodiments of this application and are not intended to limit this application. Therefore, all structures, devices, features, etc., that are similar to or identical to those of this application, i.e., all equivalent substitutions or modifications made in accordance with the scope of this patent application, shall fall within the scope of protection of this patent application.

Claims

1. A chip aging test system based on a field-programmable gate array (FPGA), comprising a driver control board for receiving aging test commands sent by a host computer, and a test board communicatively connected to the driver control board and for executing test control commands sent by the driver control board; characterized in that, The drive control board includes a processor module, a communication interface module, and an external connector module; the external connector module includes a first connector and a second connector. The first end of the processor module is connected to the communication interface module, and is used to receive test instructions sent by the host computer and generate test signals and control signals through the communication interface module, and to receive test result acquisition instructions sent by the host computer after the communication interface module sends response information to the host computer. The second end of the processor module is connected to the first connector and is used to provide the test signal to multiple groups of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test; the first end of the processor module is also used to send the interrupt information to the host computer through the communication interface module and display it. The third end of the processor module is connected to the second connector and is used to output the control signal to the test board. The control signal is used to control the test process of the chip under test on the test board.

2. The chip burn-in test system of claim 1, wherein, The processor module includes a PS unit and a PL unit. The PS unit is based on an ARM architecture, and the PL unit is based on an FPGA structure. The two units are connected in communication. The PS unit is connected to the communication interface module and is used to receive test commands sent by the host computer and send commands to the PL unit through the communication interface module. The PL unit is connected to the first connector and is used to provide the generated test signal to multiple sets of chips under test on the test board through the first connector, and then obtain interrupt information, the interrupt information including test feedback data of each chip under test; the PL unit is also connected to the second connector and is used to output the generated control signal to the test board, the control signal being used to control the test process of the chip under test on the test board.

3. The chip burn-in test system of claim 2, wherein, It also includes a comparator module, wherein the first and second ends of the comparator module are respectively connected to the PL unit, and the third end is respectively connected to the first connector and the second connector.

4. The chip burn-in test system of claim 2, wherein, It also includes a power management module, which includes a power supply unit and multiple power distribution units; the external connector module also includes a third connector, and the power supply unit is connected to the third connector through each power distribution unit.

5. The chip burn-in test system of claim 4, wherein, One end of the third connector is connected to the test board; the other end is connected to the PS unit and, through a buffer, to the PL unit.

6. The chip burn-in test system of claim 2, wherein, It also includes a storage module and a debug interface module, which are connected to the PS unit.

7. The system of claim 2, wherein, It also includes a signal processing module disposed between the processor module and the external connector module. The signal processing module includes a buffer and a driver. The buffer is used for signal buffering and impedance matching, and the driver is used to enhance the multi-chip driving capability of the signal.

8. The chip burn-in test system of claim 7, wherein, The signal processing module includes a first set of buffers and drivers, and a second set of buffers and drivers. The first set of buffers and drivers is connected in series between the PL unit and the first connector, and the second set of buffers and drivers is connected in series between the PL unit and the second connector.

9. The system of claim 1, wherein, The first connector includes multiple I / O ports and multiple DQS ports; the second connector includes multiple RE ports, multiple CEn ports, as well as address latch enable ports, command latch enable ports, write enable ports, and write protection ports.

10. The system of claim 2, wherein, The processor module includes XC7Z045-2FFG900I.

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