A switching device

Abstract

The utility model discloses a kind of switching devices, switching device includes switching board body, for connecting mainboard first interface, for connecting the second interface of memory module and for connecting the signal transmission component of two interfaces, signal transmission component includes electrically conductive connecting piece, at least two first connector and second connector oppositely arranged, electrically conductive connecting piece includes first cable, second cable and third cable, the pin of first connector is connected the pin of first interface by first cable respectively, the pin of second connector is connected the pin of second interface by second cable respectively, third cable connects first connector and second connector.The switching device can adapt to the verification scene of different types of memory modules, without developing mainboard for each memory module verification scene, solve the limitation that one verification scene needs to design a mainboard in traditional verification scheme, reduce hardware adaptation cost.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, and in particular to an adapter. Background Technology

[0002] As the core of a computer system's computation and control, the processor is the nerve center of various computing devices, and its performance directly determines the system's operating efficiency. With the iterative evolution of chip technology, the computing power and functionality of processors have continuously increased. The accompanying Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) protocol has also gradually upgraded from DDR1 to DDR5, with each generation achieving qualitative breakthroughs in bandwidth, power consumption, and signal integrity. However, in the compatibility verification stage between processors and DDR memory, due to differences in signal pin definitions, electrical characteristics, and protocol logic among different DDR models, both positive functional verification of signal pins (such as read / write stability under normal connection) and cross-scenario verification (such as compatibility after signal group swapping and pin sequence adjustment) require the development of dedicated verification motherboards for each DDR type. This results in lengthy development cycles and makes it difficult to adapt to the rapid iteration needs of processors and DDR protocols. Utility Model Content

[0003] The purpose of this utility model embodiment is to provide an adapter that can be adapted to verification scenarios of different types of memory modules. It eliminates the need to develop a separate motherboard for each type of memory module verification scenario, thus solving the limitation of traditional verification schemes that require the design of a motherboard for each verification scenario and reducing hardware adaptation costs.

[0004] To achieve the above objectives, this utility model provides an adapter device, comprising:

[0005] Adapter board body;

[0006] The first interface is located on one side of the adapter board body and is used to connect to the motherboard;

[0007] The second interface is located on the other side of the adapter board body and is used to connect the memory module;

[0008] The signal transmission component includes a conductive connector disposed on the adapter plate body, and at least two opposing first connectors and second connectors;

[0009] The conductive connector includes a first cable, a second cable, and a third cable. The pins of the first connector are connected to the pins of the first interface via the first cable. The pins of the second connector are connected to the pins of the second interface via the second cable. The third cable connects the first connector and the second connector.

[0010] This embodiment achieves flexible switching of signal transmission paths by setting an intermediate transfer structure for the signal transmission component. Compared to fixed wiring, the signal mapping relationship between the first and second interfaces can be quickly changed by replacing the connection relationship of the third cable, meeting the testing requirements of forward verification and cross-verification. It can be adapted to motherboards and memory modules of different specifications, eliminating the need to develop a separate motherboard for each memory module verification scenario. This solves the limitation of traditional verification schemes that require designing a separate motherboard for each verification scenario, reducing hardware adaptation costs.

[0011] In one possible implementation, the third cable is pluggable to both the first connector and the second connector.

[0012] In this embodiment, the third cable is a pluggable design. When the signal connection needs to be adjusted, it can be achieved simply by replacing or replugging the third cable. At the same time, it supports flexible replacement of the third cable of different lengths according to the verification requirements, thereby verifying the loss compensation function of the motherboard.

[0013] In one possible implementation, the first interface includes a first signal group and a second signal group respectively connected to the dual channels of the motherboard, and the second interface includes a third signal group and a fourth signal group respectively connected to the dual channels of the memory module; wherein...

[0014] Each signal group is used to transmit data for the corresponding channel, and the number of pins in each signal group matches the data bit width supported by the corresponding channel.

[0015] The signal group between the first interface and the second interface is connected through the signal transmission component.

[0016] This embodiment divides the pins of the first and second interfaces into signal groups, ensuring a one-to-one correspondence between the signal groups and the channels of the motherboard and memory module. This precisely adapts to the dual-channel architecture of the motherboard and memory module, ensuring that data transmission meets the channel width requirements and guaranteeing the complete reproduction of the parallel transmission characteristics of DDR memory during verification. Furthermore, the signal groups are connected via transmission components, supporting both the standard forward connection verification mode and the flexible implementation of cross-connection testing for channel fault tolerance. This enhances the specificity and accuracy of verifying core characteristics such as dual-channel signal coordination and compatibility.

[0017] In one possible implementation, the first signal group and the third signal group are connected through the signal transmission component, and the second signal group and the fourth signal group are connected through the signal transmission component.

[0018] This embodiment, by connecting the two signal groups of the two interfaces in a "forward" direction, can completely reproduce the standard dual-channel communication link between the motherboard and the memory module, ensuring that data is transmitted along the original channel path. It accurately verifies the signal integrity, timing matching, and data synchronization performance under normal working conditions, and can provide a benchmark reference for subsequent abnormal scenario testing, thereby improving the reliability of the verification.

[0019] In one possible implementation, the first signal group and the fourth signal group are connected through the signal transmission component, and the second signal group and the third signal group are connected through the signal transmission component.

[0020] This embodiment simulates an abnormal scenario where the motherboard and memory module are interchanged in dual channels by "cross-connecting" the two signal groups of the two interfaces. It accurately tests the system's fault tolerance capability for channel mismatch, address mapping error correction mechanism and data redirection function, verifies the compatibility of the memory controller with non-standard connections, and supplements the reliability verification covering extreme application scenarios.

[0021] In one possible implementation, the signal transmission component further includes a level signal control device connected to the first connector or the second connector.

[0022] This embodiment can verify the ECC (Error-Correcting Code) verification function of the motherboard. The level state of the DQ (Data Queue) data line of the DDR memory can be precisely adjusted (such as pulled high or pulled low) through the level signal control device. There is no need to rely on the traditional manual operation of changing the DQ signal line with tweezers. This realizes controllable error injection in the ECC verification scenario and ensures the repeatability and accuracy of the verification process.

[0023] In one possible implementation, the level signal control device includes at least one jumper cap; wherein a first pin of each jumper cap is connected to one of the pins of the first connector or the second connector, a second pin of each jumper cap is connected to a power input terminal, and a third pin of each jumper cap is grounded.

[0024] In this embodiment, the level signal control device is a jumper cap. As a mechanical adjustment element, the jumper cap allows for manual or automatic switching of signal levels through the corresponding connection of its level signal pins to specific pins on the connector. Furthermore, compared to complex electronic control circuits, the jumper cap has a simple structure, low cost, and can meet the needs of error-prone scenarios.

[0025] In one possible implementation, the level signal control device includes at least one resistor and its corresponding switching circuit; wherein, the first end of each resistor is connected to one of the pins of the first connector or the second connector, and the second end of each resistor is connected to the corresponding switching circuit.

[0026] The level signal control device in this embodiment is a combination of pull-up / pull-down resistors and a switching circuit. The switching circuit can be switched by an external control signal without manual plugging and unplugging, which can support the automated testing process of dynamic error injection scenarios and improve the verification efficiency of complex verification scenarios.

[0027] Compared with existing technologies, the adapter device disclosed in this utility model embodiment achieves flexible signal adjustment through the design of the adapter board body, dual interfaces, and modular signal transmission components. Utilizing a "first connector-third cable-second connector" architecture, it allows for quick switching between forward and cross connections by changing the connection method of the third cable, accurately covering multiple scenarios such as standard dual-channel verification and channel cross-testing without requiring hardware reconstruction. By flexibly adjusting interface specifications and pin mapping, it is compatible with DDR1 to DDR5 memory modules and different motherboards, reducing dedicated hardware development, lowering verification costs, and offering flexible operation. Scenario switching only requires changing the connection method of the third cable, without modifying fixed wiring, simplifying the process and shortening the verification cycle. Furthermore, the use of compatible cables reduces signal interference, the fixed connection structure ensures reliable contact, improves the accuracy of test results, and also enables proactive error injection, meeting the deep verification requirements of DDR memory modules. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the first structure of the adapter provided in this embodiment of the utility model;

[0029] Figure 2 This is a schematic diagram of the second structure of the adapter provided in this embodiment of the utility model;

[0030] Figure 3 This is a schematic diagram of the third structure of the adapter provided in this embodiment of the utility model;

[0031] Figure 4 This is a schematic diagram of the fourth structure of the adapter provided in this embodiment of the utility model;

[0032] Figure 5 This is a schematic diagram of the fifth structure of the adapter provided in this embodiment of the utility model;

[0033] Figure 6 This is a schematic diagram of the normal connection of the pins within the group provided in this embodiment of the utility model;

[0034] Figure 7This is a schematic diagram of the cross-connection of pins within a group provided in this embodiment of the utility model;

[0035] Figure 8 This is a schematic diagram of the normal pin connection between connectors provided in this embodiment of the utility model;

[0036] Figure 9 This is a schematic diagram of the pin cross connection between connectors provided in this embodiment of the utility model;

[0037] Figure 10 This is a schematic diagram of the installation position of the level signal control device provided in an embodiment of this utility model. Detailed Implementation

[0038] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0039] The adapter described in this embodiment of the utility model is implemented by combining forward connection and cross connection of signal groups in the compatibility verification of memory and motherboard. Since the traditional fixed connection adapter can only verify the signal transmission performance under the standard path, it cannot verify the compatibility of scenarios such as dual-channel interchange and abnormal mapping. Therefore, the signal groups of the two interfaces can be flexibly switched to cross connection through the signal transmission component, while retaining the forward connection mode, so as to realize the comprehensive verification of memory and motherboard under various connection scenarios.

[0040] See Figure 1 , Figure 1 This is a schematic diagram of the first structure of the adapter provided in this embodiment of the present invention, the adapter comprising:

[0041] Adapter board body 10;

[0042] The first interface 20 is located on one side of the adapter board body 10 and is used to connect to the motherboard;

[0043] The second interface 30 is located on the other side of the adapter board body 10 and is used to connect the memory module.

[0044] The signal transmission component 40 is connected to the corresponding pins of the first interface 20 and the second interface 30, respectively.

[0045] For example, the adapter plate body 10 is the basic carrier of the entire adapter device, providing a physical platform for the installation and connection of other components, and supporting the structure of the entire device.

[0046] The first interface 20 is installed on one side of the adapter board body 10. Its function is to connect to the motherboard, serving as the physical interface between the adapter and the motherboard, allowing the adapter to connect to the motherboard system. The first interface 20 has a keying notch 201 and several pins 202. The keying notch 201 is used to precisely mate with the keying structure of the motherboard interface, preventing incorrect insertion when the first interface 20 is connected to the motherboard and ensuring accurate pin alignment. The pins 202 are used to make contact with the corresponding pins of the motherboard interface to achieve signal transmission between the adapter and the motherboard, such as address signals, data signals, and control signals.

[0047] The second interface 30 is located on the other side of the adapter board body 10 and is used to connect the memory module. It serves as the port for establishing a connection between the adapter and the memory module. The second interface 30 also includes a foolproof notch 301 and several pins 302. The foolproof notch 301 is designed to match the foolproof design of the memory module interface, preventing the memory module from being connected to the second interface 30 in the wrong orientation and ensuring correct pin alignment. The pins 302 are used to make contact with the corresponding pins of the memory module to achieve signal interaction between the adapter and the memory module, enabling the transmission of data, instructions, etc.

[0048] The signal transmission component 40 acts as a bridge, connecting the corresponding pins of the first interface 20 and the second interface 30. This allows signals between the motherboard and the memory module to be transmitted between the first and second interfaces via the adapter board body and this component, enabling the interaction of data, instructions, and other signals. The diagram shows the structure connecting the upper and lower interfaces, ensuring a smooth signal path. This structural design allows the adapter to connect the motherboard and the memory module, providing the hardware foundation for communication between them.

[0049] It should be noted that since DDR has various models, and DDR5 uses an AB dual-channel configuration, which is significantly different from DDR1 to DDR4, this invention can improve the signal transmission component 40 of the adapter to adapt it to various DDR models. Furthermore, the first interface 20 and the second interface are different for different DDR protocols because the keying notch and / or pin count are different. When the adapter provided by this invention is applicable to different DDR1 to 5 memory modules, modules 20, 30, and 40 need to be adjusted to maintain consistency with the corresponding protocol.

[0050] Unlike DDR1-4, DDR5 memory modules employ a dual-channel design. DDR5 memory modules have 288 pins, including power and reverse insertion protection. In existing verification systems, the motherboard used for processor verification only has one type of memory slot, which cannot meet the corresponding functionality for A / B dual-channel swapping verification in DDR5. To implement A / B dual-channel swapping verification for both DDR5 UDIMM (Unbuffered Dual In-line Memory Module) and DDR5 RDIMM (Registered Dual In-line Memory Module), multiple motherboards would need to be designed, resulting in long development cycles and high costs.

[0051] See Figure 2 , Figure 2 This is a schematic diagram of a second structure of the adapter provided in this embodiment of the present invention. This adapter is suitable for DDR5 memory modules. In this case, the first interface 20 is connected to the motherboard 100, and the second interface 30 is connected to the memory module 200. The first interface 20 includes a first signal group 21 and a second signal group 22 respectively connected to the dual channels of the motherboard 100. The second interface 30 includes a third signal group 31 and a fourth signal group 32 respectively connected to the dual channels of the memory module 200. Each signal group is used to transmit data for the corresponding channel, and the number of pins in each signal group matches the data bit width supported by the corresponding channel. The signal groups between the first interface 20 and the second interface 30 are connected through the signal transmission component 40.

[0052] For example, the DDR5 memory module 200 adopts an A / B dual-channel design (i.e., the memory data path is physically split into two independent channels). When corresponding to the adapter, the first signal group 21 of the first interface 20 corresponds to the A channel of the motherboard 100, responsible for transmitting address, data, and control signals of the A channel; the second signal group 22 of the first interface 20 corresponds to the B channel of the motherboard 100, responsible for transmitting address, data, and control signals of the B channel; the third signal group 31 of the second interface 30 corresponds to the A channel of the memory module 200, responsible for transmitting A channel signals; and the fourth signal group 32 of the second interface 30 corresponds to the B channel of the memory module 200, responsible for transmitting B channel signals. In short, each signal group is a dedicated transmission link for a channel, ensuring independent and parallel data transmission between the A and B channels, simulating the native dual-channel architecture of DDR5.

[0053] The data width of a DDR5 channel is a fixed design, such as a single channel including a 32-bit data width and parity bits. Therefore, the number of pins in the signal group must match the data width. If a single DDR5 channel needs to transmit 32 bits of data and parity / control signals, the number of pins in the corresponding signal group must cover the data transmission pins (32 data pins), parity pins (ECC and other error correction checks), and control pins (read / write commands, clock synchronization, etc.) to ensure complete signal transmission. For example, assuming a single DDR5 channel includes a 32-bit data width and 8 bits of parity, each signal group pin must contain at least 40 functional pins (in practice, redundant / spare pins will be included, but the core is to match the data width requirement). The number of pins is the hardware carrier of the data width; matching the channel data transmission requirements with the number of physical pins ensures that signals are not lost and timing is aligned.

[0054] In this embodiment, the pins of the first interface 20 and the second interface 30 are divided into signal groups, so that each signal group corresponds one-to-one with the channels of the motherboard 100 and the memory module 200. This precisely adapts to the dual-channel architecture of the motherboard 100 and the memory module 200, ensuring that data transmission meets the channel width requirements and guaranteeing the complete reproduction of the parallel transmission characteristics of DDR5 memory during verification. Furthermore, the signal groups are connected through the transmission component 40, supporting both the standard forward connection verification mode and the flexible implementation of cross-connection testing of channel fault tolerance, thus improving the targeting and accuracy of verification of core characteristics such as dual-channel signal coordination and compatibility.

[0055] In one possible implementation, the first signal group 21 and the third signal group 31 are connected through the signal transmission component 40, and the second signal group 22 and the fourth signal group 32 are connected through the signal transmission component 40.

[0056] For example, such as Figure 2 As shown, the first signal group 21 of the first interface 20 is connected to the third signal group 31 of the second interface 30, realizing a direct connection of the A channel signal between the motherboard 100 and the memory module 200; the second signal group 22 of the first interface 20 is connected to the fourth signal group 32 of the second interface 30, realizing a direct connection of the B channel signal between the motherboard 100 and the memory module 200. The channel connection relationship satisfied at this time is AA, BB. The signal transmission component 40 is a cable, which directly connects the two signal groups. It should be noted that... Figure 2 The signal transmission component 40 only shows two lines, but in reality, there is a cable for each pin in the signal group, and the pins of the two signal groups need to be connected one-to-one. For example, the first signal group 21 and the third signal group 31 each have 32 pins, and the signal transmission component 40 needs to include 32 cables to connect the 32 pins one-to-one (the same applies to the second signal group 22 and the fourth signal group 32).

[0057] In this embodiment, by connecting the two signal groups of the two interfaces in a "forward" direction, the standard dual-channel communication link between the motherboard 100 and the memory module 200 can be fully reproduced, ensuring that data is transmitted along the original channel path. This accurately verifies the signal integrity, timing matching, and data synchronization performance under normal working conditions, providing a benchmark reference for subsequent abnormal scenario testing and improving verification reliability.

[0058] In one possible implementation, the first signal group 21 and the fourth signal group 32 are connected through the signal transmission component 40, and the second signal group 22 and the third signal group 31 are connected through the signal transmission component 40.

[0059] For example, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the third structure of the adapter provided in this embodiment of the utility model. The first signal group 21 of the first interface 20 is connected to the fourth signal group 32 of the second interface 30, realizing a direct signal connection between the A channel of the motherboard 100 and the B channel of the memory module 200; the second signal group 22 of the first interface 20 is connected to the third signal group 31 of the second interface 30, realizing a direct signal connection between the B channel of the motherboard 100 and the A channel of the memory module 200. The channel connection relationship satisfied at this time is: AB, BA.

[0060] In this embodiment, by "crossing" the two signal groups of the two interfaces, the abnormal scenario of dual-channel interchange between the motherboard 100 and the memory module 200 can be simulated. This accurately tests the system's fault tolerance capability for channel mismatch, address mapping error correction mechanism, and data redirection function, verifies the compatibility of the memory controller with non-standard connections, and supplements the reliability verification covering extreme application scenarios.

[0061] For DDR1 to DDR5, existing technologies require multiple motherboards to verify the feasibility of swapping signal pins within the same group of X8 slices and whether the pins of different X8 slices can be interchanged entirely. Therefore, this invention provides a compatible adapter. For signals within the same X8 slice, cross-connection of cables verifies the feasibility of swapping signal pins within the same group. Simultaneously, cross-connection of cables can be used to swap the pins of different X8 slices to verify the feasibility of swapping signals between different groups. It should be noted that a slice refers to a group of independent signal units, and "X8" indicates that this group of signals contains 8 bits of data (or related control / check signals), which is the basic unit of memory signal transmission. For example, if there are 8 signal lines (D0-D7) in a certain X8 group, verify whether it is feasible to "shuffle the order within the group" by swapping D0 and D1, or D2 and D5; or if there are two X8 groups (slice0 and slice1), verify whether it is feasible to swap all the signal lines of slice0 with all the signal lines of slice1.

[0062] See Figure 4 , Figure 4 This is a schematic diagram of the fourth structure of the adapter device provided in this utility model embodiment. The signal transmission component 40 includes a conductive connector disposed on the adapter board body 10, and at least two opposing first connectors 41 and second connectors 42. The conductive connector includes a first cable 401, a second cable 402 and a third cable 403. The pins of the first connector 41 are respectively connected to the pins of the first interface 20 through the first cable 401. The pins of the second connector 42 are respectively connected to the pins of the second interface 30 through the second cable 402. The third cable 403 connects the first connector 41 and the second connector 42.

[0063] For example, the conductive connector consists of a first cable 401, a second cable 402, and a third cable 403, serving as the physical transmission channel for signals. The first cable 401 establishes the connection between the first interface 20 and the first connector 41; the second cable 402 establishes the connection between the second interface 30 and the second connector 42; and the third cable 403 connects the first connector 41 and the second connector 42, enabling signal flow between interfaces and connectors, and between connectors. Signals from the motherboard side are transmitted via the first interface 20 pins and the first cable 401 to the first connector 41. Signals are transmitted with low loss between the two connectors via the third cable 403. Signals are then transmitted from the second connector 42, via the second cable 402, to the second interface 30 pins, and finally enter the memory module. The first connector 41 and the second connector 42 act as signal relay nodes, connected to cables via pins, allowing for flexible plugging and unplugging. This supports different signal path combinations and adapts to the signal transmission requirements of different DDR1 to DDR5 memory modules, such as adjusting the connection method to simulate dual-channel forward / switched, intra-group forward / crossover, and inter-group forward / crossover verification scenarios.

[0064] The third cable 403 is pluggable to both the first connector 41 and the second connector 42. The connection method of the third cable can be quickly changed and adjusted according to the verification scenario without redesigning the adapter board hardware. The first connector 41 and the second connector 42 are arranged opposite each other, and the number of each first connector 41 and second connector 42 is the same, as is the number of pins in each connector. Figure 4 The first connector 41 has n units (e.g., 8 units, the specific value of n can be set according to the number of pins of different DDR interface models), numbered 411 to 41n. Correspondingly, the second connector 42 also has n units, numbered 421 to 42n, and the number of pins in 411 to 41n and 421 to 42n are all the same. Only 1 to 2 cables are shown for the first cable 401, second cable 402, and third cable 403 in the figure. In actual applications, the number of cables corresponds one-to-one with the number of pins in the connectors. The first connector 41 and the second connector 42 can be SMA (Sub Miniature version A connector).

[0065] Because the third cable 403 is pluggable, the physical distance of the signal transmission path can be dynamically adjusted by changing its length, thereby altering signal loss (such as attenuation and delay) during transmission. Cable loss exhibits a regular pattern: the longer the cable, the greater the signal loss and the higher the delay. This adjustable loss characteristic can simulate signal attenuation states under different real-world application scenarios, such as: ① verifying the motherboard's driving capability by gradually increasing the cable length (increasing loss) and observing whether the motherboard can drive signal transmission normally, thus determining its maximum driving threshold; ② testing the loss tolerance limit by continuously extending the cable until the signal fails, accurately measuring the motherboard's maximum tolerance for signal loss. By setting the pluggable third cable 403, the above parameters can be monitored in real time without replacing hardware, simply by adjusting the cable length, providing precise data support for the reliability design of chips and systems.

[0066] In this embodiment, flexible switching of the signal transmission path is achieved by setting an intermediate transfer structure in the signal transmission component 40. Compared with fixed wiring, the signal mapping relationship between the first interface 20 and the second interface 30 can be quickly changed by changing the connection relationship of the third cable 403, meeting the testing requirements of forward verification and cross-verification. It can be adapted to motherboards and memory modules of different specifications, eliminating the need to develop a separate motherboard for each memory module verification scenario. This solves the limitation of traditional verification schemes that require designing a motherboard for each verification scenario, reducing hardware adaptation costs. In addition, the third cable 403 in this embodiment is a pluggable design. When it is necessary to adjust the signal connection relationship, it is only necessary to replace or replug the third cable 403. At the same time, it supports flexible replacement of third cables of different lengths according to verification requirements, thereby verifying the loss compensation function of the motherboard.

[0067] For DDR5 dual-channel interchange verification scenarios, Figure 4 The provided adapter is compatible Figures 2-3 The adapter structure enables dual-channel interchange verification between DDR5 memory and the motherboard. (See attached image.) Figure 5 , Figure 5 This is a fifth structural schematic diagram of the adapter provided in this embodiment of the utility model. Similarly, in this case, the first interface 20 includes a first signal group 21 and a second signal group 22 respectively connected to the dual channels of the motherboard, and the second interface 30 includes a third signal group 31 and a fourth signal group 32 respectively connected to the dual channels of the memory module; wherein, each signal group is used to transmit data of the corresponding channel, and the number of pins of each signal group matches the data bit width supported by the corresponding channel; the signal groups between the first interface 20 and the second interface 30 are connected by conductive connectors and at least two oppositely arranged first connectors 41 and second connectors 42.

[0068] For example, this adapter can achieve both forward and cross connections for dual channels:

[0069] 1) Forward connection mode: The first signal group 21 and the third signal group 31 are directly connected through the signal transmission component 40 composed of the conductive connector, the first connector 41 and the second connector 42. The second signal group 22 and the fourth signal group 32 are directly connected through the same set of signal transmission components 40, simulating the signal path of the motherboard and the memory modules A and B connected one-to-one.

[0070] 2) Cross-connection mode: The first signal group 21 and the fourth signal group 32 are cross-connected through the signal transmission component 40, and the second signal group 22 and the third signal group 31 are cross-connected through the corresponding signal transmission component, so as to realize the interchangeability verification of DDR5 memory module and motherboard A and B dual channels, and test the system's compatibility with channel mismatch without additional motherboard development.

[0071] For verification scenarios involving intra-group signal line interchange and component signal line interchange in DDR1-5, since there are multiple first connectors 41 and second connectors 42, they are grouped into pairs of opposite connectors, such as 411-421, 412-422, etc. When performing intra-group signal line cross-verification, all connector groups or some connector groups undergo intra-group pin cross-verification; when performing inter-group signal line cross-verification, all connector groups or some connector groups undergo full-group pin cross-verification. The following sections provide detailed explanations of these two verification scenarios.

[0072] 1) Intra-group verification scenario: For each connector group, the signal pins are cross-interchangeable, resulting in two situations:

[0073] Case 1: All signals within the group are connected in the forward direction. See [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of the normal pin connection within the group provided in this utility model embodiment. Taking the connector group "411-421" as an example, in this connector group, the pins D0 to D7 of connector 411 are connected to the pins D0 to D7 of connector 421 in a one-to-one forward manner. That is, D0 of 411 is connected to D0 of 421, D1 of 411 is connected to D1 of 421, and so on up to D7. This connection method can simulate the normal signal transmission path and is used to verify the stability and signal integrity of the connector group under conventional signal transmission scenarios, serving as a benchmark comparison scenario for cross-interchange verification of signals within the group.

[0074] Case 2: Some / all signals within the group are cross-connected; see [reference]. Figure 7 , Figure 7This is a schematic diagram of the pin cross-connection within the connector group provided in this embodiment of the utility model. In this connector group, the pins D0 to D7 of connector 411 and the pins D0 to D7 of connector 421 are not conventionally aligned, but are cross-connected through a third cable 403. For example, D0 of 411 can be connected to D1 of 421, and D1 of 411 can be connected to D0 of 421, and so on. All pins can be cross-connected, or only a portion can be swapped while the other portion remains connected normally (this can be flexibly adjusted according to the actual cross-connection design). By using this method of partial or complete pin cross-connection, abnormal scenarios such as pin misalignment and signal disorder that occur during signal transmission are simulated. This verifies the fault tolerance, error correction mechanism, and compatibility of the adapter and the connected motherboard, memory module, and other devices when facing non-standard signal transmission. It supplements the diverse scenarios of signal connection verification within the group and provides test conditions for comprehensively testing the stability of the equipment in complex signal environments.

[0075] 2) Inter-group verification scenario: In this case, signal pins of all connectors are cross-interchangeable, and there are two situations:

[0076] Case 1, positive connections between groups, see [link / reference] Figure 8 , Figure 8 This is a schematic diagram of the normal pin connection between connectors provided in the embodiment of this utility model. All the connectors that are arranged opposite to each other are connected in a corresponding manner, and the signals within the group are connected in the forward direction. For example, 411 and 421, 412 and 422 are directly connected according to D0~D0, D1~D1…D7~D7.

[0077] Case 2, partial / complete cross-connection between groups, see [link / reference] Figure 9 , Figure 9 This is a schematic diagram of the pin cross-connection between connectors provided in this embodiment of the utility model. The signal pins between connectors are cross-reconstructed across groups using a third cable 403. For partial cross-connection, specific connectors, such as 411-414 and 421-424, can be selected for cross-interchange, while the remaining connectors maintain their forward connections. For example, all pins of connector 411 can be cross-connected with all pins of connector 422 (in this case, 411 and 422 are directly connected according to D0-D0, D1-D1…D7-D7), simulating a mixed scenario of "partial channel misalignment, other channels normal," to verify the system's fault tolerance capability for asymmetric signal anomalies. For full cross-connection, cross-group cross-mapping is performed on all connectors, completely scrambling the correspondence between the pins of the first connector 41 and the second connector 42, such as 411 connected to 42n, 412 connected to 42n, etc., constructing an extreme condition of "global misalignment between motherboard channels and memory channels," testing the signal integrity of the adapter under complex signal topology, as well as the compatibility and error correction mechanism of the motherboard and memory modules for complete channel mismatch.

[0078] In this embodiment, intra-group cross-validation accurately simulates normal and abnormal signal transmission scenarios by connecting the pins within the connector group in both forward and cross directions. This verifies the device's fault tolerance and error correction capabilities for signal misalignment within the group, providing a fundamental test for component signal integrity. Inter-group cross-validation enables partial or complete cross-group signal reconstruction, covering local / global channel misalignment conditions. It can verify the system's compatibility and stability under complex topologies. Only cable connections need to be adjusted, allowing hardware reuse to complete tests from basic to extreme scenarios, significantly improving verification efficiency, reducing costs, helping to uncover potential device problems, and ensuring reliable communication between memory and motherboard.

[0079] In one possible implementation, the signal transmission component further includes a level signal control device connected to the first connector or the second connector.

[0080] For example, see Figure 10 , Figure 10 This is a schematic diagram showing the placement of the level signal control device 50 provided in this embodiment of the utility model. The level signal control device 50 can establish an electrical connection with the pins of the first connector 41 or the second connector 42 through a hardware interface to achieve precise control of the signal level. When verifying the ECC function of the motherboard, the level signal control device 50 can actively inject controllable errors into the DQ data line of the DDR memory, such as lowering the level of DQ3 to an abnormal threshold or raising the level of DQ7 to simulate signal interference, thereby triggering the ECC error correction mechanism of the motherboard. It should be noted that some or all of the pins of the first connector 41 or the second connector 42 can be externally connected to a level signal control device 50 to achieve more flexible signal intervention.

[0081] In this embodiment, the ECC verification function of the motherboard can be verified by the level signal control device 50. The level state of the DQ (Data Queue) data line of the DDR memory (such as pulling high or pulling low) can be precisely adjusted without relying on the traditional manual operation of changing the DQ signal line with tweezers. This realizes controllable error injection in the ECC verification scenario and ensures the repeatability and accuracy of the verification process.

[0082] In one possible implementation, the level signal control device 50 includes at least one jumper cap; wherein a first pin of each jumper cap is connected to one of the pins of the first connector 41 or the second connector 42, a second pin of each jumper cap is connected to a power input terminal, and a third pin of each jumper cap is grounded.

[0083] For example, the jumper cap adopts a 3-pin mechanical interface design. Pin 1 is fixedly connected to a pin in the first connector 41 or the second connector 42, pin 2 is connected to a preset power input terminal (such as the VDDQ power supply corresponding to the DDR1~DDR5 protocol interface), and pin 3 is directly grounded. When the jumper cap shorts pins 1 and 3, the DDR DQ line is forced to ground, simulating a low-level abnormality caused by interference; when the jumper cap shorts pins 1 and 2, the DDR DQ line is forced to high to the power supply level, simulating a high-level abnormality caused by overdrive; if the jumper cap does not short any pins, the target signal maintains normal transmission.

[0084] In this embodiment, the level signal control device 50 is a jump cap. As a mechanical adjustment element, the jump cap, through the corresponding connection of the level signal pins to specific pins of the connector, enables manual or automatic control (which can be achieved by combining a controller and analog circuits) switching of the signal level. Furthermore, compared to complex electronic control circuits, the jump cap has a simple structure, low cost, and can meet the needs of error-prone scenarios.

[0085] In one possible implementation, the level signal control device 50 includes at least one resistor and its corresponding switching circuit; wherein, the first end of each resistor is connected to one of the pins of the first connector 41 or the second connector 42, and the second end of each resistor is connected to the corresponding switching circuit.

[0086] For example, in the level signal control device 50, each resistor unit includes a pull-up resistor and a pull-down resistor. The first end of both resistors is connected to the pin of the first connector 41 or the second connector 42. The second end of the pull-up resistor is connected to the power input terminal, and the second end of the pull-down resistor is grounded. The second ends of the two resistors are connected in series with independent MOSFET switching circuits (forming a switching unit). When an abnormality occurs in the analog signal pull-up, an external control signal (such as a high level output from the motherboard GPIO) triggers the MOSFET corresponding to the pull-up resistor to turn on, and the MOSFET of the pull-down resistor turns off. The DQ line is clamped to a high level through the pull-up resistor, causing an overdrive fault in the analog signal. When an abnormality occurs in the analog signal pull-down, the control signal triggers the MOSFET of the pull-down resistor to turn on, and the MOSFET of the pull-up resistor turns off. The DQ line is grounded through the pull-down resistor, causing a short circuit fault in the analog signal. If no fault is required, both MOSFETs are turned off, and the DQ line maintains normal signal transmission.

[0087] In this embodiment, the level signal control device 50 is a combination of pull-up and pull-down resistors and a switching circuit. The switching circuit can be switched by an external control signal without manual plugging and unplugging, which can support the automated testing process of dynamic error injection scenarios and improve the verification efficiency of complex verification scenarios.

[0088] Compared with existing technologies, the adapter device disclosed in this utility model embodiment achieves flexible signal adjustment through the design of the adapter board body, dual interfaces, and modular signal transmission components. Utilizing a "first connector-third cable-second connector" architecture, it allows for quick switching between forward and cross connections by changing the connection method of the third cable, accurately covering multiple scenarios such as standard dual-channel verification and channel cross-testing without requiring hardware reconstruction. By flexibly adjusting interface specifications and pin mapping, it is compatible with DDR1 to DDR5 memory modules and different motherboards, reducing dedicated hardware development, lowering verification costs, and offering flexible operation. Scenario switching only requires changing the connection method of the third cable, without modifying fixed wiring, simplifying the process and shortening the verification cycle. Furthermore, the use of compatible cables reduces signal interference, the fixed connection structure ensures reliable contact, improves the accuracy of test results, and also enables proactive error injection, meeting the deep verification requirements of DDR memory modules.

[0089] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications are also considered to be within the protection scope of this utility model.

Claims

1. A switching device, characterized in that, include: Adapter board body; The first interface is located on one side of the adapter board body and is used to connect to the motherboard; The second interface is located on the other side of the adapter board body and is used to connect the memory module; The signal transmission component includes a conductive connector disposed on the adapter plate body, and at least two opposing first connectors and second connectors; The conductive connector includes a first cable, a second cable, and a third cable. The pins of the first connector are connected to the pins of the first interface via the first cable. The pins of the second connector are connected to the pins of the second interface via the second cable. The third cable connects the first connector and the second connector.

2. The adapter as described in claim 1, characterized in that, The third cable is pluggable to both the first connector and the second connector.

3. The adapter as described in claim 1 or 2, characterized in that, The first interface includes a first signal group and a second signal group respectively connected to the dual channels of the motherboard; the second interface includes a third signal group and a fourth signal group respectively connected to the dual channels of the memory module; wherein, Each signal group is used to transmit data for the corresponding channel, and the number of pins in each signal group matches the data bit width supported by the corresponding channel. The signal group between the first interface and the second interface is connected through the signal transmission component.

4. The adapter as described in claim 3, characterized in that, The first signal group and the third signal group are connected through the signal transmission component, and the second signal group and the fourth signal group are connected through the signal transmission component.

5. The adapter as described in claim 3, characterized in that, The first signal group and the fourth signal group are connected through the signal transmission component, and the second signal group and the third signal group are connected through the signal transmission component.

6. The adapter as described in claim 1, characterized in that, The signal transmission component further includes a level signal control device, which is connected to the first connector or the second connector.

7. The adapter as described in claim 6, characterized in that, The level signal control device includes at least one jumper cap; wherein, the first pin of each jumper cap is connected to one of the pins of the first connector or the second connector, the second pin of each jumper cap is connected to the power input terminal, and the third pin of each jumper cap is grounded.

8. The adapter as described in claim 6, characterized in that, The level signal control device includes at least one resistor and its corresponding switching circuit; wherein, the first end of each resistor is connected to one of the pins of the first connector or the second connector, and the second end of each resistor is connected to the corresponding switching circuit.

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