Signal amplification circuit, analog-to-digital conversion circuit, chip and electronic device

Abstract

The application relates to the chip technical field and provides a signal amplification circuit, an analog-digital conversion circuit, a chip and electronic equipment. The signal amplification circuit is used for amplifying an input signal and comprises a first amplification module, a second amplification module, a first feedback module, a second feedback module and a first chopping module. Since the first chopping module is connected with the first amplification module, the second amplification module, the first feedback module and the second feedback module respectively, the first chopping module is configured to control the first amplification module to alternately connect the first feedback module and the second feedback module and control the second amplification module to alternately connect the second feedback module and the first feedback module in a unit period, so that the first amplification module and the second amplification module can be made to exchange the feedback modules in the unit period, and thus the instantaneous noise voltage of the feedback resistors in the feedback modules can be offset, and the reliability of the signal amplification circuit is improved.

Description

Technical Field

[0001] This application belongs to the field of chip technology, and in particular relates to a signal amplification circuit, an analog-to-digital conversion circuit, a chip, and an electronic device. Background Technology

[0002] Signal amplifier circuits are commonly used in analog-to-digital converter circuits to amplify the input signal and increase its power. Because operational amplifiers in signal amplifier circuits have very high gain, even a small input signal voltage can easily cause the operational amplifier's output to reach its limit voltage. Therefore, appropriate feedback modules / feedback branches are needed to return a portion of the operational amplifier's output signal to the input terminal. This adjusts the operational amplifier's amplification of the input signal, controlling its gain and improving its stability.

[0003] However, in signal amplification circuits, feedback resistors are often used to construct feedback modules. This introduces flicker noise from the feedback resistors, thereby reducing the signal-to-noise ratio of the output signal of the signal amplification circuit. Utility Model Content

[0004] The purpose of this application is to provide a signal amplification circuit, an analog-to-digital conversion circuit, a chip, and an electronic device, with the aim of providing a signal amplification circuit solution that can remove flicker noise from the feedback module in the signal amplification circuit.

[0005] A first aspect of this application provides a signal amplification circuit, including:

[0006] The first amplification module and the second amplification module are used to amplify the first differential signal and the second differential signal respectively;

[0007] First feedback module and second feedback module;

[0008] The first chopper module is connected to the first amplification module, the second amplification module, the first feedback module, and the second feedback module respectively. The first chopper module is configured to control the first amplification module to alternately connect to the first feedback module and the second feedback module within a unit cycle, and to control the second amplification module to alternately connect to the second feedback module and the first feedback module.

[0009] This application provides a signal amplification circuit including a first amplification module, a second amplification module, a first feedback module, a second feedback module, and a first chopper module. The first and second amplification modules amplify a first differential signal and a second differential signal, respectively. Since the first chopper module is connected to the first, second, first, and second amplification modules, and configured to control the first amplification module to alternately connect to the first and second feedback modules within a unit cycle, and to control the second amplification module to alternately connect to the second and first feedback modules, the feedback modules of the first and second amplification modules can be interchanged within a unit cycle. This cancels the instantaneous noise voltage of the feedback resistors in each feedback module, effectively removing flicker noise from the feedback modules. In this way, the signal-to-noise ratio of the output signal of the signal amplification circuit can be avoided due to flicker noise from the feedback modules, thus improving the reliability of the signal amplification circuit.

[0010] A second aspect of this application provides an analog-to-digital conversion circuit, including the signal amplification circuit provided in the first aspect above; and an analog signal source for outputting an analog voltage as an input signal.

[0011] A third aspect of this application provides a chip that includes the signal amplification circuit provided in the first aspect; or

[0012] This chip is used to perform the analog-to-digital conversion circuit provided in the second aspect.

[0013] A fourth aspect of this application provides an electronic device, including the signal amplification circuit provided in the first aspect above; and / or

[0014] The electronic device includes the analog-to-digital conversion circuit provided in the second aspect above; or

[0015] The electronic device includes the chip provided in the third aspect mentioned above.

[0016] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a signal amplification circuit provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the specific structure of a signal amplification circuit provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram of the specific structure of a signal amplification circuit provided in another embodiment of this application;

[0020] Figure 4 for Figure 3 A specific circuit diagram of a signal amplification circuit according to an embodiment;

[0021] Figure 5 for Figure 4 An equivalent circuit diagram of a signal amplification circuit in the first chopping phase of the embodiment;

[0022] Figure 6 for Figure 4 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase of the embodiment;

[0023] Figure 7 A schematic diagram of the specific structure of a signal amplification circuit provided in another embodiment of this application;

[0024] Figure 8 for Figure 7 An embodiment provides a specific circuit diagram of a signal amplification circuit;

[0025] Figure 9 for Figure 8 An equivalent circuit diagram of a signal amplification circuit in the first chopping phase of the embodiment;

[0026] Figure 10 for Figure 8 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase of the embodiment;

[0027] Figure 11 This is a schematic diagram of the analog-to-digital conversion circuit provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 100. Signal amplification circuit;

[0030] 10. First amplification module;

[0031] 20. Second amplification module;

[0032] 30. First Feedback Module;

[0033] 40. Second Feedback Module;

[0034] 50. First chopper module;

[0035] 51. First chopper unit;

[0036] 52. Second chopper unit;

[0037] 53. Third chopper unit;

[0038] 60. Intermediate feedback module;

[0039] 70. Second chopper module;

[0040] 110. Analog signal source;

[0041] 200. Analog-to-digital conversion circuit. Detailed Implementation

[0042] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0043] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0045] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0047] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0048] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0049] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0050] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain.

[0051] Signal amplifier circuits are commonly used in analog-to-digital converter circuits to amplify the input signal and increase its power. Because operational amplifiers in signal amplifier circuits have very high gain, even a small input signal voltage can easily cause the operational amplifier's output to reach its limit voltage. Therefore, a corresponding feedback module is needed to return a portion of the operational amplifier's output signal to the input terminal. This adjusts the operational amplifier's amplification level of the input signal, thereby controlling the operational amplifier's gain and improving its stability.

[0052] For example, feedback resistors are often used to construct feedback modules in signal amplification circuits. Although chopper switches can be configured in signal amplification circuits, since chopper switches are generally only added to the input terminal and internally of the operational amplifier to remove the offset and flicker noise of the operational amplifier itself, the flicker noise of the feedback resistor is not processed, thereby reducing the signal-to-noise ratio of the output signal of the signal amplification circuit.

[0053] To address the aforementioned technical problems, this application provides a signal amplification circuit, including a first amplification module, a second amplification module, a first feedback module, a second feedback module, and a first chopper module. The first and second amplification modules amplify a first differential signal and a second differential signal, respectively. Since the first chopper module is connected to the first, second, first, and second amplification modules, and configured to control the first amplification module to alternately connect to the first and second feedback modules within a unit cycle, and to control the second amplification module to alternately connect to the second and first feedback modules, the feedback modules of the first and second amplification modules can be interchanged within a unit cycle. This cancels the instantaneous noise voltage of the feedback resistors in each feedback module, effectively removing flicker noise from the feedback modules. In this way, the signal-to-noise ratio of the output signal of the signal amplification circuit can be avoided due to flicker noise from the feedback modules, thus improving the reliability of the signal amplification circuit.

[0054] See Figure 1 , Figure 1 A schematic diagram of a signal amplification circuit provided in an embodiment of this application is shown. Figure 1 The signal amplification circuit 100 shown is used to amplify the input signal. The signal amplification circuit 100 includes: a first amplification module 10, a second amplification module 20, a first feedback module 30, a second feedback module 40, and a first chopper module 50. Specifically:

[0055] A first amplification module 10 and a second amplification module 20 are used to amplify the first differential signal and the second differential signal, respectively. A first feedback module 30 and a second feedback module 40 are also provided. A first chopper module 50 is connected to the first amplification module 10, the second amplification module 20, the first feedback module 30, and the second feedback module 40, respectively. The first chopper module 50 is configured to control the first amplification module 10 to alternately connect to the first feedback module 30 or the second feedback module 40, and to control the second amplification module 20 to alternately connect to the second feedback module 40 or the first feedback module 30, within a unit cycle.

[0056] In all embodiments of this application, the signal amplification circuit 100 is used to amplify the input signal, which is a differential signal, specifically including a first differential signal and a second differential signal. In the signal amplification circuit 100, the first amplification module 10 is used to amplify the first differential signal, and the second amplification module 20 is used to amplify the second differential signal. The signal is amplified through the output terminal (V...) of the signal amplification circuit 100. OUTP V OUTN The output consists of the amplified first differential signal and the amplified second differential signal.

[0057] In this embodiment, the first chopper module 50 is configured to control the first amplification module 10 to alternately connect to the first feedback module 30 or the second feedback module 40 within a unit cycle, and simultaneously control the second amplification module 20 to alternately connect to the second feedback module 40 or the first feedback module 30. That is, in the first half of the unit cycle, the first chopper module 50 controls the first amplification module 10 to connect to the first feedback module 30 and controls the second amplification module 20 to connect to the second feedback module 40; in the second half of the unit cycle, the first chopper module 50 controls the second amplification module 20 to connect to both the first and second feedback modules 30. Here, the unit cycle specifically refers to the minimum period of the clock signal used to control the operation of the first chopper module 50.

[0058] In a specific implementation, by providing a clock signal to the first chopper module 50, the first chopper module 50 can control the first amplification module 10 to alternately connect with the first feedback module 30 and the second feedback module 40 in each unit cycle, and at the same time control the second amplification module 20 to alternately connect with the second feedback module 40 and the first feedback module 30.

[0059] like Figure 1 As shown, the first amplification module 10 can be configured with a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first amplification module 10 is used to receive a first differential signal of the input signal, and the output terminal of the first amplification module 10 is used to output the amplified first differential signal. The second amplification module 20 can be configured with a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second amplification module 20 is used to receive a second differential signal of the input signal, and the output terminal of the second amplification module 20 is used to output the amplified second differential signal. When amplifying the differential signal using the signal amplification circuit 100, the first chopper module 50 can control the second input terminal of the first amplification module 10 to be alternately connected to the first feedback module 30 or the second feedback module 40, and simultaneously control the second input terminal of the second amplification module 20 to be alternately connected to the second feedback module 40 or the first feedback module 30.

[0060] It is readily understood that, in some embodiments, the first input terminal of the first amplification module 10 or the first input terminal of the second amplification module 20 may refer to the non-inverting input terminal of the operational amplifier, and the second input terminal of the first amplification module 10 or the second input terminal of the second amplification module 20 may refer to the inverting input terminal of the operational amplifier. In other embodiments, the first input terminal of the first amplification module 10 or the first input terminal of the second amplification module 20 may also refer to the inverting input terminal of the operational amplifier, and the second input terminal of the first amplification module 10 or the second input terminal of the second amplification module 20 may also refer to the non-inverting input terminal of the operational amplifier.

[0061] For example, the first amplification module 10 or the second amplification module 20 may include, but is not limited to, various types of operational amplifiers such as general-purpose integrated operational amplifiers, high-impedance integrated operational amplifiers, high-speed integrated operational amplifiers, high-voltage integrated operational amplifiers, power integrated operational amplifiers, wideband integrated operational amplifiers, high-precision integrated operational amplifiers, low-temperature drift integrated operational amplifiers, low-power integrated operational amplifiers, high-input impedance integrated operational amplifiers, and high-voltage high-power integrated operational amplifiers.

[0062] In this embodiment, the first feedback module 30 and the second feedback module 40 are used to provide feedback branches, respectively. The first chopper module 50 controls the first amplification module 10 to alternately connect to the first feedback module 30 and the second feedback module 40 within a unit cycle, and controls the second amplification module 20 to alternately connect to the second feedback module 40 and the first feedback module 30, which is equivalent to swapping the feedback branches of the first amplification module 10 and the second amplification module 20 within a unit cycle. In this way, the flicker noise of the first feedback module 30 and the second feedback module 40 can be canceled out within any unit cycle of the first chopper module 50.

[0063] For example, in a specific implementation, the first chopper module 50 includes at least two chopper branches, and the two chopper branches are controlled by a clock signal pair. In this example, during the first half-cycle of the clock signal pair, the first chopper module 50 can conduct the path between the first amplification module 10 and the first feedback module 30, and simultaneously conduct the path between the second amplification module 20 and the second feedback module 40. During the second half-cycle of the clock signal pair, the first chopper module 50 can conduct the path between the first amplification module 10 and the second feedback module 40, and simultaneously conduct the path between the second amplification module 20 and the first feedback module 30. In this way, the feedback branches of the first amplification module 10 and the second amplification module 20 can be interchanged within a unit cycle of the clock signal pair, thereby canceling the instantaneous noise voltage of the feedback resistors in each feedback module and removing the flicker noise of the first feedback module 30 and the second feedback module 40.

[0064] Figure 2A schematic diagram of the specific structure of a signal amplification circuit provided in an embodiment of this application is shown. Figure 2 As shown, the first amplification module 10 includes a first amplifier OP1, the first input terminal of which is used to input a first differential signal. The second amplification module 20 includes a second amplifier OP2, the first input terminal of which is used to input a second differential signal.

[0065] like Figure 2 As shown, the first chopper module 50 includes a first chopper unit 51, a second chopper unit 52, and a third chopper unit 53. The first chopper unit 51 controls the output terminals of the first amplifier OP1 and the second amplifier OP2 to be alternately connected to the first terminal of the first feedback module 30 or the first terminal of the second feedback module 40. The second chopper unit 52 controls the second input terminals of the first amplifier OP1 and the second amplifier OP2 to be alternately connected to the second terminal of the first feedback module 30 or the second terminal of the second feedback module 40. The third chopper unit 53 controls the first output terminal V of the signal amplification circuit 100. OUTP and the second output terminal V of the signal amplification circuit 100 OUTN They are alternately connected to the first end of the first feedback module 30 and the first end of the second feedback module 40.

[0066] exist Figure 2 In the example shown, the first input terminal of the first amplifier OP1 is the positive input terminal, and the second input terminal of the first amplifier OP1 is the negative input terminal. The positive input terminal of the first amplifier OP1 is used to input the first differential signal, and the negative input terminal of the first amplifier OP1 can be connected to the second terminal of the first feedback module 30 or the second feedback module 40 through the second chopper unit 52, thereby forming the feedback branch of the first amplifier OP1.

[0067] exist Figure 2 In the example shown, the first input terminal of the second amplifier OP2 is the positive input terminal, and the second input terminal of the second amplifier OP2 is the negative input terminal. The positive input terminal of the second amplifier OP2 is used to input the second differential signal, and the negative input terminal of the second amplifier OP2 can be connected to the second feedback module 40 or the first feedback module 30 through the second chopper unit 52, thereby forming the feedback branch of the second amplifier OP2.

[0068] Figure 3 A schematic diagram of the specific structure of a signal amplification circuit according to another embodiment of this application is shown. For example... Figure 3 As shown, the signal amplification circuit 100 also includes an intermediate feedback module 60. The intermediate feedback module 60 is connected between the first feedback module 30 and the second feedback module 40.

[0069] exist Figure 3In the example shown, the first end of the intermediate feedback module 60 is connected to the second end of the first feedback module 30 and written as the first intermediate node P1, and the second end of the intermediate feedback module 60 is connected to the second end of the second feedback module 40 and written as the second intermediate node P2. Figure 4 It shows Figure 3 A detailed circuit diagram of the embodiment. (For example...) Figure 4 As shown in the illustration, in one embodiment, the first feedback module 30 includes a first feedback resistor R21. The second feedback module 40 includes a second feedback resistor R22. The intermediate feedback module 60 includes an intermediate resistor R1.

[0070] The first end of the first feedback resistor R21 serves as the first end of the first feedback module 30 and is connected to the first chopper unit 51 to form the first end node Pa. The first end of the second feedback resistor R22 serves as the first end of the second feedback module 40 and is connected to the first chopper unit 51 to form the second end node Pb. The node formed by connecting the first end of the intermediate resistor R1 and the second end of the first feedback resistor R21 is the first intermediate node P1, and the node formed by connecting the second end of the intermediate resistor R1 and the second end of the second feedback resistor R22 is the second intermediate node P2.

[0071] Combination Figure 3 and Figure 4 The first input terminal V of the first amplifier OP1 IP The first input terminal V of the second amplifier OP2 is used to input the first differential signal. IN Used for inputting the second differential signal. The first chopper unit 51 includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The first terminal of the first switch SW1 and the first terminal of the second switch SW2 are connected to the output terminal of the first amplifier OP1, the second terminal of the first switch SW1 is connected to the first feedback module 30, and the second terminal of the second switch SW2 is connected to the second feedback module 40. The first terminals of the third switch SW3 and the fourth switch SW4 are connected to the output terminal of the second amplifier OP2, the second terminal of the third switch SW3 is connected to the first feedback module 30, and the second terminal of the fourth switch SW4 is connected to the second feedback module 40.

[0072] like Figure 4As shown, the second terminal of the first switch SW1 is connected to the first feedback module 30, specifically to the first terminal of the first feedback resistor R21, forming the first terminal node Pa. The second terminal of the third switch SW3 is connected to the first feedback module 30, specifically to the first terminal of the first feedback resistor R21, i.e., connected to the first terminal node Pa. The second terminal of the second switch SW2 is connected to the second feedback module 40, specifically to the first terminal of the second feedback resistor R22, forming the second terminal node Pb. The second terminal of the fourth switch SW4 is connected to the second feedback module 40, specifically to the first terminal of the second feedback resistor R22, i.e., connected to the second terminal node Pb.

[0073] exist Figure 4 In this configuration, the second chopper unit 52 includes a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, and an eighth switch SW8. The first terminals of the fifth switch SW5 and the sixth switch SW6 are connected to the second input terminal of the first amplifier OP1, and the second terminal of the fifth switch SW5 is connected to the first feedback module 30. The second terminal of the sixth switch SW6 is connected to the second feedback module 40. The first terminals of the seventh switch SW7 and the eighth switch SW8 are connected to the second input terminal of the second amplifier OP2. The second terminal of the seventh switch SW7 is connected to the first feedback module 30. The second terminal of the eighth switch SW8 is connected to the second feedback module 40.

[0074] like Figure 4 As shown, the second end of the fifth switch SW5 is connected to the first feedback module 30, specifically to the second end of the first feedback resistor R21, forming the first intermediate node P1. The second end of the eighth switch SW8 is connected to the second feedback module 40, specifically to the second end of the second feedback resistor R22, forming the second intermediate node P2.

[0075] exist Figure 4 In the third chopper unit 53, there are a ninth switch SW9, a tenth switch SW10, an eleventh switch SW11, and a twelfth switch SW12. The first terminals of the ninth switch SW9 and the tenth switch SW10 are connected to the first feedback module 30. The second terminal of the ninth switch SW9 is connected to the first output terminal V of the signal amplification circuit 100. OUTP The second terminal of the tenth switch SW10 is connected to the second output terminal V of the signal amplifier circuit 100. OUTN The first terminal of the eleventh switch SW11 and the first terminal of the twelfth switch SW12 are connected to the second feedback module 40. The second terminal of the eleventh switch SW11 is connected to the first output terminal V of the signal amplifier circuit 100. OUTP The second terminal of the twelfth switch SW12 is connected to the second output terminal V of the signal amplifier circuit 100. OUTN .

[0076] For example, combined Figures 1 to 4 ,At once Figure 4 The working principle of the signal amplification circuit shown is explained below. In this example, during practical use, a preset clock signal can be used to control the first chopper unit 51, the second chopper unit 52, and the third chopper unit 53 in the first chopper module 50. Here, the preset clock signal pair can specifically include a first clock signal and a second clock signal. The first clock signal and the second clock signal are a non-overlapping clock signal pair, that is, the first clock signal and the second clock signal are out of phase. Figure 4 In this circuit, the first switch SW1, the fourth switch SW4, the fifth switch SW5, the eighth switch SW8, the ninth switch SW9, and the twelfth switch SW12 are controlled by the first clock signal. The second switch SW2, the third switch SW3, the sixth switch SW6, the seventh switch SW7, the tenth switch SW10, and the eleventh switch SW11 are controlled by the second clock signal.

[0077] In this embodiment, the first clock signal and the second clock signal can be divided into a first chopping phase and a second chopping phase within a unit period.

[0078] As one possible implementation, in the first chopping phase, the first clock signal is high and the second clock signal is low; in the second chopping phase, the first clock signal is low and the second clock signal is high.

[0079] As another possible implementation, in the first chopping phase, the first clock signal is low and the second clock signal is high; in the second chopping phase, the first clock signal is high and the second clock signal is low.

[0080] Based on the examples above, Figure 5 It shows Figure 4 An equivalent circuit diagram of a signal amplification circuit in the first chopping phase is shown in the embodiment. Figure 6 It shows Figure 4 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase is shown in the embodiment. It should be noted that... Figure 5 and Figure 6 In the clock signal pair, within a unit cycle, the noise models of the first feedback resistor R21, the intermediate resistor R1, and the second feedback resistor R22 can all be represented as the resistors themselves connected in series with a voltage source. That is, in Figure 5 and Figure 6In the diagram, voltage source Vn1 represents the instantaneous noise voltage of the intermediate resistor R1, voltage source Vn21 represents the instantaneous noise voltage of the first feedback resistor R21, and voltage source Vn22 represents the instantaneous noise voltage of the second feedback resistor R22. However, in the actual circuit, the first feedback resistor R21, the intermediate resistor R1, and the second feedback resistor R22 are not connected to voltage sources Vn1, Vn21, and Vn22 respectively.

[0081] Combination Figure 4 and Figure 5 Taking the first chopping phase, where the first clock signal is high and the second clock signal is low, as an example, switches SW1, SW4, SW5, SW8, SW9, and SW12 are closed. Simultaneously, switches SW2, SW3, SW6, SW7, SW10, and SW11 are open. At this time, the connection relationships of each unit in the signal amplifier circuit 100 are as follows: Figure 5 As shown. Here, the feedback branch of the first amplifier OP1 is the first feedback resistor R21. The feedback branch of the second amplifier OP2 is the second feedback resistor R22. Taking into account the instantaneous value of the feedback resistor noise voltage, the instantaneous value of the output voltage of the signal amplifier circuit 100 during the first chopping phase can be expressed as:

[0082]

[0083] Among them, V OUTP -V OUTN R is the output voltage of the signal amplifier circuit 100, which can also be understood as the amplified signal voltage value output by the signal amplifier circuit 100. R1 is the resistance value of the intermediate resistor R1. 21 R is the resistance value of the first feedback resistor R21. 22 This is the resistance value of the second feedback resistor R22. V IP -VIN is the input voltage of the signal amplifier circuit 100, which can also be understood as the voltage value corresponding to the input signal of the signal amplifier circuit 100. V n,21 V represents the instantaneous noise voltage value of the first feedback resistor R21. n,22 V represents the instantaneous noise voltage value of the second feedback resistor R22. n,1 This is the instantaneous noise voltage value of the intermediate resistor R1.

[0084] Based on the examples above, Figure 6 It shows Figure 4 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase is shown in the embodiment. (Combined with...) Figure 4 and Figure 6Taking the second chopping phase, where the first clock signal is low and the second clock signal is high, as an example, switches SW1, SW4, SW5, SW8, SW9, and SW12 are open. Simultaneously, switches SW2, SW3, SW6, SW7, SW10, and SW11 are closed. At this time, the connection relationships of each unit in the signal amplifier circuit 100 are as follows: Figure 6 As shown. Here, the feedback branch of the first amplifier OP1 changes from the first feedback resistor R21 to the second feedback resistor R22. The feedback branch of the second amplifier OP2 changes from the second feedback resistor R22 to the first feedback resistor R21. That is, within a unit period of a preset clock signal pair (from the first chopping phase to the second chopping phase), the feedback branch interchange between the first amplification module 10 and the second amplification module 20 is realized. Since the noise voltage of the feedback resistor changes slowly with time, the noise voltage of the feedback resistor remains almost unchanged when the clock signal pair changes from the first chopping phase to the second chopping phase. Taking into account the instantaneous value of the noise voltage of the feedback resistor, the instantaneous value of the output voltage of the signal amplification circuit 100 in the second chopping phase can be expressed as:

[0085]

[0086] Among them, V OUTP -V OUTN R is the output voltage of the signal amplifier circuit 100, which can also be understood as the amplified signal voltage value output by the signal amplifier circuit 100. R1 is the resistance value of the intermediate resistor R1. 21 R is the resistance value of the first feedback resistor R21. 22 This is the resistance value of the second feedback resistor R22. V IP -VIN is the input voltage of the signal amplifier circuit 100, which can also be understood as the voltage value corresponding to the input signal of the signal amplifier circuit 100. V n,21 V represents the instantaneous noise voltage value of the first feedback resistor R21. n,22 V represents the instantaneous noise voltage value of the second feedback resistor R22. n,1 This is the instantaneous noise voltage value of the intermediate resistor R1.

[0087] The average of the instantaneous values ​​of the two output voltages in the first and second chopping phases can be obtained as follows: Therefore, by swapping the feedback branches between the first amplification module 10 and the second amplification module 20 within a unit cycle of the clock signal pair, the instantaneous noise voltage V of the first feedback resistor R21 can be removed. n,21 The instantaneous noise voltage V of the second feedback resistor R22 n,22And the instantaneous noise voltage V of the intermediate resistor R1 n,1 This removes the flicker noise from each resistor in the first feedback module 30, the second feedback module 40, and the intermediate feedback module 60.

[0088] As one embodiment, the signal amplification circuit further includes a second chopper module. In this embodiment, the first amplification module includes a first amplifier and a second amplifier, with the output terminal of the first amplifier connected to the input terminal of the second amplifier. The second amplification module includes a third amplifier and a fourth amplifier, with the output terminal of the third amplifier connected to the input terminal of the fourth amplifier. Here, the second chopper module is configured to alternately receive a first differential signal at the first and second input terminals of the first amplifier, and alternately connect the first and second output terminals of the first amplifier to the first and second input terminals of the second amplifier, and alternately receive a second differential signal at the first and second input terminals of the third amplifier, and alternately connect the first and second output terminals of the third amplifier to the first and second input terminals of the fourth amplifier.

[0089] Figure 7 A schematic diagram of the specific structure of a signal amplification circuit provided in another embodiment of this application is shown. For example... Figure 7 As shown, the first amplification module 10 includes a first amplifier OP11 and a second amplifier OP12, with the output of the first amplifier OP11 connected to the input of the second amplifier OP12. The second amplification module 20 includes a third amplifier OP21 and a fourth amplifier OP22, with the output of the third amplifier OP21 connected to the input of the fourth amplifier OP22.

[0090] In this embodiment, the second chopper module 70 is configured to alternately receive the first differential signal at the first input terminal and the second input terminal of the first amplifier OP11, and alternately connect the first output terminal and the second output terminal of the first amplifier OP11 to the first input terminal and the second input terminal of the second amplifier OP12, and alternately receive the second differential signal at the first input terminal and the second input terminal of the third amplifier OP21, and alternately connect the first output terminal and the second output terminal of the third amplifier OP21 to the first input terminal and the second input terminal of the fourth amplifier OP22.

[0091] In one possible implementation, the second chopper module 70 may include multiple sets of switch pairs, with the first amplifier OP11 and the third amplifier OP21 respectively embedded between the multiple sets of switch pairs. By controlling the on and off of each switch pair, the first and second input terminals of the first amplifier OP11 can alternately receive the first differential signal, the first and second output terminals of the first amplifier OP11 can alternately connect to the first and second input terminals of the second amplifier OP12, the first and second input terminals of the third amplifier OP21 can alternately receive the second differential signal, and the first and second output terminals of the third amplifier OP21 can alternately connect to the first and second input terminals of the fourth amplifier OP22 and the second input terminals of the second amplifier.

[0092] like Figure 7 As shown in the figure, as an embodiment, the first chopper module 50 includes a first chopper unit 51, a second chopper unit 52 and a third chopper unit 53.

[0093] In this embodiment, the first chopper unit 51 controls the output terminals of the second amplifier OP12 and the fourth amplifier OP22 to be alternately connected to the first terminal of the first feedback module 30 or the first terminal of the second feedback module 40. The second chopper unit 52 controls the second input terminal and the first input terminal of the first amplifier OP11 to be alternately connected to the second terminal of the second feedback module 40 or the second terminal of the first feedback module 30, and controls the second input terminal and the first input terminal of the third amplifier OP21 to be alternately connected to the second terminal of the first feedback module 30 or the second terminal of the second feedback module 40. The third chopper unit 53 controls the first output terminal V of the signal amplification circuit 100. OUTP and the second output terminal V of the signal amplification circuit 100 OUTN They are alternately connected to the first end of the first feedback module 30 and the first end of the second feedback module 40.

[0094] As one embodiment, the second chopper module 70 includes a fourth chopper unit and a fifth chopper unit (not shown in the figure). In this embodiment, the fourth chopper unit is used to control the first input terminal and the second input terminal of the first amplifier to alternately receive the first differential signal, and to control the first input terminal and the second input terminal of the third amplifier to alternately receive the second differential signal. The fifth chopper unit is used to control the first output terminal and the second output terminal of the first amplifier to alternately connect to the first input terminal and the second input terminal of the second amplifier, and to control the first output terminal and the second output terminal of the third amplifier to alternately connect to the first input terminal and the second input terminal of the fourth amplifier.

[0095] Figure 8 It shows Figure 7 The specific circuit diagram of the signal amplification circuit provided in the embodiment is shown below. (In conjunction with...) Figure 7 and Figure 8 In this embodiment, the first chopper unit 51 includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4.

[0096] Combination Figure 7 and Figure 8 The first terminal of the first switch SW1 and the first terminal of the second switch SW2 are connected to the output terminal of the second amplifier OP12, and the second terminal of the first switch SW1 is connected to the first feedback module 30. The second terminal of the second switch SW2 is connected to the second feedback module 40. The first terminal of the third switch SW3 and the first terminal of the fourth switch SW4 are connected to the output terminal of the fourth amplifier OP22, and the second terminal of the third switch SW3 is connected to the first feedback module 30. The second terminal of the fourth switch SW4 is connected to the second feedback module 40.

[0097] exist Figure 8 Specifically, the second terminal of the first switch SW1 can be connected to the first terminal of the first feedback resistor R21 to form the first terminal node Pa. The second terminal of the second switch SW2 can be connected to the first terminal of the second feedback resistor R22 to form the second terminal node Pb. The second terminal of the third switch SW3 can be connected to the first terminal of the first feedback resistor R21. The second terminal of the fourth switch SW4 can be connected to the first terminal of the second feedback resistor R22.

[0098] Combination Figure 7 and Figure 8 In this embodiment, the second chopper unit 52 includes a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, and an eighth switch SW8. The first end of the fifth switch SW5 is connected to the second end of the second feedback module 40, and the second end of the fifth switch SW5 is connected to the first input end of the first amplifier OP11. The first end of the sixth switch SW6 is connected to the second end of the first feedback module 30, and the second end of the sixth switch SW6 is connected to the second input end of the first amplifier OP11. The first end of the seventh switch SW7 is connected to the second end of the first feedback module 30, and the second end of the seventh switch SW7 is connected to the first input end of the third amplifier OP21. The first end of the eighth switch SW8 is connected to the second end of the second feedback module 40, and the second end of the eighth switch SW8 is connected to the second input end of the third amplifier OP21.

[0099] exist Figure 8 In this configuration, the first terminal of the fifth switch SW5 and the first terminal of the eighth switch SW8 can be specifically connected to the second terminal of the second feedback resistor R22 to form a second intermediate node P2. The first terminal of the sixth switch SW6 and the first terminal of the seventh switch SW7 can be specifically connected to the second terminal of the first feedback resistor R21 to form a first intermediate node P1.

[0100] In this embodiment, the third chopper unit 53 includes a ninth switch SW9, a tenth switch SW10, an eleventh switch SW11, and a twelfth switch SW12. The first terminals of the ninth switch SW9 and the tenth switch SW10 are connected to the first feedback module 30, and the second terminal of the ninth switch SW9 is connected to the first output terminal V of the signal amplification circuit 100. OUTP The second terminal of the tenth switch SW10 is connected to the second output terminal V of the signal amplifier circuit 100. OUTN The first terminal of the eleventh switch SW11 and the first terminal of the twelfth switch SW12 are connected to the second feedback module 40, and the second terminal of the eleventh switch SW11 is connected to the first output terminal V of the signal amplifier circuit 100. OUTP The second terminal of the twelfth switch SW12 is connected to the second output terminal V of the signal amplifier circuit 100. OUTN .

[0101] In this embodiment, the fourth chopper unit includes a thirteenth switch SW13, a fourteenth switch SW14, a fifteenth switch SW15, and a sixteenth switch SW16.

[0102] The first terminal of the thirteenth switch SW13 and the first terminal of the fourteenth switch SW14 are used to receive the first differential signal. The second terminal of the thirteenth switch SW13 is connected to the first input terminal of the first amplifier OP11, and the second terminal of the fourteenth switch SW14 is connected to the second input terminal of the first amplifier OP11. The first terminal of the fifteenth switch SW15 and the first terminal of the sixteenth switch SW16 are used to receive the second differential signal. The second terminal of the fifteenth switch SW15 is connected to the first input terminal of the third amplifier OP21, and the second terminal of the sixteenth switch SW16 is connected to the second input terminal of the third amplifier OP21.

[0103] In this embodiment, the fifth chopper unit includes a seventeenth switch SW17, an eighteenth switch SW18, a nineteenth switch SW19, a twentieth switch SW20, a twenty-first switch SW21, a twenty-second switch SW22, a twenty-third switch SW23, and a twenty-fourth switch SW24. The first terminals of the seventeenth switch SW17 and the nineteenth switch SW19 are connected to the first output terminal of the first amplifier OP11. The first terminals of the eighteenth switch SW18 and the twentyth switch SW20 are connected to the second output terminal of the first amplifier OP11. The second terminals of the seventeenth switch SW17 and the eighteenth switch SW18 are connected to the first input terminal of the second amplifier OP12. The second terminals of the nineteenth switch SW19 and the twentyth switch SW20 are connected to the second input terminal of the second amplifier OP12. The first terminal of the twenty-second switch SW22 and the first terminal of the twenty-fourth switch SW24 are connected to the first output terminal of the third amplifier OP21. The first terminal of the twenty-first switch SW21 and the first terminal of the twenty-third switch SW23 are connected to the second output terminal of the third amplifier OP21. The second terminal of the twenty-third switch SW23 and the second terminal of the twenty-fourth switch SW24 are connected to the first input terminal of the fourth amplifier OP22. The second terminal of the twenty-first switch SW21 and the second terminal of the twenty-second switch SW22 are connected to the second input terminal of the fourth amplifier OP22.

[0104] For example, combined Figures 7 to 8 ,At once Figure 8 The working principle of the signal amplification circuit shown is explained below. In this example, during practical use, a preset clock signal can be used to operate the first chopper unit 51, the second chopper unit 52, and the third chopper unit 53 in the first clock chopper module 50, and the fourth and fifth chopper units in the second clock chopper module 70. Here, the preset clock signal pair can specifically include a first clock signal and a second clock signal. In specific implementation, the first clock signal and the second clock signal can also be a complementary clock signal pair, that is, the first clock signal and the second clock signal have opposite phases. Figure 8 In this circuit, switches SW1 (first), SW4 (fourth), SW6 (sixth), SW8 (eighth), SW9 (ninth), SW12 (twelfth), SW13 (thirteenth), SW15 (fifteenth), SW17 (seventeenth), SW20 (twentieth), SW21 (twentieth), and SW24 (twentieth) are controlled by the first clock signal. Switches SW2 (second), SW3 (third), SW5 (fifth), SW7 (seventh), SW10 (tenth), SW11 (eleventh), SW14 (fourteenth), SW16 (sixteenth), SW18 (eighteenth), SW19 (nineteenth), SW22 (twentieth), and SW23 (twenty-third) are controlled by the second clock signal.

[0105] In this embodiment, the first clock signal and the second clock signal can be divided into a first chopping phase and a second chopping phase within a unit period.

[0106] As one possible implementation, in the first chopping phase, the first clock signal is high and the second clock signal is low; in the second chopping phase, the first clock signal is low and the second clock signal is high.

[0107] As another possible implementation, in the first chopping phase, the first clock signal is low and the second clock signal is high; in the second chopping phase, the first clock signal is high and the second clock signal is low.

[0108] Based on the examples above, Figure 9 It shows Figure 8 An equivalent circuit diagram of a signal amplification circuit in the first chopping phase is shown in the embodiment. Figure 10 It shows Figure 8 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase is shown in the embodiment. It should be noted that... Figure 9 and Figure 10 In the preset clock signal pair, within a unit period, the noise models of the first feedback resistor R21, the intermediate resistor R1, and the second feedback resistor R22 can all be represented as the resistors themselves connected in series with a voltage source (not shown in the figure).

[0109] Combination Figure 8 and Figure 9 Taking the first chopping phase, where the first clock signal is high and the second clock signal is low, as an example, switches SW1, SW4, SW6, SW8, SW9, SW12, SW13, SW15, SW17, SW20, SW21, and SW24 are closed. Simultaneously, switches SW2, SW3, SW5, SW7, SW10, SW11, SW14, SW16, SW18, SW19, SW22, and SW23 are open. At this time, the connection relationships of each unit in the signal amplification circuit 100 are as follows: Figure 9 As shown. Here, the feedback branch of the first amplification module 10 is the first feedback resistor R21. The feedback branch of the second amplification module 20 is the second feedback resistor R22. Taking into account the instantaneous value of the feedback resistor noise voltage, the instantaneous value of the output voltage of the signal amplification circuit 100 during the first chopping phase can be expressed as:

[0110]

[0111] Among them, V OUTP -V OUTN R is the output voltage of the signal amplifier circuit 100, which can also be understood as the amplified signal voltage value output by the signal amplifier circuit 100. R1 is the resistance value of the intermediate resistor R1. 21 R is the resistance value of the first feedback resistor R21. 22 This is the resistance value of the second feedback resistor R22. V IP -VIN is the input voltage of the signal amplifier circuit 100, which can also be understood as the voltage value corresponding to the input signal of the signal amplifier circuit 100. V n,21 V represents the instantaneous noise voltage value of the first feedback resistor R21. n,22 V represents the instantaneous noise voltage value of the second feedback resistor R22. n1 This is the instantaneous noise voltage value of the intermediate resistor R1.

[0112] Based on the examples above, Figure 10 It shows Figure 8 An equivalent circuit diagram of a signal amplification circuit in the second chopping phase is shown in the embodiment. (Combined with...) Figure 8 and Figure 10 Taking the second chopping phase, where the first clock signal is low and the second clock signal is high, as an example, switches SW1, SW4, SW6, SW8, SW9, SW12, SW13, SW15, SW17, SW20, SW21, and SW24 are open. Simultaneously, switches SW2, SW3, SW5, SW7, SW10, SW11, SW14, SW16, SW18, SW19, SW22, and SW23 are closed. At this time, the connection relationships of each unit in the signal amplification circuit 100 are as follows: Figure 10As shown. Here, the feedback branch of the first amplification module 10 changes from the first feedback resistor R21 to the second feedback resistor R22. The feedback branch of the second amplification module 20 changes from the second feedback resistor R22 to the first feedback resistor R21. That is, within a unit period of a preset clock signal pair (from the first chopping phase to the second chopping phase), the feedback branches between the first amplification module 10 and the second amplification module 20 are interchanged. Since the noise voltage of the feedback resistor changes slowly with time, the noise voltage of the feedback resistor remains almost unchanged when the clock signal pair changes from the first chopping phase to the second chopping phase. Taking into account the instantaneous values ​​of the resistor noise voltage in the first feedback module 30 and the second feedback module 40, the instantaneous value of the output voltage of the signal amplification circuit 100 in the second chopping phase can be expressed as:

[0113]

[0114] Among them, V OUTP -V OUTN R is the output voltage of the signal amplifier circuit 100, which can also be understood as the amplified signal voltage value output by the signal amplifier circuit 100. R1 is the resistance value of the intermediate resistor R1. 21 R is the resistance value of the first feedback resistor R21. 22 This is the resistance value of the second feedback resistor R22. V IP -VIN is the input voltage of the signal amplifier circuit 100, which can also be understood as the voltage value corresponding to the input signal of the signal amplifier circuit 100. V n,21 V represents the instantaneous noise voltage value of the first feedback resistor R21. n,22 V represents the instantaneous noise voltage value of the second feedback resistor R22. n,1 This is the instantaneous noise voltage value of the intermediate resistor R1.

[0115] The average of the instantaneous values ​​of the two output voltages in the first and second chopping phases can be obtained as follows: Therefore, by swapping the feedback branches between the first amplification module 10 and the second amplification module 20 within a unit cycle of the clock signal pair, the instantaneous noise voltage V of the first feedback resistor R21 can be removed. n,21 The instantaneous noise voltage V of the second feedback resistor R22 n,22 And the instantaneous noise voltage V of the intermediate resistor R1 n,1 This eliminates the flicker noise from each feedback resistor.

[0116] Furthermore, in this embodiment, in addition to swapping the feedback branches between the first amplification module 10 and the second amplification module 20 within a unit period of a preset clock signal pair (from the first chopping phase to the second chopping phase), the input and output terminals of the first amplifier OP11 in the first amplification module 10, as well as the input and output terminals of the second amplifier OP12, can also be swapped. Similarly, the input and output terminals of the second amplifier OP22 in the second amplification module 20, as well as the input and output terminals of the fourth amplifier OP14, can be swapped. This achieves chopping of the first amplifier OP11 and the third amplifier OP21, thereby suppressing / removing the offset voltage and flicker noise of the first amplifier OP11 and the third amplifier OP21, and further improving the overall reliability of the signal amplification circuit 100.

[0117] Figure 11 A schematic diagram of the analog-to-digital conversion circuit provided in an embodiment of this application is shown. Figure 11 As shown in the figure, this application embodiment also provides an analog-to-digital converter circuit 200, such as... Figure 11 As shown, the analog-to-digital conversion circuit 200 includes: the signal amplification circuit 100 and the analog signal source 110 provided in the above embodiment.

[0118] In this embodiment, the analog signal source 110 is used to output an analog voltage as an input signal. For example... Figure 11 As shown, the input signal can specifically be a differential signal pair including a first differential signal and a second differential signal.

[0119] As one possible implementation, in practice, there can be multiple analog signal sources 110, each of which can be connected to the signal amplifier circuit 100 via a path switch (not shown in the figure). Here, by selecting different path switches, the input signal can be switched.

[0120] It is understood that the improvements and specific implementation methods of the analog-to-digital converter circuit 200 provided in this embodiment, which are related to this application, are all in... Figures 1 to 10 The embodiments shown are described in detail, so they will not be repeated here.

[0121] This application also provides a chip, which includes the signal amplification circuit 100 and / or the analog-to-digital conversion circuit 200 provided in the above embodiments. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the signal amplification circuit 100 and / or the analog-to-digital conversion circuit 200 provided in the above embodiments, it possesses all the beneficial effects of the signal amplification circuit 100 and / or the analog-to-digital conversion circuit 200 in the above embodiments. Furthermore, the improvements and specific implementation methods related to this application are all detailed in... Figures 1 to 10 The embodiments shown are described in detail, so they will not be repeated here.

[0122] This application also provides an electronic device, which includes a device body and at least one or any one of the following: a signal amplification circuit 100, an analog-to-digital conversion circuit 200, and a chip, all disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0123] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A signal amplification circuit, characterized by, include: The first amplification module and the second amplification module are used to amplify the first differential signal and the second differential signal respectively; First feedback module and second feedback module; The first chopper module is connected to the first amplification module, the second amplification module, the first feedback module, and the second feedback module respectively. The first chopper module is configured to control the first amplification module to alternately connect to the first feedback module or the second feedback module within a unit cycle, and to control the second amplification module to alternately connect to the second feedback module or the first feedback module.

2. The signal amplification circuit as described in claim 1, characterized in that, The first amplification module includes a first amplifier, and the first input terminal of the first amplifier is used to input a first differential signal; The second amplification module includes a second amplifier, and the first input terminal of the second amplifier is used to input a second differential signal; The first chopper module includes a first chopper unit, a second chopper unit, and a third chopper unit; The first chopper unit is used to control the output terminals of the first amplifier and the second amplifier to be alternately connected to the first terminal of the first feedback module or the first terminal of the second feedback module; The second chopper unit is used to control the second input terminal of the first amplifier and the second input terminal of the second amplifier to be alternately connected to the second terminal of the first feedback module or the second terminal of the second feedback module; The third chopper unit is used to control the first output terminal and the second output terminal of the signal amplification circuit to be alternately connected to the first terminal of the first feedback module and the first terminal of the second feedback module.

3. The signal amplification circuit as described in claim 1 or 2, characterized in that, Also includes: An intermediate feedback module is connected between the first feedback module and the second feedback module.

4. The signal amplification circuit as described in claim 2, characterized in that, The first chopper unit includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch and the first terminal of the second switch are connected to the output terminal of the first amplifier, the second terminal of the first switch is connected to the first feedback module, and the second terminal of the second switch is connected to the second feedback module; the first terminal of the third switch and the first terminal of the fourth switch are connected to the output terminal of the second amplifier, the second terminal of the third switch is connected to the first feedback module, and the second terminal of the fourth switch is connected to the second feedback module. The second chopper unit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first end of the fifth switch and the first end of the sixth switch are connected to the second input terminal of the first amplifier, the second end of the fifth switch is connected to the first feedback module, and the second end of the sixth switch is connected to the second feedback module; the first end of the seventh switch and the first end of the eighth switch are connected to the second input terminal of the second amplifier, the second end of the seventh switch is connected to the first feedback module, and the second end of the eighth switch is connected to the second feedback module. The third chopper unit includes a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch; The first end of the ninth switch and the first end of the tenth switch are connected to the first feedback module, the second end of the ninth switch is connected to the first output terminal of the signal amplification circuit, and the second end of the tenth switch is connected to the second output terminal of the signal amplification circuit; the first end of the eleventh switch and the first end of the twelfth switch are connected to the second feedback module, the second end of the eleventh switch is connected to the first output terminal of the signal amplification circuit, and the second end of the twelfth switch is connected to the second output terminal of the signal amplification circuit.

5. The signal amplification circuit as described in claim 1, characterized in that, The first amplification module includes a first amplifier and a second amplifier, with the output terminal of the first amplifier connected to the input terminal of the second amplifier; The second amplification module includes a third amplifier and a fourth amplifier, with the output of the third amplifier connected to the input of the fourth amplifier; The signal amplification circuit further includes a second chopper module, which is configured to alternately receive the first differential signal at the first input terminal and the second input terminal of the first amplifier, and alternately connect the first output terminal and the second output terminal of the first amplifier to the first input terminal and the second input terminal of the second amplifier, and alternately receive the second differential signal at the first input terminal and the second input terminal of the third amplifier, and alternately connect the first output terminal and the second output terminal of the third amplifier to the first input terminal and the second input terminal of the fourth amplifier.

6. The signal amplification circuit as described in claim 5, characterized in that, The first chopper module includes a first chopper unit, a second chopper unit, and a third chopper unit; The first chopper unit is used to control the output terminals of the second amplifier and the fourth amplifier to be alternately connected to the first terminal of the first feedback module or the first terminal of the second feedback module; The second chopper unit is used to control the second input terminal and the first input terminal of the first amplifier to be alternately connected to the second terminal of the second feedback module or the second terminal of the first feedback module, and to control the second input terminal and the first input terminal of the third amplifier to be alternately connected to the second terminal of the first feedback module or the second terminal of the second feedback module; The third chopper unit is used to control the first output terminal and the second output terminal of the signal amplification circuit to be alternately connected to the first terminal of the first feedback module and the first terminal of the second feedback module. The second chopper module includes a fourth chopper unit and a fifth chopper unit; The fourth chopper unit is used to control the first input terminal and the second input terminal of the first amplifier to alternately receive the first differential signal, and to control the first input terminal and the second input terminal of the third amplifier to alternately receive the second differential signal. The fifth chopper unit is used to control the first output terminal and the second output terminal of the first amplifier to be alternately connected to the first input terminal and the second input terminal of the second amplifier, and to control the first output terminal and the second output terminal of the third amplifier to be alternately connected to the first input terminal of the fourth amplifier and the second input terminal of the second amplifier.

7. The signal amplification circuit as described in claim 6, characterized in that, The first chopper unit includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch and the first terminal of the second switch are connected to the output terminal of the second amplifier, the second terminal of the first switch is connected to the first feedback module, and the second terminal of the second switch is connected to the second feedback module; the first terminal of the third switch and the first terminal of the fourth switch are connected to the output terminal of the fourth amplifier, the second terminal of the third switch is connected to the first feedback module, and the second terminal of the fourth switch is connected to the second feedback module. The second chopper unit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first end of the fifth switch is connected to the second end of the second feedback module, and the second end of the fifth switch is connected to the first input end of the first amplifier. The first end of the sixth switch is connected to the second end of the first feedback module, and the second end of the sixth switch is connected to the second input end of the first amplifier. The first end of the seventh switch is connected to the second end of the first feedback module, and the second end of the seventh switch is connected to the first input end of the third amplifier. The first end of the eighth switch is connected to the second end of the second feedback module, and the second end of the eighth switch is connected to the second input end of the third amplifier. The third chopper unit includes a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch; The first terminal of the ninth switch and the first terminal of the tenth switch are connected to the first feedback module, the second terminal of the ninth switch is connected to the first output terminal of the signal amplification circuit, and the second terminal of the tenth switch is connected to the second output terminal of the signal amplification circuit; the first terminal of the eleventh switch and the first terminal of the twelfth switch are connected to the second feedback module, the second terminal of the eleventh switch is connected to the first output terminal of the signal amplification circuit, and the second terminal of the twelfth switch is connected to the second output terminal of the signal amplification circuit. The fourth chopper unit includes a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; The first terminal of the thirteenth switch and the first terminal of the fourteenth switch are used to receive the first differential signal. The second terminal of the thirteenth switch is connected to the first input terminal of the first amplifier. The second terminal of the fourteenth switch is connected to the second input terminal of the first amplifier. The first terminal of the fifteenth switch and the first terminal of the sixteenth switch are used to receive the second differential signal. The second terminal of the fifteenth switch is connected to the first input terminal of the third amplifier. The second terminal of the sixteenth switch is connected to the second input terminal of the third amplifier. The fifth chopper unit includes the seventeenth switch, the eighteenth switch, the nineteenth switch, the twentieth switch, the twenty-first switch, the twenty-second switch, the twenty-third switch, and the twenty-fourth switch; The first terminal of the seventeenth switch and the first terminal of the nineteenth switch are connected to the first output terminal of the first amplifier, the first terminal of the eighteenth switch and the first terminal of the twentieth switch are connected to the second output terminal of the first amplifier, the second terminal of the seventeenth switch and the second terminal of the eighteenth switch are connected to the first input terminal of the second amplifier, and the second terminal of the nineteenth switch and the second terminal of the twentieth switch are connected to the second input terminal of the second amplifier. The first terminals of the 22nd switch and the 24th switch are connected to the first output terminal of the third amplifier. The first terminals of the 21st switch and the 23rd switch are connected to the second output terminal of the third amplifier. The second terminals of the 23rd switch and the 24th switch are connected to the first input terminal of the fourth amplifier. The second terminals of the 21st switch and the 22nd switch are connected to the second input terminal of the fourth amplifier.

8. An analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes: the signal amplification circuit according to any one of claims 1 to 7; and... An analog signal source is used to output an analog voltage as an input signal.

9. A chip, characterized in that, The chip includes the signal amplification circuit according to any one of claims 1 to 7; and / or The chip includes the analog-to-digital converter circuit as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes the signal amplification circuit according to any one of claims 1 to 7; and / or The electronic device includes the analog-to-digital conversion circuit of claim 8; and / or The electronic device includes the chip of claim 9.

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