A control device for large dynamic suppression

Abstract

The utility model relates to the field of electronic control technology, specifically disclose a control device of big dynamic suppression, including signal input module, three -level series connection VGA, detection and feedback module and FPGA control module. Through attenuation network and synchronous trigger mechanism realize >=90dB dynamic suppression, single -stage insertion loss <=0.5dB, integrated double -channel square law detector and ANFIS temperature compensation model, guarantee multi -channel phase consistency and environmental adaptability, modular design supports hot plug replacement, and the device is applicable to the high dynamic signal processing scene of electric power and communication field.

Description

Technical Field

[0001] This application relates to the field of electronic control technology, and specifically discloses a control device for large dynamic suppression. Background Technology

[0002] In scenarios such as radar signal reception and power system transient overvoltage suppression, the signal dynamic range often exceeds 90dB. For example, radar receiving systems need to simultaneously process strong direct signals and weak reflected signals from the antenna. Traditional technologies typically employ discrete attenuators, multi-stage amplifiers, and analog control circuits to achieve dynamic suppression, but these methods have the following drawbacks:

[0003] Insertion loss and noise degradation: External attenuators and switching devices introduce additional insertion loss (≥2dB), which increases the system noise figure and reduces signal sensitivity.

[0004] Poor multi-channel synchronization: Discrete gain adjustment cannot guarantee the phase consistency of the sum and difference signals, affecting the angle measurement accuracy or communication quality.

[0005] Insufficient response speed: The response time of analog control circuits often exceeds 10ms, making it difficult to adapt to rapid changes in sudden signals (such as radar pulses with a pulse width ≤1μs), resulting in signal distortion or equipment overload.

[0006] Poor environmental adaptability: Temperature changes cause gain drift (typical value ±2dB / 10℃), and traditional compensation schemes have low accuracy, affecting the long-term stability of the system.

[0007] Therefore, the inventors have provided a control device for large dynamic suppression in order to solve the above-mentioned problems. Summary of the Invention

[0008] This invention provides a control device for large dynamic range suppression. Through a three-stage series variable gain amplifier (VGA), a synchronous triggering mechanism, and intelligent temperature compensation, it achieves signal suppression within a certain dynamic range, while reducing insertion loss, improving multi-channel synchronization, and enhancing environmental adaptability.

[0009] To achieve the above objectives, the basic solution of this utility model provides a control device for large dynamic suppression, including a signal input module, a gain control module, a detection and feedback module, a control module, and a power supply module; the gain control module consists of three series-connected variable gain amplifiers, each VGA containing a π-shaped attenuation network and a digitally controlled attenuation unit; the detection and feedback module includes a square-law detector and a temperature sensor for real-time detection of signal power and ambient temperature; the control module is based on an FPGA or microcontroller and generates a synchronous trigger signal to adjust the attenuation amount.

[0010] Furthermore, the numerically controlled attenuation unit has a built-in latch. After receiving control commands, it uses a synchronization pulse signal to synchronously adjust the attenuation of multiple channels, ensuring that the sum and difference signals are in phase.

[0011] Furthermore, the π-shaped attenuation network is composed of multiple resistors, supports a dynamic range adjustment of 0-30dB, a single-stage insertion loss of ≤0.5dB, and a total dynamic range of ≥90dB for the three cascaded stages.

[0012] Furthermore, the signal input module includes a bandpass filter and a limiting circuit that supports 50Ω / 75Ω impedance matching and can filter out ±10MHz out-of-band noise.

[0013] Furthermore, the power module supports wide voltage input, has built-in reverse connection protection and ripple suppression circuit, and the output voltage stability is ≤±1%.

[0014] Furthermore, the control module communicates with external devices via SPI or I²C interfaces, supporting remote configuration of gain parameters and real-time monitoring of signal status.

[0015] Furthermore, the detection and feedback module integrates a dual-channel square-law detector, which can simultaneously monitor the power of the main signal and the reference signal, with a dynamic range detection accuracy of ≤±1dB.

[0016] Furthermore, the control module uses FPGA to realize dynamic collaborative control of multi-level VGA, with a response time of ≤1ms and supports instantaneous gain adjustment for burst signals.

[0017] The principle and effect of this basic scheme are as follows:

[0018] High dynamic range: Three-level VGA series connection achieves ≥90dB dynamic suppression capability, suitable for high-requirement scenarios such as strong signal suppression in aerospace telemetry and control, and transient overvoltage suppression in power systems.

[0019] Low insertion loss and high synchronization: The single-stage insertion loss of the π-shaped attenuation network is ≤0.5dB, the synchronous triggering mechanism ensures phase consistency of multiple channels, and the system noise figure is reduced by 15%.

[0020] Fast response and adaptation: FPGA control response time ≤1ms, which can adapt to burst signals with pulse width ≥1μs; ANFIS model dynamically compensates for temperature effects, and the gain stability is improved to ±0.5dB.

[0021] High reliability and easy maintenance: Wide voltage power supply modules support harsh power supply environments, and modular design reduces the replacement time of faulty units by 70%.

[0022] Flexible expansion: Supports SPI / I²C communication interface, can be integrated into intelligent monitoring system to realize remote parameter configuration and status diagnosis. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This paper shows an overall schematic diagram of a control device for large dynamic suppression according to an embodiment of this application;

[0025] Figure 2 The timing logic diagram of the synchronous trigger signal of a control device for large dynamic range suppression according to an embodiment of this application is shown;

[0026] Figure 3 A flowchart of a temperature compensation algorithm for a control device for large dynamic suppression proposed in an embodiment of this application is shown. Detailed Implementation

[0027] To further illustrate the technical means and effects adopted by this utility model in order to achieve the intended utility model purpose, the following detailed description of the specific implementation methods, structure, features and effects of this utility model is provided in conjunction with the accompanying drawings and preferred embodiments.

[0028] A control device for large dynamic suppression, implementing, for example Figure 1 , Figure 2 , Figure 3 As shown: It includes a signal input module, a gain control module, a detection and feedback module, a control module, and a power supply module.

[0029] The signal input module includes a bandpass filter and a limiting circuit, supports 50Ω / 75Ω impedance matching, can filter out ±10MHz out-of-band noise, and suppress signal overload.

[0030] The gain control module consists of three cascaded variable gain amplifiers (VGAs). Each VGA stage includes a π-shaped attenuation network and a digitally controlled attenuation unit. The π-shaped attenuation network is composed of multiple resistors, supporting a dynamic range adjustment of 0-30dB. The insertion loss of a single stage is ≤0.5dB, and the total dynamic range of the three cascaded stages is ≥90dB. The digitally controlled attenuation unit has a built-in latch. After receiving control commands, it uses a synchronization pulse signal to synchronously adjust the attenuation of multiple channels, ensuring phase consistency with the differential signal.

[0031] The detection and feedback module includes a square-law detector and a temperature sensor for real-time detection of signal power and ambient temperature. The detection and feedback module integrates a dual-channel square-law detector, which can simultaneously monitor the power of the main signal and the reference signal, with a dynamic range detection accuracy of ≤±1dB. The temperature sensor can collect ambient temperature data in real time and compensate for gain drift (compensation accuracy ±0.5dB) through a temperature-gain correction curve or an S-adaptive neural fuzzy inference system model.

[0032] The control module, based on an FPGA or microcontroller, generates a synchronous trigger signal to adjust the attenuation. It integrates a temperature compensation algorithm, using a preset temperature-gain correction curve (compensation accuracy ±0.5dB) or a dynamic compensation model based on ANFIS (Adaptive Neural Fuzzy Inference System) to correct the impact of ambient temperature on gain in real time. The control module communicates with external devices via SPI or I²C interfaces, supporting remote configuration of gain parameters and real-time monitoring of signal status.

[0033] The temperature compensation algorithm steps include:

[0034] Step S1: Initialize the temperature sensor, set the sampling frequency (e.g., 10Hz) and temperature range (-40℃ to 85℃).

[0035] Step S2: Collect ambient temperature data T in real time and calculate the temperature change rate ΔT / Δt.

[0036] Step S3: Determine the compensation mode:

[0037] Mode 1 (Preset Temperature-Gain Correction Curve): If ΔT / Δt≤1℃ / s, the preset linear / nonlinear compensation curve is invoked (e.g., gain correction ΔG=K×T, where K is the temperature coefficient).

[0038] Mode 2 (ANFIS Dynamic Model): If ΔT / Δt > 1℃ / s or the system enables adaptive learning, input T into the ANFIS model, and generate ΔG through fuzzy rule base and neural network inference.

[0039] Step S4: Calculate the total gain compensation ΔG_total = ΔG_preset / ANFIS + ΔG_calibration (calibration value is the factory calibration offset).

[0040] Step S5: Send ΔG_total to the control module to adjust the attenuation of the three-level VGA to achieve real-time gain correction.

[0041] Step S6: Verify the compensation effect using a square-law detector. If the error is > ±0.5dB, trigger the online update of the ANFIS model parameters.

[0042] The control module uses FPGA to realize dynamic collaborative control of multi-level VGA, with a response time of ≤1ms and supports instantaneous gain adjustment for burst signals (pulse width ≥1μs).

[0043] Figure 2 The timing logic diagram for the synchronous trigger signal specifically includes the following timing signals: CLK (system clock signal): reference clock, frequency 10MHz, duty cycle 50%;

[0044] DATA (control command signal): Serial data containing attenuation configuration parameters for the three-level VGA;

[0045] LATCH_EN (Latch Enable Signal): During the high level, DATA is written to the latch;

[0046] SYNC_PULSE (synchronization pulse signal): The rising edge triggers all latches to synchronously update the decay amount.

[0047] Detailed implementation method (synchronous trigger signal timing logic)

[0048] The synchronous triggering mechanism of this invention achieves synchronous adjustment of the attenuation of multiple channels through precise timing control. The specific process is as follows:

[0049] Data loading phase:

[0050] The control module receives external commands (such as the target attenuation amount) through the SPI interface and generates serial data (DATA signal).

[0051] At the rising edge of CLK, the DATA signal is transmitted bit by bit to the latches of each VGA level, and the data format is [VGA1 attenuation value (8 bits) + VGA2 attenuation value (8 bits) + VGA3 attenuation value (8 bits)].

[0052] When the LATCH_EN signal is set to high, the latches of the three-level VGA simultaneously receive and temporarily store the corresponding attenuation value in the DATA signal (e.g., Figure 3 (middle t1-t2 stage).

[0053] Synchronization triggering phase:

[0054] After the data loading is complete (at time t2), the LATCH_EN signal is pulled low, and the latch enters the hold state.

[0055] The control module generates a SYNC_PULSE rising edge pulse with a width of 100ns (at time t3), which triggers all latches to synchronously output the temporarily stored attenuation value to the π-shaped attenuation network.

[0056] The attenuation of the three-level VGA is updated synchronously within 10ns after the rising edge of SYNC_PULSE (t3-t4 stage), ensuring that the phase error of the sum and difference signals is ≤0.5°.

[0057] Timing constraints and advantages:

[0058] Clock synchronization: CLK and SYNC_PULSE are generated from the same FPGA clock source, with clock jitter ≤1ns, avoiding timing deviation.

[0059] Response speed: The total delay from DATA loading to attenuation taking effect is ≤1ms (including SPI communication time), meeting the requirement for rapid suppression of burst signals (pulse width ≥1μs).

[0060] Anti-interference design: The SYNC_PULSE signal uses differential transmission (LVDS level) and has a common-mode noise immunity of ≥20dB to ensure trigger reliability.

[0061] The power module supports wide voltage input (5-24V DC), has built-in reverse connection protection and ripple suppression circuit, and output voltage stability ≤±1%.

[0062] The usage process of this utility model is as follows:

[0063] Taking aerospace telemetry and control system applications as an example:

[0064] Signal input: The radio frequency signal enters the bandpass filter after being matched with a 50Ω impedance to filter out external noise of ±10MHz. The limiting circuit limits the signal amplitude to within ±5V.

[0065] Dynamic inhibition:

[0066] The first-stage VGA adjusts the attenuation (0-30dB) through a π-shaped attenuation network based on feedback from the square-law detector.

[0067] The control module receives external commands through the SPI interface, generates a synchronization pulse signal, and the latches of the three-level VGA simultaneously update the attenuation value to ensure that the sum and difference signals are adjusted synchronously.

[0068] Temperature compensation:

[0069] The temperature sensor collects ambient temperature data, and the FPGA calls the ANFIS model to calculate the compensation value (such as -0.1dB / ℃) to correct the gain parameters in real time.

[0070] Power Management: The power module converts the 24V input to a stable ±12V and 5V output with ripple ≤10mV to power each unit.

[0071] This invention achieves dynamic suppression of ≥90dB and single-stage insertion loss of ≤0.5dB through a π-shaped attenuation network and a synchronous triggering mechanism; it integrates a dual-channel square-law detector and an ANFIS temperature compensation model to ensure multi-channel phase consistency and environmental adaptability; its modular design supports hot-swappable replacement and is suitable for high-dynamic signal processing scenarios in aerospace, power and communication fields.

[0072] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A control device for large dynamic suppression, characterized by, It includes a signal input module, a gain control module, a detection and feedback module, a control module, and a power supply module; the gain control module consists of three stages of variable gain amplifiers connected in series, each stage of which includes a π-shaped attenuation network and a digitally controlled attenuation unit; the detection and feedback module includes a square-law detector and a temperature sensor for real-time detection of signal power and ambient temperature; the control module is based on an FPGA or microcontroller and generates a synchronous trigger signal to adjust the attenuation.

2. A control device for large dynamic suppression according to claim 1, characterized in that, The numerically controlled attenuation unit has a built-in latch. After receiving control commands, it uses a synchronization pulse signal to synchronously adjust the attenuation of multiple channels, ensuring that the sum and difference signals are in phase.

3. A control device for large dynamic suppression according to claim 1, characterized in that, The π-shaped attenuation network consists of multiple resistors, supports a dynamic range adjustment of 0-30dB, a single-stage insertion loss of ≤0.5dB, and a total dynamic range of ≥90dB for the three cascaded stages.

4. The control device for large dynamic suppression according to claim 1, characterized in that, The signal input module includes a bandpass filter and a limiting circuit, supports 50Ω / 75Ω impedance matching, and can filter out ±10MHz out-of-band noise.

5. The control device for large dynamic suppression according to claim 1, characterized in that, The power module supports wide voltage input, has built-in reverse connection protection and ripple suppression circuit, and output voltage stability ≤±1%.

6. The control device for large dynamic suppression according to claim 1, characterized in that, The control module communicates with external devices via SPI or I²C interfaces, supporting remote configuration of gain parameters and real-time monitoring of signal status.

7. The control device for large dynamic suppression according to claim 1, characterized in that, The detection and feedback module integrates a dual-channel square-law detector, which can simultaneously monitor the power of the main signal and the reference signal, with a dynamic range detection accuracy of ≤±1dB.

8. The control device for large dynamic suppression according to claim 1, characterized in that, The control module uses FPGA to implement dynamic collaborative control of multi-level VGAs, with a response time of ≤1ms and supports instantaneous gain adjustment for burst signals.

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