Clock signal generation circuit, qubit read link, and quantum computer

Abstract

The application discloses a clock signal generation circuit, a quantum bit reading link and a quantum computer, a frequency multiplication module, which is used for frequency multiplication processing of a reference signal to generate a first clock signal containing multiple frequency components; a first power division module, which is electrically connected with the output end of the frequency multiplication module to divide the first clock signal into multiple second clock signals; a first filtering module, which is electrically connected with one output end of the first power division module to perform filtering processing on one second clock signal and output a third clock signal of one frequency component; and a second filtering module, which is electrically connected with another output end of the first power division module to perform filtering processing on another second clock signal and output a fourth clock signal of another frequency component. The third clock signal and the fourth clock signal generated by the application are stable in phase difference and can be used as reading input sampling clock and reading output sampling clock to improve the accuracy of reading results.

Description

Technical Field

[0001] This utility model relates to the field of quantum computer technology, and in particular to a clock signal generation circuit, a quantum bit readout link, and a quantum computer. Background Technology

[0002] A quantum chip is the core component for running quantum computing, integrating multiple qubits. To ensure the proper functioning of these qubits, a dedicated quantum control system is required. This system contains multiple signal modules that provide various control signals to each qubit, such as frequency control signals and quantum state control signals. When the quantum chip performs a quantum computing task, the frequency control signal and quantum state control signal are first applied to the qubit to initiate the computation process. After the computation is complete, a readout signal is applied to obtain the result.

[0003] During the reading of qubits, two critical clock signals need to be applied: one is the read input sampling clock, which controls the transmission of the read signal, and the other is the read output sampling clock, which controls the reception of the signal. The timing accuracy of these two clock signals directly determines the accuracy of the qubit reading result. However, in existing read chains, the phase difference stability between the read input sampling clock and the read output sampling clock is insufficient. This phase difference instability reduces the accuracy of the reading result, thereby affecting the overall performance and reliability of quantum computing.

[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a clock signal generation circuit, a quantum bit readout link, and a quantum computer. The clock signal generation circuit generates a third clock signal and a fourth clock signal with a stable phase difference, which can be used as the input sampling clock and the output sampling clock for reading, thereby improving the accuracy of the reading results.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] The first aspect of this utility model provides a clock signal generation circuit, comprising:

[0008] The frequency multiplier module is used to multiply the frequency of the reference signal to generate a first clock signal containing multiple frequency components.

[0009] The first power divider module has its input terminal electrically connected to the output terminal of the frequency multiplier module to divide the first clock signal into multiple second clock signals.

[0010] The first filtering module has its input terminal electrically connected to one output terminal of the first power divider module to filter a second clock signal and output a third clock signal with one frequency component.

[0011] The second filtering module has its input terminal electrically connected to another output terminal of the first power divider module to filter another second clock signal and output a fourth clock signal with another frequency component.

[0012] The clock signal generation circuit described above, further comprising the frequency multiplication module, includes:

[0013] Multiple comb spectrum generators connected in series, wherein the multiple comb spectrum generators sequentially perform frequency multiplication on the received signal to output a signal with multiple frequency components, such that the last comb spectrum generator generates a first clock signal containing multiple frequency components.

[0014] At least one filter unit is electrically connected between any two adjacent comb spectrum generators, and the filter unit is used to filter the received signal.

[0015] The clock signal generation circuit described above, further, includes a frequency multiplier module comprising: a frequency multiplier and a comb spectrum generator;

[0016] The frequency multiplier is used to multiply the reference signal to output a signal with a fixed frequency; the input terminal of the comb spectrum generator is electrically connected to the output terminal of the frequency multiplier, and is used to multiply the fixed frequency signal to output a first clock signal containing multiple frequency components.

[0017] The clock signal generation circuit described above, further comprising the first filtering module, includes:

[0018] The first amplifier has its input terminal electrically connected to one output terminal of the first power divider module to perform power amplification processing on one of the second clock signals;

[0019] The first filter has its input terminal electrically connected to the output terminal of the first amplifier to filter the second clock signal after power amplification and output a third clock signal with one frequency component.

[0020] The second filtering module includes:

[0021] The second amplifier has its input terminal electrically connected to another output terminal of the first power divider module to perform power amplification processing on another second clock signal;

[0022] The second filter has its input terminal electrically connected to the output terminal of the second amplifier to filter the power-amplified second clock signal and output a fourth clock signal with another frequency component.

[0023] The clock signal generation circuit described above further includes:

[0024] The second power divider module has its input terminal electrically connected to the output terminal of the first filter module to divide the third clock signal into multiple fifth clock signals.

[0025] The third power divider module has its input terminal electrically connected to the output terminal of the second filter module to divide the fourth clock signal into multiple sixth clock signals.

[0026] The clock signal generation circuit described above further includes a crystal oscillator source for providing the reference signal.

[0027] The clock signal generation circuit described above further includes: a phase-locked loop (PLL) module, wherein the PLL module comprises:

[0028] A mixer, wherein the two input terminals of the mixer are respectively used to receive a frequency signal and a third clock signal, so as to generate a difference frequency signal based on the frequency difference between the frequency signal and the third clock signal;

[0029] A loop filter, the input of which is electrically connected to the output of the mixer, is used to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal.

[0030] A voltage-controlled oscillator, the input of which is electrically connected to the output of the loop filter, outputs the frequency signal and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.

[0031] A second aspect of this invention provides a quantum bit readout link, comprising:

[0032] Any of the clock signal generation circuits described above, wherein the frequency component of the third clock signal is higher than the frequency component of the fourth clock signal;

[0033] A signal transmitter is used to provide a read input signal for probing qubit information using the third clock signal as the read input sampling clock;

[0034] A signal acquisition unit is used to provide a readout output signal for acquiring quantum bit information, using the fourth clock signal as the readout output sampling clock.

[0035] In the quantum bit readout link described above, the first power divider module is further electrically connected to the first filter module via a first signal line; the first power divider module is electrically connected to the second filter module via a second signal line; the first filter module is electrically connected to the signal transmitter via a third signal line; and the second filter module is electrically connected to the signal collector via a fourth signal line.

[0036] The first signal line and the second signal line are of equal length; the third signal line and the fourth signal line are of equal length.

[0037] A third aspect of this invention provides a quantum computer, including any of the quantum bit readout links described above.

[0038] The beneficial effects of this utility model are as follows:

[0039] In the clock signal generation circuit of this application, the frequency multiplier module receives the reference signal and generates a first clock signal containing multiple frequency components. The first power divider module distributes the first clock signal into multiple second clock signals. The first filter module and the second filter module respectively filter one second clock signal and output a third clock signal with one frequency component and a fourth clock signal with another frequency component.

[0040] The third and fourth clock signals in this application can be used as the input sampling clock and the output sampling clock, respectively. Since the input sampling clock and the output sampling clock are generated based on the same reference signal and after being multiplied by the same frequency multiplication module, the phase difference stability of the input sampling clock and the output sampling clock is improved, thereby ensuring the accuracy of the quantum bit reading results.

[0041] The quantum bit readout link and quantum computer provided by this invention include the clock signal generation circuit described above, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description

[0042] Figure 1 A schematic diagram of the clock signal generation circuit provided in this embodiment of the utility model. Figure 1 ;

[0043] Figure 2 A schematic diagram of the clock signal generation circuit provided in this embodiment of the utility model. Figure 2 ;

[0044] Figure 3 A schematic diagram of the frequency multiplier module provided in Example 1 of this utility model. Figure 1 ;

[0045] Figure 4 A schematic diagram of the frequency multiplier module provided in Example 2 of this utility model. Figure 2 ;

[0046] Figure 5 A schematic diagram of the phase-locked loop module provided in this embodiment of the utility model. Figure 1 ;

[0047] Figure 6 A schematic diagram of the phase-locked loop module provided in this embodiment of the utility model. Figure 2 ;

[0048] 10. Frequency multiplier module; 20. First power divider module; 30. First filter module; 40. Second filter module; 50. Second power divider module; 60. Third power divider module; 70. Phase-locked loop module; 71. Mixer; 72. Loop filter; 73. Voltage-controlled oscillator; 74. Power divider unit; 301. First comb spectrum generator; 302. First filter unit; 303. Second filter unit; 304. Second comb spectrum generator; 401. First frequency multiplier; 402. Third filter unit; 403. Second frequency multiplier; 404. Fourth filter unit; 405. Third comb spectrum generator. Detailed Implementation

[0049] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0050] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] During the reading of qubits, two critical clock signals need to be applied: one is the read input sampling clock, which controls the transmission of the read signal, and the other is the read output sampling clock, which controls the reception of the signal. Typically, the read input sampling clock and the read output sampling clock have different frequencies; for example, the read input sampling clock has a frequency of 6 GHz, and the read output sampling clock has a frequency of 3 GHz. Because of this frequency difference, existing solutions usually use different circuits to generate these two signals. This results in poor phase difference stability between the read input and read output sampling clocks, reducing the accuracy of the read results and consequently affecting the overall performance and reliability of quantum computing.

[0053] To solve the above problems, Figure 1 A schematic diagram of the clock signal generation circuit provided in this embodiment of the utility model. Figure 1 ;like Figure 1 As shown: This application discloses a clock signal generation circuit, including:

[0054] The frequency multiplier module 10 is used to multiply the frequency of the reference signal to generate a first clock signal containing multiple frequency components.

[0055] The first power divider module 20 has its input terminal electrically connected to the output terminal of the frequency multiplier module 10, so as to divide the first clock signal into multiple second clock signals.

[0056] The first filtering module 30 has its input terminal electrically connected to one output terminal of the first power divider module 20 to filter a second clock signal and output a third clock signal with one frequency component.

[0057] The second filtering module 40 has its input terminal electrically connected to another output terminal of the first power divider module 20 to filter another second clock signal and output a fourth clock signal with another frequency component.

[0058] In the clock signal generation circuit of this embodiment, the frequency multiplier module 10 receives the reference signal and generates a first clock signal containing multiple frequency components. The first power divider module 20 distributes the first clock signal into multiple second clock signals. The first filter module 30 and the second filter module 40 respectively filter one second clock signal and output a third clock signal with one frequency component and a fourth clock signal with another frequency component.

[0059] In this embodiment, the third and fourth clock signals can be used as the input sampling clock and the output sampling clock, respectively. Since the input sampling clock and the output sampling clock are generated based on the same reference signal and after being multiplied 10 times by the same frequency multiplication module, the phase difference stability of the input sampling clock and the output sampling clock is improved, thereby ensuring the accuracy of the quantum bit reading results.

[0060] In this embodiment, the reference signal is typically a 100MHz clock signal. In some implementations of this embodiment, the clock signal generation circuit further includes a crystal oscillator source for providing the reference signal. In this embodiment, a crystal oscillator source is selected to provide the reference signal. The crystal oscillator source has the characteristics of high stability and low phase noise, so that the final clock signal has the characteristics of high stability and low phase noise.

[0061] In this embodiment, the first power dividing module 20 can be a power divider. To ensure the signal quality after power division, the first power dividing module 20 may further include an amplifier electrically connected to the front end and / or back end of the power divider. For example, the first power dividing module 20 is a two-way power divider.

[0062] The circuit composition of the frequency multiplier module 10 in this embodiment is not specifically limited. In some embodiments of this embodiment, the frequency multiplier module 10 includes: multiple comb spectrum generators connected in series, which sequentially perform frequency multiplication processing on the received signal to output signals with multiple frequency components, such that the last comb spectrum generator generates a first clock signal containing multiple frequency components; at least one filter unit is electrically connected between any two adjacent comb spectrum generators, and the filter unit is used to filter the received signal.

[0063] In this embodiment, the frequency multiplication module 10 uses a multi-stage comb spectrum generator cascaded to achieve a "step-by-step frequency multiplication-filtering" link from 100MHz to 3GHz / 6GHz. After each low-order frequency multiplication, filtering effectively removes unwanted frequency components and adjacent-order spurious signals, resulting in significantly better overall phase noise compared to a single ×30 / 60 high-order frequency multiplication. Simultaneously, the third and fourth clock signals are generated at lower multiplication ratios in their respective sub-links, reducing phase jitter and thus decreasing the phase difference between these two signals, improving readout accuracy.

[0064] In this embodiment, the number of comb spectrum generators is not specifically limited; the number of comb spectrum generators can be 2, 3, or other quantities.

[0065] In this embodiment, the number of filter units electrically connected between any two adjacent comb spectrum generators is not specifically limited and can be 1, 2 or other numbers.

[0066] In this embodiment, the filtering unit can be a filter, or an amplifier and a filter. By setting the amplifier, the power of the signal can be guaranteed to improve the signal quality.

[0067] In other embodiments of this example, the frequency multiplier module 10 includes a frequency multiplier and a comb spectrum generator; wherein the frequency multiplier is used to perform frequency multiplication processing on the reference signal to output a signal with a fixed frequency; the input terminal of the comb spectrum generator is electrically connected to the output terminal of the frequency multiplier, and is used to perform frequency multiplication processing on the signal with a fixed frequency to output a first clock signal containing multiple frequency components.

[0068] In this embodiment, the frequency multiplier module 10 cascades a frequency multiplier and a comb spectrum generator to achieve a "step-by-step low-multiplication" link from 100MHz to 3GHz / 6GHz. This not only significantly improves the overall phase noise compared to a single ×30 / 60 higher-order multiplication, but also allows the third and fourth clock signals to be generated at lower multiplication ratios in their respective sub-links, reducing phase jitter and thus improving the stability of the phase difference between these two signals and enhancing readout accuracy.

[0069] In this embodiment, the frequency multiplier module 10 may further include a filtering unit electrically connected between the frequency multiplier and the comb spectrum generator. The filtering unit may be a filter, or it may be an amplifier and a filter. By setting the amplifier, the power of the signal can be guaranteed to improve the signal quality.

[0070] In this embodiment, the number of frequency multipliers is not specifically limited and can be one, two, or other numbers. When the frequency multiplier module 10 includes multiple frequency multipliers, a filter unit can be electrically connected between two adjacent frequency multipliers. The filter unit can be a filter, or an amplifier and a filter. By setting an amplifier, the signal power can be guaranteed to improve the signal quality.

[0071] Two specific examples of frequency multiplier module 10 are given below:

[0072] Example 1: Figure 3 A schematic diagram of the frequency multiplier module provided in this embodiment of the utility model. Figure 1 ;like Figure 3 As shown: The frequency multiplication module 10 includes: a first comb spectrum generator 301, a first filter unit 302, a second filter unit 303, and a second comb spectrum generator 304 connected in series; wherein, the first comb spectrum generator 301 and the second comb spectrum generator 304 sequentially perform frequency multiplication processing on the received signal to output a signal with multiple frequency components, so that the second comb spectrum generator 304 generates a first clock signal containing multiple frequency components; the first filter unit 302 and the second filter unit 303 both include an amplifier and a filter connected in series, and sequentially amplify and filter the received signal.

[0073] In this example, the process of generating the first clock signal is as follows:

[0074] First, the 100MHz reference signal is frequency-multiplied by the first comb generator 301, outputting signals with frequency components of 0.1GHz, 0.2GHz, 0.3GHz, 0.4GHz, 0.5GHz, 0.6GHz, 0.7GHz, 0.8GHz, 0.9GHz, 1.0GHz, 1.1GHz, 1.2GHz, 1.3GHz, 1.4GHz, and 1.5GHz. Second, after amplification and filtering by the first filter unit 302 and the second filter unit 303, a signal with a frequency of 1.5GHz is obtained. Finally, after passing through the second comb generator 304, a first clock signal with frequency components of 1.5GHz, 3GHz, 4.5GHz, and 6GHz is output.

[0075] Example 2: Figure 4 A schematic diagram of the frequency multiplier module provided in this embodiment of the utility model. Figure 2 ;like Figure 4 As shown: The frequency multiplier module 10 includes: a first frequency multiplier 401, a third filter unit 402, a second frequency multiplier 403, a fourth filter unit 404, and a third comb spectrum generator 405 connected in series; wherein, the first frequency multiplier 401 and the second frequency multiplier 403 are used to multiply the received signal to output a signal of a fixed frequency; the third comb spectrum generator 405 is used to multiply the fixed frequency signal to output a first clock signal containing multiple frequency components; the third filter unit 402 and the fourth filter unit 404 each include an amplifier and a filter connected in series, which amplify and filter the received signal in sequence.

[0076] In this example, the process of generating the first clock signal is as follows:

[0077] First, the 100MHz reference signal is multiplied by the first frequency multiplier 401, outputting a signal with a frequency of 300MHz. Second, after being amplified and filtered by the third filter unit 402, it passes through the second frequency multiplier 403, outputting a signal with a frequency of 1.5GHz. Finally, after being amplified and filtered by the fourth filter unit 404, it passes through the third comb spectrum generator 405, outputting a first clock signal with frequency components of 1.5GHz, 3GHz, 4.5GHz, and 6GHz.

[0078] The multiple frequency multiplication processes mentioned above can reduce the multiplication ratio and improve the phase difference stability between the final third and fourth clock signals. The following is a detailed explanation based on Examples 1 and 2:

[0079] Example 1 and Example 2 output a first clock signal with frequency components of 1.5GHz, 3GHz, 4.5GHz, and 6GHz. After being divided by the first power divider module 20, one path passes through the first filter module 30 to obtain a third clock signal with a frequency component of 6GHz, and the other path passes through the second filter module 40 to obtain a fourth clock signal with a frequency component of 3GHz. Here, the multiplication factor of the third clock signal is 4 (6GHz divided by 1.5GHz), and the multiplication factor of the fourth clock signal is 2 (3GHz divided by 1.5GHz). If directly obtained by multiplying by 100MHz, then the multiplication factor of the third clock signal is 60 (6GHz divided by 100MHz), and the multiplication factor of the fourth clock signal is 30 (3GHz divided by 100MHz). It can be seen that the scheme in this example greatly reduces the multiplication factor, reduces the phase jitter of the third and fourth clock signals, thereby improving the stability of the phase difference between the two signals and improving the reading accuracy.

[0080] In order to ensure the signal quality after frequency multiplication, in some embodiments of this example, an amplifier is connected in series at the front end of the frequency multiplication module 10 to boost the input signal power in advance, so as to ensure that the signal after frequency multiplication still has a high signal-to-noise ratio.

[0081] In this example, the first filtering module 30 can be composed of a filter alone, or it can be composed of an amplifier and a filter. In some embodiments of this example, the first filtering module 30 includes: a first amplifier, whose input terminal is electrically connected to one output terminal of the first power divider module 20, to perform power amplification processing on a second clock signal; and a first filter, whose input terminal is electrically connected to the output terminal of the first amplifier, to perform filtering processing on the power amplified second clock signal and output a third clock signal with one frequency component.

[0082] In this embodiment, the first amplifier in the first filtering module 30 ensures the signal amplitude, and the first filter ensures the spectral purity by filtering out spurious and unwanted frequency components. Together, they enable the subsequent link to obtain a high-quality clock.

[0083] In this example, the second filtering module 40 can be composed of a filter alone, or it can be composed of an amplifier and a filter. In some embodiments of this example, the second filtering module 40 includes: a second amplifier, whose input terminal is electrically connected to another output terminal of the first power divider module 20, to perform power amplification processing on another second clock signal; and a second filter, whose input terminal is electrically connected to the output terminal of the second amplifier, to perform filtering processing on the power-amplified second clock signal and output a fourth clock signal with another frequency component.

[0084] In this embodiment, the second amplifier in the second filtering module 40 ensures the signal amplitude, and the second filter ensures the spectral purity by filtering out spurious and unwanted frequency components. Together, they enable the subsequent link to obtain a high-quality clock.

[0085] As the number of qubits integrated in a quantum chip increases, the number of read input sampling clocks and read output sampling clocks required also increases. To ensure the phase difference stability of all read input sampling clocks and read output sampling clocks of the same quantum chip, this application discloses a clock signal generation circuit, such as... Figure 2 As shown, Figure 2 A schematic diagram of the clock signal generation circuit provided in this embodiment of the utility model. Figure 2 Based on the clock signal generation circuit in Embodiment 1, it further includes:

[0086] The second power divider module 50 has its input terminal electrically connected to the output terminal of the first filter module 30 to divide the third clock signal into multiple fifth clock signals.

[0087] The third power divider module 60 has its input terminal electrically connected to the output terminal of the second filter module 40 to divide the fourth clock signal into multiple sixth clock signals.

[0088] The second power divider module 50 can generate multiple fifth clock signals as the input sampling clock for reading, and the third power divider module 60 can generate multiple sixth clock signals as the output sampling clock for reading. Furthermore, since the multiple fifth clock signals and multiple sixth clock signals are all based on the same reference signal and generated by the same frequency multiplication module after being multiplied by 10, the stability of the phase difference is guaranteed, thereby ensuring the accuracy of the quantum bit reading results.

[0089] The second power divider module 50 in this embodiment can be a single power divider or multiple power dividers cascaded together. In order to ensure the signal quality after power division, the second power divider module 50 may also include an amplifier electrically connected to the front end and / or back end of the power divider.

[0090] The third power divider module 60 in this embodiment can be a single power divider or multiple power dividers cascaded together. In order to ensure the signal quality after power division, the third power divider module 60 may also include an amplifier electrically connected to the front end and / or back end of the power divider.

[0091] To further improve the quality of the third clock signal, in some implementations of this embodiment, such as... Figure 5 As shown, Figure 5 A schematic diagram of the phase-locked loop module provided in this embodiment of the utility model. Figure 1 The clock signal generation circuit also includes: a phase-locked loop module 70, which includes:

[0092] Mixer 71 has two input terminals for receiving a frequency signal and a third clock signal, respectively, to generate a difference frequency signal based on the frequency difference between the frequency signal and the third clock signal.

[0093] The input terminal of the loop filter 72 is electrically connected to the output terminal of the mixer 71 to perform low-pass filtering on the difference frequency signal and generate the first voltage-controlled signal.

[0094] The voltage-controlled oscillator 73 has its input terminal electrically connected to the output terminal of the loop filter 72 to output a frequency signal, and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.

[0095] The working principle of the phase-locked loop module 70 in this embodiment is as follows: The mixer 71 accurately compares the frequency signal output by the voltage-controlled oscillator 73 with the frequency-multiplied clock signal after frequency multiplication, generating a difference frequency signal representing the frequency difference between the two. The loop filter 72 performs low-pass filtering on the difference frequency signal to generate a first voltage-controlled signal. The voltage-controlled oscillator 73 adjusts the frequency of its output frequency signal according to the first voltage-controlled signal until the frequency of the frequency signal is locked to the target frequency.

[0096] In the phase-locked loop module 70 of this embodiment, the loop filter 72, through its low-pass filtering function, combines with the dynamic frequency adjustment function of the voltage-controlled oscillator 73 to work together to improve the far-end and near-end phase noise of the frequency-multiplied clock signal. Furthermore, this circuit employs a mixer 71, effectively avoiding the problem in traditional phase-locked loop modules 70 where a high-frequency divider is required due to the low frequency of the phase detector. This significantly reduces the near-end phase noise introduced into the feedback link and effectively improves near-end phase noise performance.

[0097] In summary, the phase-locked loop module 70 of this embodiment improves the near-end and far-end phase noise performance of the third clock signal, increases the phase noise level of the third clock signal to improve the quality of the third clock signal, and can improve the accuracy of the reading results when used as a reading input sampling clock.

[0098] In this embodiment, the target frequency is the frequency of the third clock signal.

[0099] In this embodiment, the loop filter 72 can be either active or passive. In some embodiments of this embodiment, the loop filter 72 is active. Compared to a passive loop filter, the active loop filter 72 can provide higher gain and wider loop bandwidth, thereby achieving faster lock-in time and better dynamic response. To further reduce phase noise, the phase-locked loop module 70 also includes an LDO (low dropout linear regulator) to power the loop filter 72. Using an LDO regulator to power the loop filter 72 can provide a stable, low-noise power supply, thereby helping to reduce the phase noise of the phase-locked loop module 70.

[0100] In this embodiment, the type of voltage-controlled oscillator 73 is not specifically limited. In order to further reduce phase noise, in some implementations of this embodiment, the voltage-controlled oscillator 73 adopts a sapphire dielectric oscillator.

[0101] In this embodiment, the initial voltage control signal of the voltage-controlled oscillator 73 can be provided by the voltage-controlled oscillator 73 itself or by an external circuit. To accelerate the locking process of the phase-locked loop module 70 and improve its stability and dynamic performance, in some implementations of this embodiment, the phase-locked loop module 70 further includes a capture circuit for providing a second voltage control signal. This second voltage control signal serves as the initial voltage control signal, enabling the voltage-controlled oscillator 73 to output a frequency signal. The capture circuit provides the initial voltage control signal when the phase-locked loop module 70 starts up, prompting the frequency signal output by the voltage-controlled oscillator 73 to quickly approach the target frequency.

[0102] In this embodiment, the specific type of the capture circuit is not limited. For example, it can be a Wien bridge oscillator circuit, a triangular wave generation circuit, or other circuits. In some implementations of this embodiment, the capture circuit is a triangular wave generation circuit. Compared with other capture circuits, the triangular wave generation circuit has advantages such as fast frequency sweep, high controllability, low noise level, and simple circuit.

[0103] In some implementations of this embodiment, such as Figure 6 As shown, Figure 6 A schematic diagram of the phase-locked loop module provided in this embodiment of the utility model. Figure 2 ;exist Figure 5 Based on the phase-locked loop module 70, the phase-locked loop module 70 also includes: a power divider unit 74, the input terminal of the power divider unit 74 is electrically connected to the output terminal of the voltage-controlled oscillator 73, and one of the multiple output terminals of the power divider unit 74 is electrically connected to one input terminal of the mixer 71, so as to divide the frequency signal into multiple paths and output them at multiple output terminals respectively.

[0104] In this embodiment, the frequency signal output from the voltage-controlled oscillator 73 is divided into multiple paths by the power divider unit 74, allowing the signal to be used at multiple output terminals. This not only allows the same frequency signal to be used for different circuit requirements but also helps reduce interference between different circuit parts, improving the overall stability and signal quality of the circuit. In this embodiment, the design of the power divider unit 74 allows it to have at least two output terminals, but the number is not specifically limited and can be two, three, or more. The power-divided frequency signals are allocated to different uses: one signal is used as a feedback signal and output to the mixer 71 to maintain the stable operation of the phase-locked loop; the remaining signals can be output to the quantum bit readout link as the readout input sampling clock for that link, or output to other circuits that require such signals.

[0105] In this embodiment, the power dividing unit 74 can be a power divider. To ensure the signal quality after power division, the power dividing unit 74 may also include an amplifier electrically connected to the front end and / or back end of the power divider. For example, the power dividing unit 74 is a two-way power divider.

[0106] To further improve the quality of the fourth clock signal, in some embodiments of this example, a phase-locked loop module 70 as described in the above embodiment can be added to the clock signal generation circuit to process the fourth clock signal, optimize its phase noise, and improve its quality.

[0107] Based on the same concept, this application also proposes a quantum bit readout link, including:

[0108] The clock signal generation circuit of any of the above embodiments, wherein the frequency component of the third clock signal is higher than the frequency component of the fourth clock signal.

[0109] A signal transmitter is used to provide a read input signal for probing qubit information, with a third clock signal serving as the read input sampling clock.

[0110] The signal acquisition unit is used to provide the readout output signal for the acquired qubit information, with the fourth clock signal as the readout output sampling clock.

[0111] In this embodiment, the quantum bit readout link uses the third and fourth clock signals output by the clock signal generation circuit of the above embodiment as the readout input sampling clock and the readout output sampling clock, respectively. Since these two clocks are generated based on the same reference signal and after being multiplied 10 by the same frequency multiplication module, the phase difference stability of the readout input sampling clock and the readout output sampling clock is improved, thereby ensuring the accuracy of the readout results of the quantum bit readout link.

[0112] To further improve the phase difference stability of the third and fourth clock signals, in some embodiments of this example, the first power divider module 20 is electrically connected to the first filter module 30 via a first signal line; the first power divider module 20 is electrically connected to the second filter module 40 via a second signal line; the first filter module 30 is electrically connected to the signal transmitter via a third signal line; and the second filter module 40 is electrically connected to the signal acquisition unit via a fourth signal line. The first and second signal lines are of equal length; the third and fourth signal lines are of equal length. This equal-length setting in this embodiment can reduce phase jitter of the third and fourth clock signals during transmission, thereby ensuring good stability of the phase difference between the third and fourth clock signals.

[0113] Based on the same concept, embodiments of this application also propose a quantum computer, including the aforementioned qubit readout link.

[0114] The quantum computer of this application includes the aforementioned quantum bit readout link. Since the aforementioned quantum bit readout link includes the aforementioned clock signal generation circuit, the quantum computer of this application has the same beneficial effects as the aforementioned clock signal generation circuit, which will not be described in detail here.

[0115] In this specification, references to terms such as "some embodiments" or "examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0116] The above are merely preferred embodiments of this utility model and do not constitute any limitation on this utility model. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and contents disclosed in this utility model without departing from the scope of the technical solutions of this utility model shall still fall within the protection scope of this utility model.

Claims

1. A clock signal generation circuit, characterized in that, include: The frequency multiplier module is used to multiply the frequency of the reference signal to generate a first clock signal containing multiple frequency components. The first power divider module has its input terminal electrically connected to the output terminal of the frequency multiplier module to divide the first clock signal into multiple second clock signals. The first filtering module has its input terminal electrically connected to one output terminal of the first power divider module to filter a second clock signal and output a third clock signal with one frequency component. The second filtering module has its input terminal electrically connected to another output terminal of the first power divider module to filter another second clock signal and output a fourth clock signal with another frequency component.

2. The clock signal generation circuit according to claim 1, characterized in that, The frequency multiplier module includes: Multiple comb spectrum generators connected in series, wherein the multiple comb spectrum generators sequentially perform frequency multiplication on the received signal to output a signal with multiple frequency components, such that the last comb spectrum generator generates a first clock signal containing multiple frequency components. At least one filter unit is electrically connected between any two adjacent comb spectrum generators, and the filter unit is used to filter the received signal.

3. The clock signal generation circuit according to claim 1, characterized in that, The frequency doubling module includes: a frequency multiplier and a comb spectrum generator; The frequency multiplier is used to multiply the reference signal to output a signal with a fixed frequency; the input terminal of the comb spectrum generator is electrically connected to the output terminal of the frequency multiplier, and is used to multiply the fixed frequency signal to output a first clock signal containing multiple frequency components.

4. The clock signal generation circuit according to claim 1, characterized in that, The first filtering module includes: The first amplifier has its input terminal electrically connected to one output terminal of the first power divider module to perform power amplification processing on one of the second clock signals; The first filter has its input terminal electrically connected to the output terminal of the first amplifier to filter the second clock signal after power amplification and output a third clock signal with one frequency component. The second filtering module includes: The second amplifier has its input terminal electrically connected to another output terminal of the first power divider module to perform power amplification processing on another second clock signal; The second filter has its input terminal electrically connected to the output terminal of the second amplifier to filter the power-amplified second clock signal and output a fourth clock signal with another frequency component.

5. The clock signal generation circuit according to claim 1, characterized in that, Also includes: The second power divider module has its input terminal electrically connected to the output terminal of the first filter module to divide the third clock signal into multiple fifth clock signals. The third power divider module has its input terminal electrically connected to the output terminal of the second filter module to divide the fourth clock signal into multiple sixth clock signals.

6. The clock signal generation circuit according to claim 1, characterized in that, Also includes: A crystal oscillator source is used to provide the reference signal.

7. The clock signal generation circuit according to claim 1, characterized in that, Also includes: Phase-locked loop (PLL) module, the PLL module comprising: A mixer, wherein the two input terminals of the mixer are respectively used to receive a frequency signal and the third clock signal, so as to generate a difference frequency signal based on the frequency difference between the frequency signal and the third clock signal; A loop filter, the input of which is electrically connected to the output of the mixer, is used to perform low-pass filtering on the difference frequency signal and generate a first voltage-controlled signal. A voltage-controlled oscillator, the input of which is electrically connected to the output of the loop filter, outputs the frequency signal and adjusts the frequency of the frequency signal according to the first voltage control signal until it is locked to the target frequency.

8. A quantum bit readout link, characterized in that, include: The clock signal generation circuit as described in any one of claims 1-7, wherein the frequency component of the third clock signal is higher than the frequency component of the fourth clock signal; A signal transmitter is used to provide a read input signal for probing qubit information using the third clock signal as the read input sampling clock; A signal acquisition unit is used to provide a readout output signal for acquiring quantum bit information, using the fourth clock signal as the readout output sampling clock.

9. The quantum bit readout link according to claim 8, characterized in that, The first power divider module is electrically connected to the first filter module via a first signal line; the first power divider module is electrically connected to the second filter module via a second signal line; the first filter module is electrically connected to the signal transmitter via a third signal line. The second filtering module is electrically connected to the signal acquisition unit via the fourth signal line; The first signal line and the second signal line are of equal length; the third signal line and the fourth signal line are of equal length.

10. A quantum computer, characterized in that, This includes the quantum bit readout link as described in claim 8 or 9.

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