Gate drive circuit with refresh rate modulation

Abstract

The utility model discloses a grid drive circuit with refresh rate modulation, which is coupled with a shielding signal by a pull-down circuit and between a charge-discharge circuit and an output circuit, and a first noise suppression circuit and a second noise suppression circuit are respectively provided with a first control circuit and a second control circuit, and are respectively coupled with the shielding signal. When the shielding signal is enabled, the pull-down circuit controls a first control node between the charge-discharge circuit and the output circuit to be pulled down to a corresponding reference potential according to the shielding signal, and the shielding signal drives a first bias node of the first noise suppression circuit to maintain at the potential of a first input signal, and drives a second bias node of the second noise suppression circuit to maintain at the potential of a second input signal, so as to modulate the refresh rate.

Description

Technical Field

[0001] This utility model relates to a driving circuit, and more particularly to a gate driving circuit with refresh rate modulation. Background Technology

[0002] With the emergence of the concept of System-on-Glass (SOG), many products now integrate the gate driver or scan driver circuitry from the display driver circuitry onto the glass, known as GOA (Gate-Driver-on-Array) circuitry. GOA circuitry offers numerous advantages. Besides reducing the bezel area for a thinner bezel, it also reduces the number of gate driver ICs used, lowering IC purchase costs and avoiding wire breakage issues during glass-IC bonding, thus improving product yield. It is currently widely used in small and medium-sized displays such as mobile phones and laptops, and even large displays utilizing GOA circuitry have emerged in recent years.

[0003] Please see Figure 1 This is a schematic diagram of a prior art gate drive circuit. As shown in the figure, the prior art gate drive circuit 1 for GOA includes a charging and discharging circuit 10, an output circuit 20, and a noise suppression circuit 40. The charging and discharging circuit 10 generates a first control potential A[N] through a first transistor M1 and a second transistor M2 based on a first control signal G[N-4], a second control signal G[N+4], a first drive voltage VDDF, and a second drive voltage VDDR, so as to provide the output circuit 20 with a third transistor and a capacitor C to generate an output signal G[N] at an output terminal OUT based on the first control potential A[N] and a clock signal CLK. In this way, a power supply potential VGH is coupled to a fourth transistor M4 and a fifth transistor M5 of the noise suppression circuit 40, and a reference potential VSS and the first control potential A[N] are coupled to a sixth transistor M6 and a seventh transistor M7 of the noise suppression circuit 40, so as to provide a first bias voltage B[N], which drives an eighth transistor M8 and a ninth transistor M9 to control the potential of the first control potential A[N] and the output signal G[N] to suppress noise.

[0004] However, the prior art gate drive circuit 1 still maintains a high refresh rate display in static images, resulting in wasted power consumption. Moreover, the single-stage gate drive circuit only has a noise suppression circuit 40, which operates for a long time to suppress the gate drive circuit 1 from erroneously outputting the output signal G[N] due to noise. For thin-film transistors, the longer the operating time, the more severe the degradation. Furthermore, the extended operating time of thin-film transistors will cause the threshold voltage to increase over time. For example, after applying voltage to the gate of a thin-film transistor for more than 10 hours, the threshold voltage will rise to at least 4V.

[0005] To address the aforementioned problems, this invention provides a gate drive circuit with refresh rate modulation. It couples a masking signal via a pull-down circuit and simultaneously couples the masking signal via a first control circuit of a first noise suppression circuit and a second control circuit of a second noise suppression circuit. When the masking signal is enabled, the pull-down circuit pulls down a first control potential between a charging / discharging circuit and an output circuit to a corresponding reference potential. Simultaneously, the first and second control circuits maintain a first bias potential and a second bias potential of the first and second noise suppression circuits at corresponding first and second input signals, respectively. This prevents the output circuit from generating an output signal, allowing the display panel coupled to the gate drive circuit to achieve screen refresh rate modulation in at least one corresponding frame, thereby reducing power consumption. Furthermore, the alternating use of the first and second noise suppression circuits to suppress noise reduces transistor degradation. Utility Model Content

[0006] One objective of this invention is to provide a gate drive circuit with refresh rate modulation. When the masking signal is enabled, the pull-down circuit pulls down a first control potential between a charging / discharging circuit and an output circuit to a corresponding reference potential. Simultaneously, the first and second control circuits maintain a first bias potential and a second bias potential of the first and second noise suppression circuits at the corresponding first and second input signals, thereby preventing the output circuit from generating an output signal. In this way, the display panel coupled to the gate drive circuit achieves the effect of screen refresh rate modulation in at least one corresponding frame, thereby reducing power consumption.

[0007] Another objective of this invention is to provide a gate drive circuit with refresh rate modulation, which maintains a first bias potential and a second bias potential of the first and second noise suppression circuits at corresponding first and second input signals, thereby using the first and second noise suppression circuits alternately to suppress noise and reduce transistor degradation.

[0008] To achieve the above objectives, this utility model discloses a gate drive circuit with refresh rate modulation, which receives a clock signal, a first input signal, a second input signal, a first power supply voltage, and a second power supply voltage from an external circuit. The gate drive circuit with refresh rate modulation includes a charging / discharging circuit, an output circuit, a pull-down circuit, a first noise suppression circuit, and a second noise suppression circuit. The charging / discharging circuit is coupled to a first control signal, a second control signal, a first driving voltage, and a second driving voltage, and the charging / discharging circuit... A first control potential is generated at a first control node based on the first control signal, the second control signal, the first driving voltage, and the second driving voltage. The output circuit is coupled to the clock signal, the first control node, and an output terminal. The output circuit generates an output signal corresponding to the first control potential to an output terminal based on the clock signal. A pull-down circuit is coupled between the charging / discharging circuit and the output circuit, and is also coupled to a shielding signal and a reference potential. A first noise suppression circuit is coupled to the first control node and the output terminal, and is also coupled to a first input... The first noise suppression circuit generates a first bias voltage based on the first input signal and the reference potential to control the first control potential and the output signal potential. The first noise suppression circuit further includes a first control circuit coupled to the shielding signal and the first input signal. The second noise suppression circuit is coupled to the first control node and the output terminal, and is also coupled to a second input signal and the reference potential. The second noise suppression circuit generates a second bias voltage based on the second input signal to control the first control node and the reference potential. The second noise suppression circuit further includes a second control circuit coupled to the shielding signal and the second input signal. When the shielding signal is enabled, the pull-down circuit controls the first control node to be pulled down to the corresponding reference potential based on the shielding signal. The first control circuit controls the first bias potential to be maintained at the potential of the first input signal based on the shielding signal, and the second control circuit controls the second bias potential to be maintained at the potential of the second input signal based on the shielding signal, thereby preventing the output circuit from generating an output signal. In this way, the present invention enables a display panel coupled to the gate drive circuit to achieve screen refresh rate modulation in at least one corresponding frame, thereby reducing power consumption. Furthermore, the alternating use of the first and second noise suppression circuits to suppress noise reduces transistor degradation.

[0009] This utility model provides an embodiment in which the gate drive circuit with refresh rate modulation further includes a bridge circuit coupled to the first control node and a second control node. The second control node is coupled between the bridge circuit and the charging / discharging circuit, and the first control node is coupled between the bridge circuit and the output circuit. The bridge circuit enables the first control potential to be conducted from the first control node to the second control node to form a second control potential. The output circuit generates the output signal based on the clock signal and the second control potential.

[0010] This utility model provides an embodiment in which the bridge circuit includes a bridge transistor, a first terminal of which is coupled to a second terminal of which is coupled to the first control node, and a third terminal of which is coupled to the second control node, so that the first control potential is conducted from the first control node to the second control node to form the second control potential.

[0011] This utility model provides an embodiment in which the pull-down circuit is further coupled between the bridge circuit and the charging / discharging circuit.

[0012] This utility model provides an embodiment in which the pull-down circuit is further coupled between the bridge circuit and the output circuit.

[0013] This utility model provides an embodiment in which the charging and discharging circuit includes a first transistor and a second transistor. A first terminal of the first transistor is coupled to the first control signal, a second terminal of the first transistor is coupled to the first driving voltage, and a first terminal of the second transistor is coupled to the second control signal and a second terminal of the second transistor is coupled to the second driving voltage. A third terminal of the second transistor and a third terminal of the first transistor are coupled to the pull-down circuit and the output circuit. When the first control signal drives the first transistor to conduct, the first control potential of the first control node corresponds to the first driving voltage. When the second control signal drives the second transistor to conduct, the first control potential of the first control node corresponds to the second driving voltage.

[0014] This utility model provides an embodiment in which the output circuit includes a third transistor, a first terminal of which is coupled to the first control node, a second terminal of which is coupled to the clock signal, and a third terminal of which is coupled to the output terminal.

[0015] This utility model provides an embodiment in which the pull-down circuit includes a first shielding transistor, a first terminal of which is coupled to the shielding signal, a second terminal of which is coupled between the charging / discharging circuit and the output circuit, and a third terminal of which is coupled to the reference potential.

[0016] This utility model provides an embodiment in which the first noise suppression circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, an eighth transistor, and a ninth transistor. A first terminal and a second terminal of the fourth transistor are coupled to the first input signal. A first terminal of the fifth transistor is coupled to the second input signal. A second terminal of the fifth transistor and a third terminal of the fourth transistor are coupled to the first control circuit. A first terminal of the sixth transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal of the sixth transistor is coupled to the first bias potential. A third terminal of the sixth transistor is coupled to the reference potential. A first terminal of the eighth transistor is coupled to the first bias potential. A second terminal of the eighth transistor is coupled between the charging / discharging circuit and the output circuit. A third terminal of the eighth transistor is coupled to the reference potential. A first terminal of the ninth transistor is coupled to the first bias potential. A second terminal of the ninth transistor is coupled to the output terminal. A third terminal of the ninth transistor is coupled to the reference potential.

[0017] This utility model provides an embodiment in which the first noise suppression circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. A first terminal and a second terminal of the fourth transistor are coupled to the first input signal. A first terminal of the fifth transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal of the fifth transistor and a third terminal of the fourth transistor are coupled to the first control circuit. A first terminal of the sixth transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal of the sixth transistor is coupled to the first bias potential. The third terminal of the seventh transistor is coupled to the reference potential. The first terminal of the seventh transistor is coupled between the third terminal of the fourth transistor and the second terminal of the fifth transistor. The second terminal of the seventh transistor is coupled between the first and second terminals of the fourth transistor and is coupled to the first input signal. The third terminal of the seventh transistor is coupled to the first bias potential. The first terminal of the eighth transistor is coupled to the first bias potential. The second terminal of the eighth transistor is coupled between the charging / discharging circuit and the output circuit. The third terminal of the eighth transistor is coupled to the reference potential. The first terminal of the ninth transistor is coupled to the first bias potential. The second terminal of the ninth transistor is coupled to the output terminal. The third terminal of the ninth transistor is coupled to the reference potential.

[0018] This utility model provides an embodiment in which the first control circuit includes a second shielding transistor, a first terminal of which is coupled to the shielding signal, a second terminal of which is coupled to the first bias potential, and a third terminal of which is coupled to the first input signal.

[0019] This utility model provides an embodiment in which the second noise suppression circuit further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a fourteenth transistor, and a fifteenth transistor. A first terminal and a second terminal of the tenth transistor are coupled to the second input signal. A first terminal of the eleventh transistor is coupled to the first input signal. A second terminal and a third terminal of the eleventh transistor are coupled to the second control circuit. A first terminal of the twelfth transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal of the twelfth transistor is coupled to the second bias potential. A third terminal of the twelfth transistor is coupled to the reference potential. A first terminal of the fourteenth transistor is coupled to the second bias potential. A second terminal of the fourteenth transistor is coupled between the charging / discharging circuit and the output circuit. A third terminal of the fourteenth transistor is coupled to the reference potential. A first terminal of the fifteenth transistor is coupled to the second bias potential. A second terminal of the fifteenth transistor is coupled to the output terminal. A third terminal of the fifteenth transistor is coupled to the reference potential.

[0020] This utility model provides an embodiment in which the second noise suppression circuit further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. A first terminal and a second terminal of the tenth transistor are coupled to the second input signal. A first terminal of the eleventh transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal and a third terminal of the eleventh transistor are coupled to the second control circuit. A first terminal of the twelfth transistor is coupled between the charging / discharging circuit and the output circuit. A first terminal of the twelfth transistor is coupled between the charging / discharging circuit and the output circuit. A second terminal of the twelfth transistor is coupled to the second bias potential. A third terminal of the thirteenth transistor is coupled to the reference potential. A first terminal of the thirteenth transistor is coupled between the third terminal of the tenth transistor and the second terminal of the eleventh transistor. A second terminal of the thirteenth transistor is coupled between the first and second terminals of the tenth transistor and is coupled to the second input signal. A third terminal of the thirteenth transistor is coupled to the second bias potential. A first terminal of the fourteenth transistor is coupled to the second bias potential. A second terminal of the fourteenth transistor is coupled between the charging / discharging circuit and the output circuit. A third terminal of the fourteenth transistor is coupled to the reference potential. A first terminal of the fifteenth transistor is coupled to the second bias potential. A second terminal of the fifteenth transistor is coupled to the output terminal. A third terminal of the fifteenth transistor is coupled to the reference potential.

[0021] This utility model provides an embodiment in which the second control circuit includes a second shielding transistor, a first terminal of which is coupled to the shielding signal, a second terminal of which is coupled to the first bias potential, and a third terminal of which is coupled to the second input signal. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a prior art gate drive circuit; Figure 2 This is a schematic diagram of a single-stage gate drive circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a multi-stage gate drive circuit according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a driving circuit according to an embodiment of the present invention; Figure 5A This is a schematic diagram of a single-stage gate drive circuit forward scanning according to an embodiment of the present invention. Figure 5B This is a schematic diagram of the signal of the first control electrode scanning in a forward direction according to an embodiment of the present invention; Figure 5C This is a schematic diagram of a single-stage gate drive circuit forward scanning to enable a masking signal according to an embodiment of the present invention. Figure 5D This is a schematic diagram of the first control electrode in an embodiment of the present invention, which is enabled by a shielding signal and scans in the forward direction. Figure 6A This is a schematic diagram of a single-stage gate drive circuit in reverse scanning according to an embodiment of the present invention; and Figure 6B This is a schematic diagram of the signal of the first control electrode in reverse scanning according to an embodiment of the present invention; Figure 6C This is a schematic diagram of a single-stage gate drive circuit in reverse scanning enabled by a masking signal according to an embodiment of the present invention. Figure 6D This is a schematic diagram of the first control electrode in one embodiment of the present invention, which is enabled by a shielding signal and scanned in reverse. Figure 7A This is a schematic diagram of a signal that disables the masking signal according to an embodiment of the present invention; Figure 7B This is a schematic diagram of a shielding signal enabling according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the output signal of this utility model at 60Hz; Figure 9This is a schematic diagram of the output signal of this utility model at 30Hz; Figure 10 This is a schematic diagram of the output signal of this utility model at 20Hz; Figure 11A This is a schematic diagram of the display of the image of this utility model at 60Hz; Figure 11B This is a schematic diagram of the display of the image of this utility model at 30Hz; Figure 11C This is a schematic diagram of the display of the image of this utility model at 20Hz; Figure 12 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention; Figure 13 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention; Figure 14 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention; Figure 15A This is a schematic diagram of a single-stage gate drive circuit forward scanning according to another embodiment of the present invention. Figure 15B This is a schematic diagram of the first control electrode scanning in a forward direction, representing another embodiment of the present invention. Figure 15C This is a schematic diagram of a single-stage gate drive circuit forward scanning to enable the masking signal, according to another embodiment of the present invention. Figure 15D This is a schematic diagram of the first control electrode being enabled by the shielding signal and scanning in the forward direction, according to another embodiment of the present invention. Figure 16A This is a schematic diagram of a single-stage gate drive circuit in reverse scanning according to another embodiment of the present invention; and Figure 16B This is a schematic diagram of the signal of the first control electrode in reverse scanning according to another embodiment of the present invention; Figure 16C This is a schematic diagram of a single-stage gate drive circuit in reverse scanning enabled by a masking signal, according to another embodiment of the present invention. Figure 16D This is a schematic diagram of the first control electrode in another embodiment of the present invention, which is enabled by a shielding signal and scanned in reverse. Figure 17A This is a schematic diagram of a signal that disables the masking signal according to another embodiment of the present invention; Figure 17B This is a schematic diagram of the signal enabling the masking signal according to another embodiment of the present invention; Figure 18 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention; Figure 19 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention; Figure 20A This is a schematic diagram of a single-stage gate drive circuit forward scanning according to another embodiment of the present invention. Figure 20B This is a schematic diagram of the first control electrode scanning in a forward direction, representing another embodiment of the present invention. Figure 20C This is a schematic diagram of a single-stage gate drive circuit forward scanning to enable the masking signal, according to another embodiment of the present invention. Figure 20D This is a schematic diagram of the first control electrode being enabled by the shielding signal and scanning in the forward direction, according to another embodiment of the present invention. Figure 21A This is a schematic diagram of a single-stage gate drive circuit in reverse scanning according to another embodiment of the present invention. Figure 21B This is a schematic diagram of the signal of the first control electrode in reverse scanning according to another embodiment of the present invention; Figure 21C This is a schematic diagram of a single-stage gate drive circuit in reverse scanning enabled by a masking signal, according to another embodiment of the present invention. Figure 21D This is a schematic diagram of the signal of the first control electrode enabled by the shielding signal and scanned in reverse according to another embodiment of the present invention; and Figure 22 This is a schematic diagram of the gate drive circuit of another embodiment of the present invention. [Figure Number Reference Guide] 1: Gate drive circuit 10: Charging and discharging circuit 12: Second control node 15: Bridge circuit 20: Output Circuit 22: First control node 30: Pull-down circuit 40: First noise suppression circuit 42: First bias node 44: First control circuit 50: Second noise suppression circuit 52: Second bias node 54: Second control circuit 100: Drive circuit 300: Control Circuit A[N]: First control potential A1: First control potential A5: First control potential B[N]: First bias voltage potential C[N]: Second bias voltage potential C: Capacitor CLK1: First clock signal CLK2: Second Clock Signal CLK3: Third Clock Signal CLK4: Fourth Clock Signal CLK5: Fifth Clock Signal CLK6: Sixth Clock Signal CLK7: Seventh Clock Signal CLK8: Eighth Clock Signal CLK[N]: Nth clock signal CLK: Clock signal ECK: First Input Signal EXCK: Second input signal Frame1: Display screen 1 Frame2: Display screen 2 Frame3: Display screen 3 Frame4: Display screen 4 Frame5: Display screen 5 Frame6: Display screen 6 G[N]: Output signal G1: Output signal G5: Output signal G[N-4]: First control signal G[N+4]: Second control signal M1: First transistor M2: Second transistor M3: Third transistor M4: Fourth transistor M5: Fifth Transistor M6: Sixth Transistor M7: Seventh Transistor M8: Eighth transistor M9: Ninth Transistor M1A: First transistor M2A: Second transistor M3A: Third transistor M4A: Fourth transistor M5A: Fifth Transistor M6A: Sixth Transistor M8A: Eighth Transistor M9A: Ninth Transistor M10A: Tenth Transistor M11A: Eleventh Transistor M12A: Twelfth Transistor M13A: Thirteenth Transistor M14A: Fourteenth Transistor M15A: The fifteenth transistor M1B: First Transistor M2B: Second Transistor M3B: Third transistor M4B: Fourth Transistor M5B: Fifth Transistor M6B: Sixth Transistor M7B: Seventh Transistor M8B: Eighth Transistor M9B: Ninth Transistor M10B: Tenth Transistor M11B: Eleventh Transistor M12B: Twelfth Transistor M13B: Thirteenth Transistor M14B: Fourteenth Transistor M15B: Fifteenth transistor; Mbr: Bridge transistor Mm0: First masking transistor Mm1: Second shielding transistor Mm2: Third shielding transistor MSK: Masking signal N1: Gate drive circuit; N1A: Nth stage gate drive circuit; N2A: N-4th stage gate drive circuit; N3A: N+4th stage gate drive circuit; N1B: Nth stage gate drive circuit; N1C: Nth stage gate drive circuit; N1D: Nth stage gate drive circuit; OUT: Output terminal. Start: Start signal T: Time Tr: Rise Time Tf: Descent time V: Voltage VDDF: First driving voltage VDDR: Second drive voltage VSS: Reference potential; Z[N]: Second control potential; ΔV: Voltage change. Detailed Implementation

[0023] To provide a better understanding of the structural features and effects achieved by this utility model, preferred embodiments and detailed descriptions are provided below:

[0024] Given that conventional gate drive circuits maintain a high refresh rate display even in static images, resulting in wasted power consumption, and that only one noise suppression circuit suppresses noise, placing a heavy stress on the noise suppression circuit, this invention proposes a gate drive circuit with refresh rate modulation. This circuit provides a pull-down circuit coupled to a masking signal. When the masking signal is enabled, the pull-down circuit pulls down a first control potential between a charging / discharging circuit and an output circuit to a corresponding reference potential. A first control circuit controls the first bias potential to maintain at the potential of the first input signal based on the enabled masking signal, and a second control circuit controls the second bias potential to maintain at the potential of the second input signal based on the enabled masking signal, thereby preventing the output circuit from generating an output signal.

[0025] The following will further explain the characteristics provided by the gate drive circuit with refresh rate modulation disclosed in this utility model, and the system it is paired with:

[0026] First, please refer to Figure 2 , Figure 3 and Figure 4 This is a schematic diagram of a single-stage gate driving circuit, a multi-stage gate driving circuit, and a driving circuit according to an embodiment of the present invention. As shown in the figure, the present invention provides a gate driving circuit with refresh rate modulation. This embodiment uses the Nth stage gate driving circuit N1A as an example. It receives a clock signal CLK, a first input signal ECK, a second input signal EXCK, a first driving voltage VDDF, a second driving voltage VDDR, and a reference potential VSS from an external circuit. This embodiment uses a control circuit 300 as an example of an external circuit. It provides a plurality of clock signals, a start signal Start, the first input signal ECK, the second input signal EXCK, the first driving voltage VDDF, the second driving voltage VDDR, and the reference potential VSS to a driving circuit 100 to drive the driving circuit 100 to provide a plurality of output signals, such as the first output signal G1 to the Nth output signal G[N].

[0027] These clock signals are a first clock signal CLK1 to an Nth clock signal CLKN, which is an example of clock signal CLK, where N is a natural number greater than 4. The driving circuit 100 includes a plurality of gate driving circuits. In this embodiment, the Nth-level gate driving circuit N1A, the (N-4)th-level gate driving circuit N2A, and the (N+4)th-level gate driving circuit N3A are used as examples. However, these gate driving circuits are not limited to only 3 levels; rather, 3 levels of gate driving circuits are used as an example. The Nth-level gate driving circuit N1A includes a charging / discharging circuit 10, an output circuit 20, a pull-down circuit 30, a first noise suppression circuit 40, and a second noise suppression circuit 50.

[0028] Further reading Figure 2 and Figure 3 The charging / discharging circuit 10 receives a first control signal G[N-4] generated by a gate driving circuit N2A of the (N-4)th stage and a second control signal G[N+4] generated by a gate driving circuit N3A of the (N+4)th stage. It also receives the first driving voltage VDDF and the second driving voltage VDDR from the external circuit. The charging / discharging circuit 10 controls a first control potential A[N] of a first control node 22 based on the first control signal G[N-4], the second control signal G[N+4], the first driving voltage VDDF, and the second driving voltage VDDR. The output circuit 20 is coupled to the first control node 22 and an output terminal OUT, and receives the clock signal CLK. It generates a corresponding output signal G[N] to the output terminal OUT based on the clock signal CLK and the first control potential A[N]. The pull-down circuit 30 is coupled between the charging / discharging circuit 10 and the output circuit 20 and receives a shielding signal MSK and the reference potential VSS.

[0029] Following the above, the first noise suppression circuit 40 is coupled to the first control node 22 and the output terminal OUT, and is also coupled to the first input signal ECK and the reference potential VSS. The first noise suppression circuit 40 controls the potentials of the first control potential A[N] and the output signal G[N] according to the first input signal ECK, and receives the masking signal MSK to control the potentials of the first control potential A[N] and the output signal G[N]. The second noise suppression circuit 50 is coupled to the first control node 22 and the output terminal OUT, and receives the second input signal EXCK and the reference potential VSS. The second noise suppression circuit 50 controls the potentials of the first control potential A[N] and the output signal G[N] according to the second input signal EXCK, and receives the masking signal MSK to control the potentials of the first control potential A[N] and the output signal G[N].

[0030] Continuing from the above, in the Nth-stage gate drive circuit N1A of this invention, when the masking signal MSK is enabled, the pull-down circuit 30 controls the first control potential A[N] of the first control node 22 to be pulled down to the corresponding reference potential VSS according to the masking signal MSK. The first control circuit 44 controls the first bias potential B[N] to be maintained at the potential of the first input signal ECK according to the masking signal MSK. The second control circuit 54 controls the second bias potential C[N] according to the masking signal MSK. [N] is maintained at the potential of the second input signal EXCK. Thus, when the masking signal MSK is enabled, in addition to the pull-down circuit 30 controlling the first control potential A[N] to pull down to the corresponding reference potential VSS, causing the output circuit 20 to be unable to output the output signal G[N], the first noise suppression circuit 40 and the second noise suppression circuit 50 continue to suppress noise, that is, the first control potential A[N] and the output signal G[N] are continuously pulled down to the corresponding reference potential VSS.

[0031] like Figures 5A to 5D and Figures 6A to 6D As shown, it is a schematic diagram of a single-stage gate drive circuit in forward scanning, a schematic diagram of the first control electrode in forward scanning, a schematic diagram of a single-stage gate drive circuit in reverse scanning, and a schematic diagram of the first control electrode in reverse scanning, according to an embodiment of the present invention; Figure 5A and Figure 5B As shown, when the Nth-stage gate drive circuit N1A performs a forward scan, the first drive voltage VDDF is relatively high, while the second drive voltage VDDR is relatively low. The first transistor M1A and the second transistor M2A control the first control potential A[N] of the first control node 22 according to the first control signal G[N-4] and the second control signal G[N+4]. Figure 5B The waveform changes shown. Figure 5C and Figure 5D As shown, when the masking signal MSK is enabled, the first control potential A[N] is pulled down by the pull-down circuit 30 to the corresponding reference potential VSS, thus causing the Nth stage gate drive circuit N1A to fail to generate the output signal G[N] during forward scanning.

[0032] Continuing from the above, such as Figure 6A and Figure 6B As shown, when the Nth-stage gate drive circuit N1A performs a reverse scan, the first drive voltage VDDF corresponds to a low potential, while the second drive voltage VDDR corresponds to a high potential. The first transistor M1A and the second transistor M2A control the first control potential A[N] of the first control node 22 according to the first control signal G[N-4] and the second control signal G[N+4]. Figure 6B The waveform changes shown. Figure 6C and Figure 6D As shown, when the masking signal MSK is enabled, the first control potential A[N] is pulled down by the pull-down circuit 30 to the corresponding reference potential VSS, thus causing the Nth stage gate drive circuit N1A to fail to generate the output signal G[N] during reverse scanning.

[0033] See also Figure 4 And see also Figure 7A and Figure 7B This diagram illustrates the enabling and disabling of the masking signal according to an embodiment of the present invention. As shown, when the masking signal MSK is disabled, the drive circuit 100 operates normally. In this embodiment, the drive circuit 100 receives the first clock signal CLK1 to the eighth clock signal CLK8 and the start signal Start, providing corresponding first control potentials A1 and A5, thus generating corresponding output signals G1 and G5. However, when the masking signal MSK is enabled, although the drive circuit 100 receives the first clock signal CLK1 to the eighth clock signal CLK8 and the start signal Start, it does not provide the corresponding first control potentials A1 and A5, and therefore does not generate the corresponding output signals G1 and G5. In other words, the enabled masking signal MSK prevents the drive circuit 100 from generating these output signals G1 and G5.

[0034] Furthermore, the timing of enabling and disabling the masking signal MSK in this invention corresponds to the refresh rate of the display device electrically connected to the gate driving circuit of this invention. Therefore, in addition to corresponding to the timing of the first clock signal CLK1 to the eighth clock signal CLK8, it also corresponds to the timing of the start signal Start, thereby allowing the gate driving circuit of this invention to generate the corresponding pulse waveform of the output signal G[N] according to the refresh rate of the display device. In this embodiment, the enabling of the masking signal MSK is synchronized with the enabling of the start signal Start, but this invention is not limited to this and can also make the enabling of the masking signal MSK and the enabling of the start signal Start asynchronous. The following further explains the refresh rate.

[0035] Please see Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B and Figure 11CThis diagram illustrates the output signal of this invention relative to the masking signal at 60Hz, 30Hz, and 20Hz, as well as the display diagrams at 60Hz, 30Hz, and 20Hz. As shown, the gate drive circuit of this invention is illustrated using a 60Hz screen refresh rate as an example of a maximum percentage 100% refresh rate, and a display device electrically connected to the gate drive circuit of this invention is illustrated using refresh display frames 1 to 6 as examples to demonstrate how this invention modulates the refresh rate. Since the refresh rate is 60Hz, generally 60Hz makes the display period of each display frame 16.67 milliseconds (ms), and... Figure 8 and Figure 11A As shown, when the display device (not shown) does not adjust the refresh rate, that is, when the masking signal MSK is not enabled during the display period of each display frame, the display device (not shown) refreshes display frames 1 to 6.

[0036] Continuing from the above, such as Figure 9 and Figure 11B As shown, when the refresh rate of the display device (not shown) is adjusted from 60Hz to 30Hz, that is, when the masking signal MSK is enabled during the display period of odd-numbered or even-numbered display frames, the display device (not shown) refreshes half of the display frames from Frame 1 to Frame 6. In this embodiment, the masking signal MSK is enabled during the display period of even-numbered display frames, so the display device (not shown) refreshes the odd-numbered display frames, that is, refreshes Frame 1, Frame 3, and Frame 5.

[0037] Continuing from the above, such as Figure 10 and Figure 11C As shown, when the refresh rate of the display device (not shown) is adjusted from 60Hz to 20Hz, that is, when the masking signal MSK is enabled during the display period of two of the three display frames, the display device (not shown) only refreshes one-third of the display frames from Frame 1 to Frame 6. In this embodiment, the masking signal MSK is enabled during the display periods of Frame 2, Frame 3, Frame 5, and Frame 6. Therefore, the display device (not shown) refreshes Frame 1 and Frame 4, that is, it refreshes Frame 1 and Frame 4.

[0038] Please see Figure 12This is a schematic diagram of the gate driving circuit of another embodiment of the present invention. As shown in the figure, the circuit block of the Nth stage gate driving circuit N1A of the present invention is the same as that of the previous embodiment. This embodiment further describes the detailed circuit of each circuit block. The charging and discharging circuit 10 includes a first transistor M1A and a second transistor M2A. A first terminal of the first transistor M1A is coupled to the first control signal G[N-4], a second terminal of the first transistor M1A is coupled to the first driving voltage VDDF, and a first terminal of the second transistor M2A is coupled to the second control signal G[N+4]. A second terminal of the second transistor M2A is coupled to the second driving voltage VDDR, and a third terminal of the second transistor M2A is connected to a third terminal of the first transistor M1A. The pull-down circuit 30 is coupled to the output circuit 20; wherein, when the first control signal G[N-4] drives the first transistor M1A to turn on, the first control potential A[N] of the first control node 22 is driven to correspond to the first driving voltage VDDF; when the second control signal G[N+4] drives the second transistor M2A to turn on, the first control potential A[N] of the first control node 22 is driven to correspond to the second driving voltage VDDR, thereby controlling the output circuit 20 to generate the output signal G[N].

[0039] Continuing from the above, the output circuit 20 includes a third transistor M3A, one of its first terminals being coupled to the first control node 22 to obtain the first control potential A[N]. A second terminal of the third transistor M3A receives the clock signal CLK, and a third terminal of the third transistor M3A is coupled to the output terminal OUT, so that the third transistor M3A generates the output signal G[N] based on the first control potential A[N] of the first control node 22 and the clock signal CLK. At the same time, the output circuit 20 may further include a capacitor C, which is coupled to the first terminal and the third terminal of the third transistor M3A, so that the effect of the first control potential A[N] being turned on to the output terminal OUT is more obvious. The pull-down circuit 30 includes a first shielding transistor Mm0, a first terminal of which is coupled to the shielding signal MSK, a second terminal of which is coupled between the charging / discharging circuit 10 and the output circuit 20, and a third terminal of which is coupled to the reference potential VSS. When the shielding signal MSK is enabled, the first shielding transistor Mm0 is turned on according to the enabled shielding signal MSK, thereby controlling the first control potential A[N] of the first control node 22 to be pulled down to the corresponding reference potential VSS, so as to prevent the third transistor M3A from generating the output signal G[N] according to the clock signal CLK and the first control potential A[N].

[0040] Continuing from the above, the first noise suppression circuit 40 further includes a fourth transistor M4A, a fifth transistor M5A, a sixth transistor M6A, an eighth transistor M8A, and a ninth transistor M9A. A first terminal and a second terminal of the fourth transistor M4A are coupled to the first input signal ECK. Further, a first terminal of the fifth transistor M5A is coupled to the second input signal EXCK. A second terminal of the fifth transistor M5A and a third terminal of the fourth transistor M4A are coupled to the first control circuit 44. A first terminal of the sixth transistor M6A is coupled between the charging / discharging circuit 10 and the output circuit 20. A second terminal of the sixth transistor M6A is coupled to the first bias node 42 to receive the first... A bias potential B[N] is provided. A third terminal of the sixth transistor M6A is coupled to the reference potential VSS. A first terminal of the eighth transistor M8A is coupled to the first bias potential B[N]. A second terminal of the eighth transistor M8A is coupled between the charging / discharging circuit 10 and the output circuit 20, i.e., coupled to the first control potential A[N]. A third terminal of the eighth transistor M8A is coupled to the reference potential VSS. A first terminal of the ninth transistor M9A is coupled to the first bias node 42 to receive the first bias potential B[N]. A second terminal of the ninth transistor M9A is coupled to the output terminal OUT, i.e., coupled to the output signal G[N]. A third terminal of the ninth transistor M9A is coupled to the reference potential VSS.

[0041] Continuing from the above, the first control circuit 44 includes a second shielding transistor Mm1, a first terminal of which is coupled to the shielding signal MSK, a second terminal of which is coupled to the first bias potential, and a third terminal of which is coupled to the first input signal ECK. When the shielding signal MSK is enabled, the first control circuit 44 controls the first bias potential B[N] to maintain at the potential of the first input signal ECK according to the shielding signal MSK, so as to control the first noise suppression circuit 40 to continuously control the eighth transistor M8A and the ninth transistor M9A to continuously pull down the first control potential A[N] between the output signal G[N] of the output terminal OUT and the charging / discharging circuit 10 and the output circuit 20 to the corresponding reference potential VSS according to the first bias potential B[N].

[0042] Continuing from the above, the second noise suppression circuit 50 further includes a tenth transistor M10A, an eleventh transistor M11A, a twelfth transistor M12A, a fourteenth transistor M14A, and a fifteenth transistor M15A. A first terminal and a second terminal of the tenth transistor M10A are coupled to the second input signal EXCK. A first terminal of the eleventh transistor M11A is coupled to the first input signal ECK. A second terminal and a third terminal of the eleventh transistor M11A are coupled to the second control circuit 54. A first terminal of the twelfth transistor M12A is coupled between the charging / discharging circuit 10 and the output circuit 20. A second terminal of the twelfth transistor M12A is coupled to… The second bias node 52 receives the second bias potential C[N]. A third terminal of the twelfth transistor M12A receives the reference potential VSS. A first terminal of the fourteenth transistor M14A is coupled to the second bias node 52 to receive the second bias potential C[N]. A second terminal of the fourteenth transistor M14A is coupled between the charging / discharging circuit 10 and the output circuit 20. A third terminal of the fourteenth transistor M14A is coupled to the reference potential VSS. A first terminal of the fifteenth transistor M15A is coupled to the second bias potential C[N]. A second terminal of the fifteenth transistor M15A is coupled to the output terminal OUT. A third terminal of the fifteenth transistor M15A is coupled to the reference potential VSS.

[0043] Continuing from the above, the second control circuit 54 includes a third shielding transistor Mm2, a first terminal of which is coupled to the shielding signal MSK, a second terminal of which is coupled to the second bias potential C[N], and a third terminal of which is coupled to the second input signal EXCK. When the shielding signal MSK is enabled, the second control circuit 54 controls the second bias potential C[N] to maintain at the potential of the second input signal EXCK according to the shielding signal MSK, so as to control the second noise suppression circuit 50 to continuously control the fourteenth transistor M14A and the fifteenth transistor M15A to continuously pull down the first control potential A[N] between the output signal G[N] and the charging / discharging circuit 10 and the output circuit 20 to the corresponding reference potential VSS according to the first bias potential B[N].

[0044] Please see Figure 13 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention. Figure 12 and Figure 13 The difference lies in, for example Figure 12 The fifth transistor M5A and the eleventh transistor M11A of the first noise suppression circuit 40 and the second noise suppression circuit 50 of the Nth gate drive circuit N1A shown respectively receive the second input signal EXCK and the first input signal ECK, and as shown... Figure 13 The first noise suppression circuit 40 of the Nth gate drive circuit N1B and the fifth transistor M5B and eleventh transistor M11B of the second noise suppression circuit 50 are respectively coupled between the charge / discharge circuit 10 and the output circuit 20, and in particular coupled to the first control potential A[N] of the first control node 22. Therefore, as shown Figure 12 As shown, a first terminal of the fifth transistor M5B and a first terminal of the sixth transistor M6B are coupled to the first control node 22 to receive the first control potential A[N]. Furthermore, a first terminal of the eleventh transistor M11B and a first terminal of the twelfth transistor M12B are coupled to the first control potential A[N]. In this embodiment, the first input signal ECK and the second input signal EXCK are both high DC potentials. Therefore, the first noise suppression circuit 40 and the second noise suppression circuit 50 further suppress noise based on the first control potential A[N]. Other operating methods, such as the signal operation corresponding to the masking signal MSK and the operation of generating the output signal G[N], are the same as in the previous embodiment and will not be described again.

[0045] Please see Figure 14 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention. Figure 12 and Figure 14 The difference lies in, for example Figure 14 The Nth-stage gate drive circuit N1C shown is further provided with a bridge circuit 15, which is coupled between the charging / discharging circuit 10 and the output circuit 20. In particular, in this embodiment, the bridge circuit 15 is coupled between the first control potential A[N] of the first control node 22 and the second control potential Z[N] of a second control node 12. The pull-down circuit 30 is coupled between the charging / discharging circuit 10 and the bridge circuit 15. Furthermore, the second terminal of the first shielding transistor Mm0 of the pull-down circuit 30 is coupled between the charging / discharging circuit 10 and the bridge circuit 15. The remaining connections are the same as those of the Nth-stage gate drive circuit N1A, so they will not be described again.

[0046] Continuing from the above, in detail, the Nth-level gate drive circuit N1C of this embodiment further blocks the voltage division caused by the parasitic capacitance of the first transistor M1A and the second transistor M2A through the bridge circuit 15, that is, to prevent the voltage division caused by the parasitic capacitance of the first transistor M1A and the second transistor M2A from affecting the first control potential A[N] of the first control node 22. The bridge circuit 15 includes a bridge transistor Mbr, one of its first and second ends of which are coupled to the second control node 12. The third end of the bridge transistor Mbr is coupled to the first control node 22. That is, the first and second ends of the bridge transistor Mbr are coupled to the second control potential Z[N]. The third end of the bridge transistor Mbr is coupled to the first control potential A[N] and the pull-down circuit 30. The third end of the bridge transistor Mbr is further coupled to the second end of the first shielding transistor Mm0. When the shielding signal MSK is enabled, the pull-down circuit 30 will pull down the second control potential Z[N] to the corresponding reference potential VSS, thereby controlling the first control potential A[N] to be pulled down to the corresponding reference potential VSS. The other operating behaviors are the same as those of the Nth gate drive circuit N1A, so they will not be described in detail.

[0047] like Figure 15A and Figure 15B As shown, it is a schematic diagram of a single-stage gate drive circuit forward scanning and a signal schematic diagram of the first control electrode being forward scanning, according to another embodiment of the present invention; wherein the Figures 5A to 5B and Figures 15A to 15B The difference lies in, for example Figures 15A to 15B The first control potential A[N] shown is further increased during the output phase when the masking signal MSK is disabled, thereby shortening the rise time (Tr) and fall time (Tf) of the output signal G[N]. Figure 15C and Figure 15D As shown, it is a schematic diagram of a single-stage gate drive circuit forward scanning with the masking signal enabled and a schematic diagram of the first control voltage being enabled and forward scanning with the masking signal enabled, according to another embodiment of the present invention. When the masking signal MSK is enabled, based on the threshold voltage of the bridge transistor Mbr of the bridge circuit 15, the first control potential A[N] is pulled down to be closer to the reference potential VSS. Therefore, this embodiment provides a better suppression effect for the output signal G[N].

[0048] like Figure 16A and Figure 16B As shown, it is a schematic diagram of the reverse scanning of a single-stage gate drive circuit and a schematic diagram of the signal of the first control electrode during reverse scanning, according to another embodiment of the present invention; wherein the Figures 6A to 6B and Figures 16A to 16B The difference lies in, for example Figures 16A to 16BThe first control potential A[N] shown is further increased during the output phase when the masking signal MSK is disabled, thereby shortening the rise time (Tr) and fall time (Tf) of the output signal G[N]. Figure 16C and Figure 16D As shown, it is a schematic diagram of a single-stage gate drive circuit in reverse scanning with the masking signal enabled, and a schematic diagram of the first control voltage at the masking signal enabled and in reverse scanning, according to another embodiment of the present invention. When the masking signal MSK is enabled, based on the threshold voltage of the bridge transistor Mbr of the bridge circuit 15, the first control potential A[N] is pulled down to be closer to the reference potential VSS. Therefore, this embodiment provides a better suppression effect for the output signal G[N].

[0049] like Figure 17A and Figure 17B As shown, it is a schematic diagram of the signal for disabling the masking signal and a schematic diagram of the signal for enabling the masking signal, according to another embodiment of this utility model; wherein Figure 7A and Figure 17A The difference lies in Figure 17A The first control potentials A1 and A5 are boosted to a higher potential during the output stage, while Figure 7B and Figure 17B The difference lies in Figure 17B The first control potentials A1 and A5 are further suppressed to approach the reference potential VSS, thus approaching the DC state, which means that the signal waveform will approach a straight line.

[0050] like Figure 18 The diagram shown is a schematic representation of a gate drive circuit according to another embodiment of this invention. Figure 14 and Figure 18 The difference lies in, for example Figure 14 The fifth transistor M5A and the eleventh transistor M11A of the first noise suppression circuit 40 and the second noise suppression circuit 50 of the Nth gate drive circuit N1C shown are respectively coupled to the second input signal EXCK and the first input signal ECK, and as shown... Figure 18 The first noise suppression circuit 40 and the fifth transistor M5B and the eleventh transistor M11B of the Nth gate drive circuit N1D shown are respectively coupled between the charge / discharge circuit 10 and the output circuit 20, and in particular coupled to the first control potential Z[N] of the second control node 12. Therefore, as Figure 18As shown, a first terminal of the fifth transistor M5B and a first terminal of the sixth transistor M6B are coupled together to the second control potential Z[N]. A first terminal and a second terminal of the fourth transistor M4B are coupled together to the second terminal of the seventh transistor M7B to the first input signal ECK. A first terminal of the seventh transistor M7B is coupled between a third terminal of the fourth transistor M4B and a second terminal of the fifth transistor M5B. When the fourth transistor M4B receives the first input signal ECK and turns on, it will drive the seventh transistor M7B to turn on as well, thereby controlling the first bias potential B[N] of the first bias node 42 to rise.

[0051] Continuing from the above, a first terminal of the eleventh transistor M11B and a first terminal of the twelfth transistor M12B are coupled together to the second control potential Z[N]. The second control potential Z[N] can be turned on by the bridge circuit 15 to make its potential equal to the first control potential A[N]. Furthermore, a first terminal and a second terminal of the tenth transistor M10B are coupled together with a second terminal of the thirteenth transistor M13B to the first input signal ECK. A first terminal of the thirteenth transistor M13B is coupled between a third terminal of the tenth transistor M10B and a second terminal of the eleventh transistor M11B. When the tenth transistor... When transistor M10B receives the first input signal EXCK and turns on, it will also drive the thirteenth transistor M13B to turn on, thereby controlling the first bias potential B[N] of the first bias node 42 to rise. In this embodiment, the first input signal ECK and the second input signal EXCK are both high DC potentials. Therefore, the first noise suppression circuit 40 and the second noise suppression circuit 50 further suppress noise according to the second control potential Z[N]. Other operation methods, such as the signal operation corresponding to the masking signal MSK and the operation of generating the output signal G[N], are the same as in the previous embodiment, so they will not be described again.

[0052] Please see Figure 19 This is a schematic diagram of a gate drive circuit according to another embodiment of the present invention. Figure 14 and Figure 19 The difference lies in, for example Figure 19 The Nth-stage gate drive circuit N1D shown further configures the pull-down circuit 30 to be coupled between the charge / discharge circuit 10 and the bridge circuit 15. Furthermore, the second terminal of the first shielding transistor Mm0 of the pull-down circuit 30 is coupled between the charge / discharge circuit 10 and the bridge circuit 15. Figure 19The Nth-level gate drive circuit N1D shown is further configured such that the pull-down circuit 30 is coupled between the bridge circuit 15 and the output circuit 20. Furthermore, the second terminal of the first shielding transistor Mm0 of the pull-down circuit 30 is coupled between the bridge circuit 15 and the output circuit 20. The remaining connection relationships are the same as those of the Nth-level gate drive circuit N1A, and therefore will not be described in detail.

[0053] In detail, based on the voltage divider formula: It can be seen that the first control potential A[N] increases by a boost potential difference ΔV from the pre-charging stage to the output stage. A[N] The reference clock signal CLK and the potential ΔV of the output signal G[N] are used as references. clk With ΔV G[N] Therefore, the boost potential difference ΔV is obtained. A[N] And like Figure 13 The capacitor C formed by the charging / discharging circuit 10 to the output circuit 20 shown is total C b +C gdM3B +C gsM3B +C gs_Mbr , and like Figure 19 The capacitor C formed by the charging / discharging circuit 10 to the output circuit 20 shown is total C b +C gdM3A +C gsM3A +C gs_Mbr +C gd_mm0 ,Right now Figure 19 The capacitor C shown total Compared to Figure 13 The capacitor C shown total Further increase the capacitance change by an amount, which is the parasitic capacitance C of the first shielding transistor Mm0. gd_mm0 Therefore, Figure 19 The first control potential A[N] shown is further reduced by a voltage change ΔV, for example: reducing a threshold voltage Vth of a transistor corresponds to the output stage of the first control potential A[N].

[0054] like Figures 20A to 20D As shown, when the Nth-stage gate drive circuit N1A performs a forward scan, the first drive voltage VDDF is relatively high, while the second drive voltage VDDR is relatively low. The first transistor M1A and the second transistor M2A control the first control potential A[N] of the first control node 22 according to the first control signal G[N-4] and the second control signal G[N+4]. Figure 20B The waveform change shown is such that the first control potential A[N] reduces the voltage change ΔV during the output phase.

[0055] Continuing from the above, such as Figures 21A to 21D As shown, when the Nth-stage gate drive circuit N1A performs a reverse scan, the first drive voltage VDDF corresponds to a low potential, while the second drive voltage VDDR corresponds to a high potential. The first transistor M1A and the second transistor M2A control the first control potential A[N] of the first control node 22 according to the first control signal G[N-4] and the second control signal G[N+4]. Figure 21B The waveform change shown is such that the first control potential A[N] reduces the voltage change ΔV during the output phase.

[0056] like Figure 22 The diagram shown is a schematic representation of a gate drive circuit according to another embodiment of this invention. Figure 19 and Figure 22 The difference lies in Figure 22 The first terminal of the fifth transistor M5B and the first terminal of the sixth transistor M6B are coupled together to the first control potential A[N]. Similarly, the first terminal of the eleventh transistor M11B and the first terminal of the twelfth transistor M12B are coupled together to the first control potential A[N]. In this embodiment, the first input signal ECK and the second input signal EXCK are both high DC potentials. Therefore, the first noise suppression circuit 40 and the second noise suppression circuit 50 further suppress noise based on the first control potential A[N]. Other operating methods, such as the signal operation corresponding to the masking signal MSK and the operation of generating the output signal G[N], are the same as... Figure 19 In the embodiment, the operation of the fourth transistor M4B and the seventh transistor M7B, as well as the operation of the tenth transistor M10B and the thirteenth transistor M13B, are the same as... Figure 18 The embodiments are as described above, and therefore will not be repeated.

[0057] In summary, the gate drive circuit with refresh rate modulation of this invention provides a pull-down circuit coupled between a charging / discharging circuit and an output circuit, and coupled to a masking signal and a reference potential. When the masking signal is enabled, the pull-down circuit pulls down a control potential between the charging / discharging circuit and the output circuit to the corresponding reference potential, such as pulling down the first control potential of the first control node or the second control potential of the second control node to the corresponding reference potential, thereby preventing the output circuit from generating the output signal. Furthermore, this invention further includes a first control circuit and a second control circuit in the first noise suppression circuit and the second noise suppression circuit, respectively, to control the first noise suppression circuit and the second noise suppression circuit to suppress noise based on the enabled masking signal, thereby preventing the output circuit from erroneously outputting the output signal.

[0058] The sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0059] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present utility model should be included in the scope of the claims of the present utility model.

Claims

1. A gate drive circuit with refresh rate modulation, characterized in that, It receives a clock signal, a first input signal, a second input signal, a first drive voltage, a second drive voltage, and a reference potential from an external circuit. The gate drive circuit with refresh rate modulation includes: A charging and discharging circuit receives a first control signal, a second control signal, a first driving voltage and a second driving voltage, and controls a first control potential of a first control node according to the first control signal, the second control signal, the first driving voltage and the second driving voltage; An output circuit receives the clock signal and is coupled to the first control node and an output terminal, and generates a corresponding output signal to the output terminal based on the clock signal and the first control potential. A pull-down circuit is coupled between the charging / discharging circuit and the output circuit and receives a shielding signal and the reference potential; A first noise suppression circuit receives the first input signal and the reference potential, and is coupled to the first control node and the output terminal. The first noise suppression circuit generates a first bias potential to a first bias node based on the first input signal to control the first control potential and the potential of the output signal. A first control circuit is provided, which receives the shielding signal and the first input signal. as well as A second noise suppression circuit receives the second input signal and the reference potential, and is coupled to the first control node and the output terminal. The second noise suppression circuit generates a second bias potential to a second bias node based on the second input signal to control the potential of the first control potential and the output signal. A second control circuit is also provided, which receives the shielding signal and the second input signal. When the masking signal is enabled, the pull-down circuit controls the first control node to be pulled down to the corresponding reference potential according to the masking signal. The first control circuit controls the first bias potential to be maintained at the potential of the first input signal according to the masking signal. The second control circuit controls the second bias potential to be maintained at the potential of the second input signal according to the masking signal.

2. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, It also includes: A bridge circuit is coupled to the first control node and a second control node. The second control node is coupled between the bridge circuit and the charging / discharging circuit. The first control node is coupled between the bridge circuit and the output circuit. The bridge circuit enables the first control potential to be conducted from the first control node to the second control node to form a second control potential. The output circuit generates the output signal based on the clock signal and the second control potential.

3. The gate drive circuit with refresh rate modulation as described in claim 2, characterized in that, The bridge circuit includes: A bridge transistor has a first terminal and a second terminal coupled to the first control node, and a third terminal coupled to the second control node, so that the first control potential is conducted from the first control node to the second control node to form the second control potential.

4. The gate drive circuit with refresh rate modulation as described in claim 2, characterized in that, The pull-down circuit is further coupled between the bridge circuit and the charging / discharging circuit.

5. The gate drive circuit with refresh rate modulation as described in claim 2, wherein the pull-down circuit is further coupled between the bridge circuit and the output circuit.

6. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The charging and discharging circuit includes: A first transistor, wherein a first terminal receives the first control signal, and a second terminal of the first transistor receives the first drive voltage; and A second transistor, wherein a first terminal of the second transistor receives the second control signal, a second terminal of the second transistor receives the second drive voltage, and a third terminal of the second transistor is coupled to the third terminal of the first transistor to the pull-down circuit and the output circuit; Specifically, when the first control signal drives the first transistor to turn on, the first control potential of the first control node corresponds to the first driving voltage; when the second control signal drives the second transistor to turn on, the first control potential of the first control node corresponds to the second driving voltage.

7. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The output circuit includes: A third transistor, a first terminal of which is coupled to the first control node, a second terminal of which receives the clock signal, and a third terminal of which is coupled to the output terminal, so as to generate the output signal according to the first control potential and the clock signal.

8. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The pull-down circuit includes: A first shielding transistor has a first terminal receiving the shielding signal, a second terminal of the first shielding transistor being coupled between the charging / discharging circuit and the output circuit, and a third terminal of the first shielding transistor receiving the reference potential.

9. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The first noise suppression circuit further includes: A fourth transistor, wherein a first terminal and a second terminal receive the first input signal; A fifth transistor, a first terminal of which receives the second input signal, and a second terminal of the fifth transistor coupled to a third terminal of the fourth transistor in the first control circuit; A sixth transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, a second terminal of which is coupled to the first bias node, and a third terminal of which receives the reference potential; An eighth transistor, a first terminal of which is coupled to the first bias node, a second terminal of which is coupled between the charging / discharging circuit and the output circuit, and a third terminal of which receives the reference potential; as well as A ninth transistor, a first terminal of which is coupled to the first bias node, a second terminal of which is coupled to the output terminal, and a third terminal of which is coupled to the reference potential.

10. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The first noise suppression circuit further includes: A fourth transistor, wherein a first terminal and a second terminal are coupled to the first input signal; A fifth transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, and a second terminal of the fifth transistor and a third terminal of the fourth transistor are coupled to the first control circuit. A sixth transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, a second terminal of which is coupled to the first bias node, and a third terminal of which is coupled to the reference potential; A seventh transistor, a first terminal of which is coupled between the third terminal of the fourth transistor and the second terminal of the fifth transistor, a second terminal of the seventh transistor is coupled between the first terminal and the second terminal of the fourth transistor and is coupled to the first input signal, and a third terminal of the seventh transistor is coupled to the first bias node. An eighth transistor, a first terminal of which is coupled to the first bias node, a second terminal of which is coupled between the charging / discharging circuit and the output circuit, and a third terminal of which receives the reference potential; as well as A ninth transistor, a first terminal of which is coupled to the first bias node, a second terminal of which is coupled to the output terminal, and a third terminal of which receives the first input signal.

11. The gate drive circuit with refresh rate modulation as described in claim 9 or 10, characterized in that, The first control circuit includes: A second shielding transistor, wherein a first terminal of the second shielding transistor receives the shielding signal, a second terminal of the second shielding transistor is coupled to the first bias node, and a third terminal of the second shielding transistor receives the first input signal.

12. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The second noise suppression circuit further includes: A tenth transistor, wherein a first terminal and a second terminal receive the second input signal; An eleventh transistor, a first terminal of which receives the first input signal, and a second terminal of the eleventh transistor and a third terminal of the tenth transistor are coupled to the second control circuit. A twelfth transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, a second terminal of which is coupled to the second bias potential, and a third terminal of which is coupled to the reference potential; A fourteenth transistor, a first terminal of which is coupled to the second bias potential, a second terminal of which is coupled between the charging / discharging circuit and the output circuit, and a third terminal of which is coupled to the reference potential; as well as A fifteenth transistor, a first terminal of which is coupled to the second bias node, a second terminal of the fourteenth transistor is coupled to the output terminal, and a third terminal of the fourteenth transistor is coupled to the reference potential.

13. The gate drive circuit with refresh rate modulation as described in claim 1, characterized in that, The second noise suppression circuit further includes: A tenth transistor, wherein a first terminal and a second terminal receive the second input signal; An eleventh transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, and a second terminal of the eleventh transistor and a third terminal of the tenth transistor are coupled to the second control circuit. A twelfth transistor, a first terminal of which is coupled between the charging / discharging circuit and the output circuit, a second terminal of which is coupled to the second bias potential, and a third terminal of which is coupled to the reference potential; A thirteenth transistor, a first terminal of which is coupled between the third terminal of the tenth transistor and the second terminal of the eleventh transistor, a second terminal of the thirteenth transistor being coupled between the first and second terminals of the tenth transistor and coupled to the second input signal, and a third terminal of the thirteenth transistor being coupled to the second bias node; A fourteenth transistor, a first terminal of which is coupled to the second bias node, a second terminal of which is coupled between the charging / discharging circuit and the output circuit, and a third terminal of which is coupled to the reference potential; as well as A fifteenth transistor, a first terminal of which is coupled to the second bias node, a second terminal of which is coupled to the output terminal, and a third terminal of which is coupled to the reference potential.

14. The gate drive circuit with refresh rate modulation as described in claim 12 or 13, characterized in that, The second control circuit includes: A third shielding transistor, wherein a first terminal of the third shielding transistor receives the shielding signal, a second terminal of the third shielding transistor is coupled to the second bias node, and a third terminal of the third shielding transistor receives the second input signal.

15. The gate drive circuit with refresh rate modulation as claimed in claim 1, further receiving a start signal from the external circuit, wherein a timing sequence of the masking signal corresponds to a timing sequence of the clock signal and a timing sequence of the start signal.

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