Dual output hybrid synthesizing frequency hopping source device

Abstract

The utility model relates to a kind of double-way output mixed synthesis formula frequency hopping source device, belong to frequency synthesis technical field.Frequency hopping source device includes signal generation subcircuit, frequency multiplication synthesis circuit, phase-locked loop synthesis circuit, mixed frequency synthesis circuit, signal conditioning power subcircuit and logic control circuit.Two-way reference signal of phase is generated by signal generation subcircuit, and two-way reference signal is input frequency multiplication synthesis circuit and phase-locked loop synthesis circuit respectively to carry out frequency multiplication processing and frequency hopping processing, then two-way synthesis signal after frequency multiplication processing and frequency hopping processing is mixed frequency by mixed frequency synthesis circuit, finally again utilize signal conditioning power subcircuit to the conditioning and one-to-two power division of mixed frequency signal, output two-way equal amplitude in-phase synthesis signal, it is convenient to support simultaneously upper frequency conversion and lower frequency conversion use.The utility model mixes frequency to phase-locked loop synthesis output signal and direct analog synthesis output signal, realizes the purpose of mixed synthesis output low phase noise frequency hopping signal.

Description

Technical Field

[0001] This utility model relates to the field of frequency synthesis technology, specifically to a dual-output hybrid synthesis frequency hopping source device. Background Technology

[0002] Currently, there are various frequency synthesis techniques in the L-band, but each technique has its own inherent limitations. Direct analog frequency synthesis, the earliest technique, uses frequency multipliers, dividers, and mixers to perform addition, subtraction, multiplication, and division operations on the source signal to obtain various desired frequencies. Its advantages include extremely high operating frequencies and extremely low phase noise; however, its disadvantages include difficult frequency conversion, numerous output spurious signals, complex circuit structures, and high circuit costs, failing to meet the requirements of modern equipment miniaturization, low power consumption, and low cost. Phase-locked loop (PLL) indirect frequency synthesis technology has a long history, consisting of phase detectors, voltage-controlled attenuators, and frequency dividers. It offers advantages such as high operating frequencies and low output spurious signals, but its disadvantages include long frequency conversion times and high phase noise.

[0003] Direct analog frequency synthesis to output frequency-hopping signals is difficult and complex to implement, but it can achieve very low phase noise. Phase-locked loop (PLL) indirect frequency synthesis facilitates frequency hopping and is simple to implement, but it severely degrades signal phase noise. Therefore, there is an urgent need for a frequency synthesis device with a relatively simple circuit structure and low phase noise. Utility Model Content

[0004] To address the shortcomings of existing technologies, this utility model provides a dual-output hybrid synthesis frequency hopping source device. This addresses the technical problem in existing frequency synthesis devices that struggle to combine the advantages of direct analog synthesis and phase-locked loop synthesis, achieving low-phase-noise, rapid frequency hopping through mixing.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: This utility model provides a dual-output hybrid synthesis frequency hopping source device, including a signal generation power divider circuit, a frequency multiplier synthesis circuit, a phase-locked loop synthesis circuit, a frequency mixer synthesis circuit, a signal conditioning power divider circuit, and a logic control circuit; wherein... The signal generation and splitting circuit is provided with a first reference signal output terminal and a second reference signal output terminal; the first reference signal output terminal is connected to the local oscillator terminal of the mixing and synthesizing circuit via a frequency multiplication and synthesis circuit; the second reference signal output terminal is connected to the intermediate frequency terminal of the mixing and synthesizing circuit via a phase-locked loop synthesis circuit. The output terminal of the mixing and synthesizing circuit is connected to the input terminal of the signal conditioning and power dividing circuit, and the output terminal of the signal conditioning and power dividing circuit is used to power divide and output the first frequency hopping synthesized signal and the first frequency hopping synthesized signal. The logic control circuit has a frequency hopping control terminal and a signal monitoring terminal. The frequency hopping control terminal is connected to a phase-locked loop synthesis circuit, and the signal monitoring terminal is connected to a signal generation and division circuit.

[0006] Preferably, the signal generation and power division circuit includes a temperature-controlled crystal oscillator, a coupling circuit, a first attenuation matching circuit, a first power divider circuit, a second attenuation matching circuit, a detection circuit, and a comparator circuit; wherein, The output terminal of the thermostatic crystal oscillator is connected to the input terminal of the coupling circuit, and the first output terminal of the coupling circuit is connected to the input terminal of the first power divider circuit via the first attenuation matching circuit. The output of the first power divider circuit includes a first reference signal output and a second reference signal output. The first reference signal output is connected to the input of the frequency multiplication and synthesis circuit, and the second reference signal output is connected to the input of the phase-locked loop synthesis circuit. The second output terminal of the coupling circuit is connected to the input terminal of the comparator circuit via the second attenuation circuit and the detection circuit in sequence, and the output terminal of the comparator circuit is connected to the signal monitoring terminal.

[0007] Preferably, the frequency multiplier circuit includes, in sequence, a first power adjustment circuit, a first amplifier circuit, a pre-amplifier matching circuit, a frequency multiplier diode, a post-amplifier matching circuit, a second power adjustment circuit, a first filter circuit, a second amplifier circuit, a second filter circuit, and a third attenuation matching circuit; wherein, The input terminal of the first power adjustment circuit is connected to the output terminal of the first reference signal, and the output terminal of the third attenuation matching circuit is connected to the local oscillator terminal of the mixing and synthesis circuit.

[0008] Preferably, the phase-locked loop synthesis circuit includes a third power adjustment circuit, a phase-locked loop circuit, a third filter circuit, and a loop filter circuit; wherein, The phase-locked loop circuit has a first signal input terminal and a second signal input terminal, and the second signal input terminal is connected to the frequency hopping control terminal. The input terminal of the third power adjustment circuit is connected to the output terminal of the second reference signal, and the output terminal of the third power adjustment circuit is connected to the first signal input terminal of the phase-locked loop circuit. The first output terminal of the phase-locked loop is connected to the input terminal of the loop filter circuit, and the output terminal of the loop filter circuit is connected to the control voltage input terminal of the phase-locked loop circuit. The second output terminal of the phase-locked loop circuit is connected to the intermediate frequency terminal of the mixer-synthesizer circuit via a third filter circuit.

[0009] Preferably, the mixing and synthesizing circuit includes a fourth power adjustment circuit, a fifth power adjustment circuit, a mixing circuit, and a fourth attenuation matching circuit; wherein, The input terminal of the fourth power adjustment circuit is connected to the output terminal of the third attenuation matching circuit, and the output terminal of the fourth power adjustment circuit is connected to the local oscillator terminal of the mixer circuit. The input terminal of the fifth power adjustment circuit is connected to the output terminal of the third filter circuit, and the output terminal of the fifth power adjustment circuit is connected to the intermediate frequency terminal of the mixer circuit. The output of the mixer circuit is connected to the input of the signal conditioning power divider circuit via a fourth attenuation matching circuit.

[0010] Preferably, the signal conditioning power divider circuit includes a fourth filter circuit, a third amplifier circuit, an equalization circuit, a fifth attenuation matching circuit, a second power divider circuit, a sixth attenuation matching circuit, a seventh attenuation matching circuit, a fifth filter circuit, and a sixth filter circuit. The input terminal of the fourth filter circuit is connected to the output terminal of the fourth attenuation matching circuit, and the output terminal of the fourth filter circuit is connected to the input terminal of the second power divider circuit in sequence through the third amplifier circuit, the equalization circuit, and the fifth attenuation matching circuit. The first output of the second power divider circuit is connected to the input of the fifth filter circuit via the sixth attenuation matching circuit. The output of the fifth filter circuit is used to output the first frequency hopping synthesized signal. The second output of the second power divider circuit is connected to the input of the sixth filter circuit via the seventh attenuation matching circuit. The output of the sixth filter circuit is used to output the second frequency hopping synthesized signal.

[0011] Preferably, the dual-output hybrid synthesis frequency hopping source device further includes a first power management circuit; wherein, the input terminal of the first power management circuit is connected to an external power supply, and the output terminal of the first power management circuit is respectively connected to a signal generation power divider circuit, a frequency multiplication synthesis circuit, a phase-locked loop synthesis circuit, a frequency mixing synthesis circuit, a signal conditioning power divider circuit, and a logic control circuit.

[0012] Preferably, the logic control circuit includes a clock generation circuit, an FPGA circuit, a data storage circuit, a second power management circuit, and a serial communication circuit; wherein, The clock generation circuit and data storage circuit are electrically connected to the FPGA circuit; the FPGA circuit is connected to the host computer via a serial communication circuit. The input terminal of the second power management circuit is connected to the output terminal of the first power management circuit, and the output terminal of the second power management circuit is connected to the FPGA circuit, the clock generation circuit, and the data storage circuit, respectively. The output terminal of the FPGA circuit includes a frequency hopping control terminal, a signal monitoring terminal, and a power monitoring terminal. The frequency hopping control terminal is used to output a phase-locked loop control signal, the signal monitoring terminal is used to receive the output signal of the temperature-controlled crystal oscillator, and the power monitoring terminal is connected to the output terminal of the first power management circuit.

[0013] Preferably, the first power management circuit includes a first power supply branch, a second power supply branch, and a third power supply branch; wherein, the first power supply branch includes a first common-mode inductor and a first output filter capacitor connected in sequence; the input terminal of the first common-mode inductor is connected to an external power supply, and the output terminal of the first output filter capacitor is connected to a signal generation and splitting circuit and a frequency multiplier and synthesizer circuit; The second power supply branch includes a second common-mode inductor, a first input filter capacitor, a second input filter capacitor, a first voltage conversion chip, a first voltage divider feedback resistor, a second output filter capacitor, a third output filter capacitor, and a fourth output filter capacitor connected in sequence; the input terminal of the second common-mode inductor is connected to an external power supply, and the output terminal of the fourth output filter capacitor is connected to a phase-locked loop synthesis circuit. The third power supply branch includes a third common-mode inductor, a third input filter capacitor, a fourth input filter capacitor, a second voltage conversion chip, a second voltage divider feedback resistor, a fourth output filter capacitor, a fifth output filter capacitor, a sixth output filter capacitor, and a power supply filter inductor; the input terminal of the third common-mode inductor is connected to an external power supply, and the output terminal of the power supply filter inductor is connected to a logic control circuit, a first amplifier, a second amplifier, and a third amplifier.

[0014] In summary, this utility model has the following beneficial effects: This invention generates two in-phase reference signals through a signal generation and division circuit. These two reference signals are then input into a frequency multiplier synthesis circuit and a phase-locked loop (PLL) synthesis circuit for frequency multiplication and frequency hopping processing, respectively. A mixing synthesis circuit then mixes the two synthesized signals using a 10th-order frequency multiplication plus PLL approach, outputting a synthesized signal. This reduces output phase noise compared to a single PLL technique and accommodates frequency hopping requirements. Finally, a signal conditioning and power division circuit conditions and divides the mixed signal, outputting two equal-amplitude, in-phase synthesized signals, facilitating simultaneous up-conversion and down-conversion. This invention combines the advantages of direct analog frequency synthesis and PLL indirect frequency synthesis, mixing the PLL-synthesized output signal and the direct analog-synthesized output signal to achieve a low-phase-noise frequency-hopping signal through hybrid synthesis. Attached Figure Description

[0015] Figure 1 This is a circuit connection diagram of the dual-output hybrid synthesis frequency hopping source device of this utility model; Figure 2 This is a schematic diagram of the signal generation and splitting circuit structure of this utility model; Figure 3 This is a schematic diagram of the frequency multiplication synthesis circuit structure of this utility model; Figure 4 This is a schematic diagram of the phase-locked loop synthesis circuit structure of this utility model; Figure 5 This is a schematic diagram of the mixing and synthesis circuit structure of this utility model; Figure 6 This is a schematic diagram of the signal conditioning power divider circuit structure of this utility model; Figure 7 This is a schematic diagram of the logic control circuit structure of this utility model; Figure 8 This is a schematic diagram of the first power supply branch structure of this utility model; Figure 9 This is a schematic diagram of the second power supply branch structure of this utility model; Figure 10 This is a schematic diagram of the third power supply branch structure of this utility model; Figure 11 This is a top view of the plug-in chassis of this utility model; Figure 12 This is a right view of the plug-in chassis of this utility model; Figure 13 This is a left view of the plug-in chassis of this utility model.

[0016] Figure label: Figures 11-13 In the middle, 1. Cabinet; 2. Guide rails; 3. Low-frequency power supply control interface; 4. RF coaxial interface; 5. Front panel. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings.

[0018] To make the objectives, solutions, and advantages of this utility model clearer, the following detailed description of this utility model is provided in conjunction with the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this utility model are only used to explain this utility model and are not intended to limit this utility model.

[0019] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to implement the present invention. In other embodiments, well-known structures, circuits, materials, or methods are not specifically described in order to avoid obscuring the present invention.

[0020] Direct analog frequency synthesis to output a frequency-hopping signal is difficult and complex to implement, but it can achieve very low phase noise. Phase-locked loop (PLL) indirect frequency synthesis facilitates frequency hopping and is simple to implement, but it severely degrades signal phase noise. To combine the advantages of both, this invention uses a mixing method to combine the advantages of both. The two signals are mixed using a mixer, and the phase noise of the output signal depends on the signal with the worst phase noise among the two input signals. The following describes the invention in conjunction with the appendix... Figures 1-13 The embodiments of this utility model will be described in detail below.

[0021] Example 1: Refer to Figure 1 As shown, this embodiment provides a dual-output hybrid synthesis frequency hopping source device, mainly including a signal generation power divider circuit, a frequency multiplier synthesis circuit, a phase-locked loop synthesis circuit, a frequency mixer synthesis circuit, a signal conditioning power divider circuit, and a logic control circuit. Among them, The signal generation and division circuit has a first reference signal output terminal and a second reference signal output terminal. The first reference signal output terminal outputs a first reference signal, and the second reference signal output terminal outputs a second reference signal. The first reference signal output terminal is connected to the local oscillator terminal of the frequency mixer synthesis circuit via a frequency multiplier synthesis circuit; the second reference signal output terminal is connected to the intermediate frequency terminal of the frequency mixer synthesis circuit via a phase-locked loop synthesis circuit.

[0022] The output of the frequency mixing and synthesis circuit is connected to the input of the signal conditioning and power divider circuit. The output of the signal conditioning and power divider circuit is used to output the first frequency hopping synthesized signal and the first frequency hopping synthesized signal.

[0023] The logic control circuit has a frequency hopping control terminal and a signal monitoring terminal. The frequency hopping control terminal is connected to the phase-locked loop synthesis circuit, and the signal monitoring terminal is connected to the signal generation and division circuit.

[0024] In this embodiment, the signal generation and dividing circuit has a built-in 100MHz crystal oscillator, which can generate a 100MHz reference signal. The crystal oscillator output signal is monitored through a coupler and a detector. A two-way power divider divides the crystal oscillator output signal into two channels, which are then provided to the frequency multiplication and synthesis circuits and the phase-locked loop synthesis circuit as their input reference clocks. (Refer to...) Figure 2 As shown, the signal generation and power division circuit specifically includes a temperature-controlled crystal oscillator, a coupling circuit, a first attenuation matching circuit, a first power divider circuit, a second attenuation matching circuit, a detection circuit, and a comparator circuit (i.e., corresponding to...). Figure 2 (U1~U7 in the series). The output terminal of the thermostatic crystal oscillator is connected to the input terminal of the coupling circuit, and the first output terminal of the coupling circuit is connected to the input terminal of the first power divider circuit via the first attenuation matching circuit.

[0025] The output of the first power divider circuit includes a first reference signal output and a second reference signal output. The first reference signal output is connected to the input of the frequency multiplication and synthesis circuit, and the second reference signal output is connected to the input of the phase-locked loop synthesis circuit.

[0026] The second output of the coupling circuit is connected to the input of the comparator circuit via a second attenuation circuit and a detection circuit. The output of the comparator circuit is connected to the signal monitoring terminal. The coupling circuit can be implemented using a coupler.

[0027] Figure 2In this circuit, a 100MHz clock signal is generated by a temperature-controlled crystal oscillator U1 as a reference. This signal is coupled through a coupling circuit U2, and then fed into a detector circuit U6 after passing through a first attenuation matching circuit U5. The detector circuit has a built-in detector diode, which detects the signal and generates a voltage signal. This voltage signal is then fed into a comparator circuit U7. After comparison, the comparator circuit U7 outputs a TTL voltage signal. When the output power of the 100MHz signal is ≥0dBm, the comparator output is high; when the output power is <0dBm, the comparator output is low. This TTL comparator output signal is then input to the signal monitoring terminal of the logic control circuit for monitoring. The 100MHz signal directly output from the coupling circuit U2 undergoes impedance matching through a first attenuation matching circuit U3, and then is fed into a first power divider circuit U4 for signal splitting. The power is then divided into two equal-amplitude, in-phase 100MHz crystal oscillator signals as reference signals (i.e., the first reference signal and the second reference signal), which are used by the frequency multiplication synthesis circuit and the phase-locked loop synthesis circuit.

[0028] In this embodiment, the frequency multiplication synthesis circuit uses the input 100MHz crystal oscillator signal as the reference signal, performs 10-fold frequency multiplication through the frequency multiplication diode in the circuit, outputs a 1000MHz ultra-low phase noise fixed frequency signal, and then filters out noise through a narrowband filter to obtain a clean output signal. This output signal is used as the input of the local oscillator of the mixer in the frequency mixing synthesis circuit.

[0029] Specifically, refer to Figure 3 As shown, the frequency multiplier circuit includes, in sequence, a first power adjustment circuit, a first amplifier circuit, a pre-amplifier matching circuit, a frequency multiplier diode, a post-amplifier matching circuit, a second power adjustment circuit, a first filter circuit, a second amplifier circuit, a second filter circuit, and a third attenuation matching circuit (corresponding to...). Figure 3 (U8~U17 in the series). The input terminal of the first power adjustment circuit is connected to the output terminal of the first reference signal, and the output terminal of the third attenuation matching circuit is connected to the local oscillator terminal of the mixing and synthesis circuit, inputting the frequency multiplication and synthesis point frequency signal to the local oscillator terminal of the mixing and synthesis circuit.

[0030] The first and second amplifier circuits can be implemented using amplifiers, and the first and second filter circuits can be implemented using filters.

[0031] In this embodiment, the frequency multiplier circuit is used to generate and filter 100MHz harmonics. Its main components are the frequency multiplier diode U11 and the second amplifier circuit (corresponding to the amplifier), first filter circuit, and second filter circuit (corresponding to the filter) connected after the frequency multiplier diode. The frequency multiplier circuit takes the 100MHz first reference signal output from the first reference signal output terminal of the signal generation power divider circuit and performs signal power adjustment and signal amplification through the first power adjustment circuit U8 and the first amplifier circuit U9 to ensure that the power of the 10-fold frequency multiplier circuit composed of the input pre-stage matching circuit U10, the frequency multiplier diode U11, and the post-stage matching circuit U12 is at the most suitable power value. Then, the output power is adjusted by the first power adjustment circuit U13 and the second amplifier circuit U15. The first filter circuit U14 initially filters out unwanted harmonic components, and the second filter circuit U16 further filters out unwanted harmonic components as well as the harmonic components generated by the second amplifier circuit U15. Finally, the third matching attenuation circuit U17 provides impedance matching for the output port, ensuring that the entire frequency multiplier circuit operates in the optimal matching state.

[0032] The pre-stage matching circuit U10 of the frequency multiplier diode provides excitation energy to the frequency multiplier diode circuit U11, generating an AC voltage to excite the frequency multiplier diode U11 to produce harmonics. The pre-stage matching circuit U10 consists of a capacitor, an inductor, and a resistor.

[0033] The frequency multiplier diode U11 can be either a step recovery diode or a varactor diode, which can generate rich harmonic components under a suitable excitation voltage to output the desired harmonic frequency. The subsequent matching circuit U12 of the frequency multiplier diode consists of a 1 / 4 wavelength microstrip line and a coupling capacitor, which allows the frequency multiplier diode U11 to be tuned to a frequency that is multiplied by 10, maximizing the power of the 10th harmonic output of the frequency multiplier diode U11, reducing the power of other harmonics, and maximizing the frequency multiplication efficiency.

[0034] In this embodiment, the phase-locked loop synthesis circuit uses the input 100MHz crystal oscillator signal (i.e., the second reference signal) as the reference signal of the phase-locked loop loop, and synthesizes a frequency-hopping signal of 650~755MHz through the phase-locked loop. The frequency jump of the output signal is controlled by the logic control circuit, and then the harmonics are suppressed by the low-pass filter to obtain a clean output signal. This output signal is used as the intermediate frequency input of the mixer of the frequency mixing synthesis circuit.

[0035] Reference Figure 4 As shown, the phase-locked loop synthesis circuit includes a third power adjustment circuit, a phase-locked loop circuit, a third filter circuit, and a loop filter circuit (corresponding to...). Figure 4 (U18~U21 in the series). The phase-locked loop circuit has a first signal input terminal and a second signal input terminal, and the second signal input terminal is connected to the frequency hopping control terminal; The input terminal of the third power adjustment circuit is connected to the output terminal of the second reference signal, and the output terminal of the third power adjustment circuit is connected to the first signal input terminal of the phase-locked loop circuit. The first output terminal of the phase-locked loop circuit is connected to the input terminal of the loop filter circuit, and the output terminal of the loop filter circuit is connected to the control voltage input terminal of the phase-locked loop circuit. The second output of the phase-locked loop circuit is connected to the intermediate frequency terminal of the mixer-synthesizer circuit via the third filter circuit, and the phase-locked loop synthesized frequency hopping signal is input to the mixer-synthesizer circuit.

[0036] Specifically, the phase-locked loop (PLL) circuit U19 includes a PLL, which internally consists of a phase detector (PD), a voltage-controlled oscillator (VCO), and a frequency divider. A PLL is a closed-loop control system that achieves phase synchronization between the output signal and the reference signal through negative phase feedback. Its core function is to ensure that the frequency and phase of the output signal accurately track the input reference signal. The specific circuit structure and working principle can be found in existing PLL circuit structures, and will not be elaborated further in this embodiment.

[0037] Specifically, the phase-locked loop (PLL) synthesizer circuit generates a frequency-hopping signal in the 650-755MHz range. Its core is the PLL circuit U19. The PLL synthesizer circuit takes the input 100MHz reference signal (i.e., the second reference signal) and adjusts it via the third power adjustment circuit U18 to ensure the signal power value input to the PLL circuit U19 meets operational requirements. The PLL circuit U19 uses the input 100MHz reference signal as its reference and controls the values ​​of its internal frequency divider, phase detector, and other registers through logic control circuits. The PLL itself employs fractional-order frequency division technology to control the required synthesized output frequency. The loop filter circuit U21 works with the PLL circuit U19 to adjust the phase noise of the PLL output signal. A reasonable loop bandwidth ensures stable and reliable PLL output. The third filter circuit U20 filters out high-order harmonics in the PLL output signal, reducing spurious signals in the final output after mixing.

[0038] In this embodiment, the mixing synthesis circuit uses the signal output from the frequency multiplier synthesis circuit as the local oscillator input of the mixer in this mixing circuit, and uses the signal output from the phase-locked loop synthesis circuit as the intermediate frequency input of the mixer, thereby performing up-conversion through the mixer in the mixing synthesis circuit. (Refer to...) Figure 5 As shown, the mixing and synthesis circuit of this embodiment includes a fourth power adjustment circuit, a fifth power adjustment circuit, a mixing circuit, and a fourth attenuation matching circuit (i.e., corresponding to...). Figure 5 (China U22~U25). Among them, The input terminal of the fourth power adjustment circuit is connected to the output terminal of the third attenuation matching circuit, and the output terminal of the fourth power adjustment circuit is connected to the local oscillator terminal of the mixer circuit.

[0039] The input of the fifth power adjustment circuit is connected to the output of the third filter circuit, and the output of the fifth power adjustment circuit is connected to the intermediate frequency terminal of the mixer circuit.

[0040] The output of the mixer circuit is connected to the input of the signal conditioning power divider circuit via the fourth attenuation matching circuit.

[0041] Specifically, the mixing circuit is a mixer. The mixer is a double-balanced mixer, which outputs a signal of 1000±650~755MHz. The output signal is then filtered by a signal conditioning power divider circuit to obtain a signal of 1650~1755MHz, achieving the effects of low spurious emissions, low phase noise, and frequency hopping output.

[0042] Specifically, the mixing and synthesis circuit adjusts the power of the two initial synthesis signals (i.e., the frequency multiplication synthesis point frequency signal and the phase-locked loop synthesis frequency hopping signal) to the required power level for mixing through the power adjustment circuits U22 and U25, respectively. After mixing by the mixing circuit U23, the required 1650~1755MHz signal is output. Finally, the fourth attenuation matching circuit U24 matches the mixer output port to the optimal impedance and outputs the mixed synthesis frequency hopping signal.

[0043] In this embodiment, a 10-fold frequency multiplication + phase-locked loop method is used to mix and output a synthesized signal. This reduces the output phase noise compared to a single phase-locked loop technology and also meets the frequency hopping requirements compared to a single frequency multiplication synthesis technology.

[0044] In this embodiment, the signal conditioning power divider circuit is mainly used to condition the signal output from the mixer-synthesizer circuit through filtering, amplification, attenuation matching, etc., and then output two synthesized signals of equal amplitude and in phase through a 1-to-2 power divider. (Refer to...) Figure 6 As shown, the signal conditioning power divider circuit includes a fourth filter circuit, a third amplifier circuit, an equalization circuit, a fifth attenuation matching circuit, a second power divider circuit, a sixth attenuation matching circuit, a seventh attenuation matching circuit, a fifth filter circuit, and a sixth filter circuit (i.e., corresponding to...). Figure 6 (China U26~U34). Among them, The input of the fourth filter circuit is connected to the output of the fourth attenuation matching circuit. The output of the fourth filter circuit is then connected to the input of the second power divider circuit via the third amplifier circuit, the equalization circuit, and the fifth attenuation matching circuit. The second power divider circuit is specifically a 1-to-2 power divider circuit, used to divide the signal into two equal-amplitude, in-phase signals, and can be implemented using a 1-to-2 power divider. The fifth and sixth filter circuits can be implemented using narrowband bandpass filters.

[0045] The first output of the second power divider circuit is connected to the input of the fifth filter circuit via the sixth attenuation matching circuit. The output of the fifth filter circuit is used to output the first frequency hopping synthesized signal.

[0046] The second output of the second power divider circuit is connected to the input of the sixth filter circuit via the seventh attenuation matching circuit. The output of the sixth filter circuit is used to output the second frequency hopping synthesized signal.

[0047] Specifically, the mixed-synthesized frequency-hopping signal, after mixing, contains not only the desired output signal but also higher harmonics and various noise signals. Therefore, the fourth filter circuit U26 is used to initially filter out unwanted noise signals, resulting in a cleaner signal spectrum. Then, the third amplifier circuit U27 and the fifth attenuation matching circuit U29 adjust the link output power to 0dBm±1dB. The equalization circuit U28 equalizes the signal amplitude within the output bandwidth, making the output signal amplitude change more smoothly. The second power divider circuit U30 splits the signal into two equal-amplitude, in-phase paths. The sixth and seventh attenuation matching circuits U31 and U33 match the impedances of the two output ports of the second power divider circuit U30 to the optimal impedance before outputting. Finally, the fifth filter circuit U32 and the sixth filter circuit U34 filter the signal again, suppressing harmonics and other noise signals, ultimately outputting a low-spurious signal spectrum, namely the two equal-amplitude, in-phase first and second frequency-hopping synthesized signals.

[0048] In this embodiment, when outputting the frequency-hopping signal, a 1-to-2 power divider is used to split the signal into two equal-amplitude, in-phase paths, facilitating simultaneous support for up-conversion and down-conversion. Both output paths have narrow-band bandpass filters and attenuation matching circuits to improve the isolation between the up-conversion and down-conversion channels.

[0049] In this embodiment, the output frequency of the thermostatic crystal oscillator in the signal generation power divider circuit is 100MHz, and the measured output phase noise can reach -160dBc / Hz@1kHz. After being multiplied 10 times by the frequency multiplier synthesis circuit, a 1000MHz point frequency signal is output. Using the phase noise degradation calculation formula 20logN (where N is the frequency multiplication number), it can be seen that after 10 frequency multiplications, the theoretical output phase noise of this signal can reach -140dBc / Hz@1kHz. However, due to the superposition degradation of the 100MHz crystal oscillator output signal by the first amplification circuit in the frequency multiplier synthesis circuit, the measured phase noise of the 1000MHz output signal can reach -130dBc / Hz@1kHz, and the harmonic and spurious output can reach -70dBc. Since this signal is a point frequency signal, there is no frequency hopping time indicator.

[0050] With an input reference frequency of 100MHz and an input reference clock phase noise of -160dBc / Hz@1kHz, the phase noise of the synthesized signal output from the phase-locked loop (PLL) can reach -125dBc / Hz@1kHz, and the frequency hopping time is ≤50us. After the synthesized signal is filtered by the third filtering circuit, the harmonic and spurious output can reach -75dBc.

[0051] The initial synthesized signals output from the frequency multiplier and phase-locked loop synthesizers are then mixed and synthesized by the frequency mixer. The resulting 1650~1755MHz signal has a phase noise as low as -125dBc / Hz@1kHz. Simultaneously, after filtering by the fourth, fifth, and sixth filter circuits, the spurious output signal reaches -65dBc, and the frequency hopping time is ≤50us. After power division by the second power divider circuit, two equal-amplitude, in-phase signals can be output.

[0052] This embodiment can achieve dual-channel equal-amplitude, in-phase output frequency-hopping signals within an output frequency range of 1650~1755MHz. It also enables fast frequency hopping (hopping time ≤50µs) with high frequency resolution. Compared to a single direct synthesis method, it achieves high-resolution frequency hopping with a simpler circuit. At an output of 0dBm, the spurious output reaches -65dBc, a 5dB reduction compared to -60dBc in a single direct synthesis method. The output phase noise is as low as -125dBc / Hz@1kHz, 7dB lower than -118dBc / Hz@1kHz in a single phase-locked loop synthesis method. This embodiment achieves hybrid synthesis output by mixing the phase-locked loop synthesized output signal and the direct analog synthesized output signal, combining the advantages of both to achieve low phase noise, low spurious emissions, low power consumption, relatively simple circuit structure, and high operating frequency. This solves the problem of contradictory performance indicators such as spurious emission suppression, frequency hopping output, and phase noise in traditional solutions.

[0053] Example 2: In this example, based on Example 1 above, the dual-output hybrid synthesis frequency hopping source device further includes a first power management circuit, used to convert the input +5.5V power supply to a +5V power supply output, providing the power required for stable operation of the aforementioned circuit. The input terminal of the first power management circuit is connected to an external power supply, and the output terminal of the first power management circuit is connected to the signal generation power divider circuit, the frequency multiplier synthesis circuit, the phase-locked loop synthesis circuit, the frequency mixer synthesis circuit, the signal conditioning power divider circuit, and the logic control circuit, respectively.

[0054] In this embodiment, the logic control circuit mainly includes components such as an FPGA controller (i.e., an FPGA chip) and memory. The logic control circuit controls the frequency hopping of the phase-locked loop synthesis circuit to achieve frequency hopping control of the final mixed-synthesized signal. It also controls the power management of the first power management circuit and monitors the crystal oscillator signal of the signal generation power divider circuit. The logic control circuit communicates with the computer via a 232 serial port and implements frequency hopping management through pre-installed host computer control software. The specific host computer control software can be configured according to actual needs, and it is not an improvement direction of this utility model; therefore, it will not be described in detail here.

[0055] Specifically, refer to Figure 7 As shown, the logic control circuit includes a clock generation circuit, an FPGA circuit, a data storage circuit, a second power management circuit, and a serial communication circuit; among which, The clock generation circuit and data storage circuit are electrically connected to the FPGA circuit; the FPGA circuit is connected to the host computer via a serial communication circuit. A π-type filter is also provided between the clock generation circuit and the FPGA circuit. The FPGA circuit specifically contains an FPGA chip.

[0056] The input terminal of the second power management circuit is connected to the output terminal of the first power management circuit. The output terminal of the second power management circuit is connected to the FPGA circuit, the clock generation circuit, and the data storage circuit, respectively, to supply power to the FPGA circuit, the clock generation circuit, and the data storage circuit.

[0057] The FPGA circuit's outputs include a frequency hopping control terminal, a signal monitoring terminal, and a power monitoring terminal. The frequency hopping control terminal outputs the phase-locked loop (PLL) control signal to control the frequency hopping of the PLL synthesis circuit. The signal monitoring terminal receives the output signal from the temperature-controlled crystal oscillator in the signal generation power divider circuit, enabling crystal oscillator detection. The power monitoring terminal is connected to the output of the first power management circuit to monitor power supply.

[0058] Specifically, the clock generation circuit U35 generates a 20MHz signal clock. After harmonics are filtered out by a first-stage π-type filter, it supplies the FPGA chip in the FPGA circuit U37 as the input clock. The second power management circuit U36 converts the input +5V voltage into +3.3V, +2.5V, and +1.2V power supply voltages required for the operation of the FPGA and logic control circuits through a set of linear regulator circuits (LDO). Both the input and output terminals of the second power management circuit are connected to filter capacitors and filter inductors to reduce power supply noise interference. The FPGA circuit U37 contains an FPGA chip, which can control all devices requiring logic control in this device, including: phase-locked loop control, power monitoring control, crystal oscillator monitoring control, serial communication control, and data storage control. The serial communication circuit U38 provides a serial communication buffer chip to ensure stable 232 serial data communication between the FPGA chip and the host computer. Since the FPGA cannot store data when power is off, the data storage circuit U39 stores the FPGA's logic program, which is automatically loaded upon power-up.

[0059] In this embodiment, the first power management circuit converts the externally input +5.5V power supply voltage into the power supply voltage required for the operation of this device through voltage regulation, filtering, and other processing. The first power management circuit provides one +5.5V voltage output, one +5V voltage output, and one +3.3V voltage output. Specifically, the first power management circuit includes a first power supply branch, a second power supply branch, and a third power supply branch. (Refer to...) Figure 8 As shown, the first power supply branch includes a first common-mode inductor (i.e., ...) connected in sequence. Figure 8 LF1) and the first output filter capacitor (i.e. Figure 8 In the circuit diagram, C1 is a +5.5V output filter capacitor. The input terminal of the first common-mode inductor is connected to an external power supply, and the output terminal of the first output filter capacitor is connected to the signal generation power divider circuit and the frequency multiplier circuit. Specifically, C1 is a +5.5V output filter capacitor, which supplies power to the frequency multiplier circuit and the signal generation power divider circuit.

[0060] Reference Figure 9 As shown, the second power supply branch includes a second common-mode inductor connected in sequence (i.e., Figure 9 LF2), the first input filter capacitor (i.e. Figure 9 C11 in the middle), the second input filter capacitor (i.e. Figure 9 C15 in the middle), the first voltage conversion chip (i.e. Figure 9 U40 in the middle), the first voltage divider feedback resistor (i.e. Figure 9 R9 and R10 in the middle), the second output filter capacitor (i.e. Figure 9 C12 in the middle), the third output filter capacitor (i.e. Figure 9 C13) and the fourth output filter capacitor (i.e. Figure 9(C14 in the diagram). The input terminal of the second common-mode inductor is connected to an external power supply, and the output terminal of the fourth output filter capacitor is connected to a phase-locked loop synthesis circuit.

[0061] Figure 9 In this circuit, the first voltage conversion chip, U40, is a +3.3V voltage conversion chip. This chip is packaged in a 5-pin DD plastic package, providing a large heat dissipation area, which effectively reduces the temperature rise during power conversion and extends the product's lifespan. Filter capacitors C11 and C15 are input filter capacitors, while filter capacitors C12, C13, and C14 are output filter capacitors, effectively filtering out power supply noise. Resistors R9 and R10 are voltage divider feedback resistors; the feedback voltage obtained from their voltage division allows the first voltage conversion chip U40 to stably output a +3.3V voltage, powering the phase-locked loop circuit.

[0062] Reference Figure 10 As shown, the third power supply branch includes a third common-mode inductor (i.e. Figure 10 LF2), the third input filter capacitor (i.e. Figure 10 C23 in the middle), the fourth input filter capacitor (i.e. Figure 10 C27 in the middle), the second voltage conversion chip (i.e. Figure 10 U41 in the middle), the second voltage divider feedback resistor (i.e. Figure 10 R4 and R5 in the middle), the fourth output filter capacitor (i.e. Figure 10 C24 in the middle), the fifth output filter capacitor (i.e. Figure 10 C25 in the middle), the sixth output filter capacitor (i.e. Figure 10 C26 in the middle) and power supply filter inductor (i.e. Figure 10 (L3 in the diagram). The input of the third common-mode inductor is connected to an external power supply, and the output of the power supply filter inductor is connected to the logic control circuit, the first amplifier, the second amplifier, and the third amplifier.

[0063] Figure 10 In this circuit, the second voltage conversion chip U41 is a +5V voltage conversion chip. It is packaged in an 8-pin SO plastic package, resulting in a small chip size and saving printed circuit space. Filter capacitors C23 and C27 are input filter capacitors, while C24, C25, and C26 are output filter capacitors, effectively filtering out power supply noise. The power supply filter inductor L3 prevents interference signals from crossing over into the power supply circuit. Resistors R4 and R5 are voltage divider feedback resistors; the feedback voltage obtained from their voltage division allows the second voltage conversion chip U41 to stably output a +5V voltage, powering the FPGA circuit and various amplifier circuits.

[0064] In this embodiment, the first common-mode inductor, the second common-mode inductor, and the third common-mode inductor are all 10mH common-mode inductors, which can effectively suppress noise signals at the power input and prevent interference to sensitive components in the device. The filter capacitors in each power supply branch are all aluminum electrolytic capacitors, which can effectively filter out low-frequency ripple and provide a stable power supply environment for the circuit.

[0065] In this embodiment, a common-mode inductor and aluminum electrolytic capacitor are used for filtering and interference suppression in the power management circuit. Compared with traditional capacitor and ferrite bead filters or single ceramic capacitor filters, the low-frequency interference suppression is improved by 30dBc.

[0066] Example 3: In this example, based on Examples 1 and 2 above, and referring to... Figures 11-13 This embodiment also provides a pluggable chassis for installing the aforementioned circuitry. The chassis and its cover are both made of aluminum alloy. The cover includes an outer cover and an inner cover, both of which are coated using a natural conductive anodizing process. The chassis body is coated using an overall nickel plating process, resulting in a bright silver color. The overall form is a pluggable chassis module. The inner and outer covers are sealed with screws, and the chassis has two locating pins and two pull-out aids. Figure 11 In the middle, there are protruding guide rails on both the top and bottom of the cabinet, which work together with the whole machine cabinet to complete the push and pull action. Figure 12 The enclosure features one CPCI low-frequency power supply control interface and two BMA-type RF coaxial interfaces. Figure 13 In the middle, the side of the enclosure has a separate front panel, which contains two fault indicator lights and corresponding black characters silkscreened on the front panel, such as frequency synthesizer module.

[0067] The pluggable chassis in this embodiment adopts a modular design. The connector interface used in the chassis is a combination of CPCI connectors and BMA connectors to meet the requirements of quick plugging and unplugging. Compared with the traditional single integrated connector, it reduces costs, and the distributed connectors increase the redundancy of the design layout.

[0068] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above description is only a specific embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A dual-output hybrid synthesis frequency hopping source device, characterized in that: This includes signal generation and power division circuits, frequency multiplication and synthesis circuits, phase-locked loop synthesis circuits, frequency mixer synthesis circuits, signal conditioning and power division circuits, and logic control circuits; among them, The signal generation and splitting circuit is provided with a first reference signal output terminal and a second reference signal output terminal; the first reference signal output terminal is connected to the local oscillator terminal of the mixing and synthesizing circuit via a frequency multiplication and synthesis circuit; the second reference signal output terminal is connected to the intermediate frequency terminal of the mixing and synthesizing circuit via a phase-locked loop synthesis circuit. The output terminal of the mixing and synthesizing circuit is connected to the input terminal of the signal conditioning and power dividing circuit, and the output terminal of the signal conditioning and power dividing circuit is used to power divide and output the first frequency hopping synthesized signal and the first frequency hopping synthesized signal. The logic control circuit has a frequency hopping control terminal and a signal monitoring terminal. The frequency hopping control terminal is connected to a phase-locked loop synthesis circuit, and the signal monitoring terminal is connected to a signal generation and division circuit.

2. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The signal generation and power division circuit includes a temperature-controlled crystal oscillator, a coupling circuit, a first attenuation matching circuit, a first power divider circuit, a second attenuation matching circuit, a detector circuit, and a comparator circuit; wherein, The output terminal of the thermostatic crystal oscillator is connected to the input terminal of the coupling circuit, and the first output terminal of the coupling circuit is connected to the input terminal of the first power divider circuit via the first attenuation matching circuit. The output of the first power divider circuit includes a first reference signal output and a second reference signal output. The first reference signal output is connected to the input of the frequency multiplication and synthesis circuit, and the second reference signal output is connected to the input of the phase-locked loop synthesis circuit. The second output terminal of the coupling circuit is connected to the input terminal of the comparator circuit via the second attenuation circuit and the detection circuit in sequence, and the output terminal of the comparator circuit is connected to the signal monitoring terminal.

3. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The frequency multiplier circuit comprises, in sequence, a first power adjustment circuit, a first amplifier circuit, a pre-stage matching circuit, a frequency multiplier diode, a post-stage matching circuit, a second power adjustment circuit, a first filter circuit, a second amplifier circuit, a second filter circuit, and a third attenuation matching circuit; wherein... The input terminal of the first power adjustment circuit is connected to the output terminal of the first reference signal, and the output terminal of the third attenuation matching circuit is connected to the local oscillator terminal of the mixing and synthesis circuit.

4. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The phase-locked loop synthesis circuit includes a third power adjustment circuit, a phase-locked loop circuit, a third filter circuit, and a loop filter circuit; wherein... The phase-locked loop circuit has a first signal input terminal and a second signal input terminal, and the second signal input terminal is connected to the frequency hopping control terminal. The input terminal of the third power adjustment circuit is connected to the output terminal of the second reference signal, and the output terminal of the third power adjustment circuit is connected to the first signal input terminal of the phase-locked loop circuit. The first output terminal of the phase-locked loop is connected to the input terminal of the loop filter circuit, and the output terminal of the loop filter circuit is connected to the control voltage input terminal of the phase-locked loop circuit. The second output terminal of the phase-locked loop circuit is connected to the intermediate frequency terminal of the mixer-synthesizer circuit via a third filter circuit.

5. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The mixing and synthesis circuit includes a fourth power adjustment circuit, a fifth power adjustment circuit, a mixing circuit, and a fourth attenuation matching circuit; wherein... The input terminal of the fourth power adjustment circuit is connected to the output terminal of the third attenuation matching circuit, and the output terminal of the fourth power adjustment circuit is connected to the local oscillator terminal of the mixer circuit. The input terminal of the fifth power adjustment circuit is connected to the output terminal of the third filter circuit, and the output terminal of the fifth power adjustment circuit is connected to the intermediate frequency terminal of the mixer circuit. The output of the mixer circuit is connected to the input of the signal conditioning power divider circuit via a fourth attenuation matching circuit.

6. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The signal conditioning power divider circuit includes a fourth filter circuit, a third amplifier circuit, an equalization circuit, a fifth attenuation matching circuit, a second power divider circuit, a sixth attenuation matching circuit, a seventh attenuation matching circuit, a fifth filter circuit, and a sixth filter circuit. The input terminal of the fourth filter circuit is connected to the output terminal of the fourth attenuation matching circuit, and the output terminal of the fourth filter circuit is connected to the input terminal of the second power divider circuit in sequence through the third amplifier circuit, the equalization circuit, and the fifth attenuation matching circuit. The first output of the second power divider circuit is connected to the input of the fifth filter circuit via the sixth attenuation matching circuit. The output of the fifth filter circuit is used to output the first frequency hopping synthesized signal. The second output of the second power divider circuit is connected to the input of the sixth filter circuit via the seventh attenuation matching circuit. The output of the sixth filter circuit is used to output the second frequency hopping synthesized signal.

7. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: It also includes a first power management circuit; wherein the input terminal of the first power management circuit is connected to an external power supply, and the output terminal of the first power management circuit is connected to a signal generation power divider circuit, a frequency multiplier synthesis circuit, a phase-locked loop synthesis circuit, a frequency mixer synthesis circuit, a signal conditioning power divider circuit, and a logic control circuit, respectively.

8. The dual-output hybrid synthesis frequency hopping source device according to claim 1, characterized in that: The logic control circuit includes a clock generation circuit, an FPGA circuit, a data storage circuit, a second power management circuit, and a serial communication circuit; wherein, The clock generation circuit and data storage circuit are electrically connected to the FPGA circuit; the FPGA circuit is connected to the host computer via a serial communication circuit. The input terminal of the second power management circuit is connected to the output terminal of the first power management circuit, and the output terminal of the second power management circuit is connected to the FPGA circuit, the clock generation circuit, and the data storage circuit, respectively. The output terminal of the FPGA circuit includes a frequency hopping control terminal, a signal monitoring terminal, and a power monitoring terminal. The frequency hopping control terminal is used to output a phase-locked loop control signal, the signal monitoring terminal is used to receive the output signal of the temperature-controlled crystal oscillator, and the power monitoring terminal is connected to the output terminal of the first power management circuit.

9. The dual-output hybrid synthesis frequency hopping source device according to claim 7, characterized in that: The first power management circuit includes a first power supply branch, a second power supply branch, and a third power supply branch; wherein, the first power supply branch includes a first common-mode inductor and a first output filter capacitor connected in sequence; the input terminal of the first common-mode inductor is connected to an external power supply, and the output terminal of the first output filter capacitor is connected to a signal generation and splitting circuit and a frequency multiplier and synthesizer circuit; The second power supply branch includes a second common-mode inductor, a first input filter capacitor, a second input filter capacitor, a first voltage conversion chip, a first voltage divider feedback resistor, a second output filter capacitor, a third output filter capacitor, and a fourth output filter capacitor connected in sequence; the input terminal of the second common-mode inductor is connected to an external power supply, and the output terminal of the fourth output filter capacitor is connected to a phase-locked loop synthesis circuit. The third power supply branch includes a third common-mode inductor, a third input filter capacitor, a fourth input filter capacitor, a second voltage conversion chip, a second voltage divider feedback resistor, a fourth output filter capacitor, a fifth output filter capacitor, a sixth output filter capacitor, and a power supply filter inductor; the input terminal of the third common-mode inductor is connected to an external power supply, and the output terminal of the power supply filter inductor is connected to a logic control circuit, a first amplifier, a second amplifier, and a third amplifier.

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