Bit line switch circuit, pixel array circuit, image sensor, and camera
Patent Information
- Application Number
- CN202521333469.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2026-08-18
- Estimated Expiration
- 2035-06-26
AI Technical Summary
[0004]但是现有的技术中，无论擦除模式的正高压还是编程模式的负电压传进读出电路，都会导致器件产生过压问题
[0017]本实用新型处于读出模式时，位线开关打开，像素器件上电压正常传输至读出电路，由读出电路转换成与曝光有关的图像信号；当处于编程模式或擦除模式时，位线开关断开，像素器件上电压无法传输至读出电路，实现位线电压和读出电路电压的有效隔离，本实用新型有效的解决了现有相机内的图像传感器在编辑和擦除模式的工作过程中，读出电路会过压损坏的问题。
Smart Images
Figure CN224653594U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of image sensors and cameras, and in particular to a bit line switch circuit, a pixel array circuit, an image sensor, and a camera. Background Technology
[0002] Image sensors are optoelectronic imaging devices widely used in machine vision, target reconnaissance, security monitoring, and medical testing. With the widespread application of large-scale pixel arrays, the market has placed higher demands on the performance of imaging devices.
[0003] The floating grid sensor is an innovative image sensing technology. Its pixel unit borrows the principle of fast flash memory. Under specific voltage conditions, the pixel threshold voltage can be increased as a whole through programming mode or decreased as a whole through erasure mode. By programming and erasing operations, the pixel threshold voltage consistency is achieved, thereby improving image quality.
[0004] However, in existing technologies, whether the positive high voltage of the erase mode or the negative voltage of the programming mode is transmitted into the readout circuit, it will cause the device to have an overvoltage problem. Utility Model Content
[0005] Therefore, the technical problem to be solved by this utility model is that the readout circuit will be damaged by overvoltage during the operation of the editing and erasing modes in the prior art.
[0006] The above-mentioned technical problem is solved by the following technical solution: a bit line switching circuit, comprising a high voltage domain including a first deep N-well high-voltage transistor and a second deep N-well high-voltage transistor connected to each other, the first deep N-well high-voltage transistor being connected to a readout circuit, and the second deep N-well high-voltage transistor being connected to a pixel unit; a low voltage domain including a first PMOS transistor and a second PMOS transistor connected in series, the first PMOS transistor being connected to the first deep N-well high-voltage transistor; and a control signal terminal including a Prog_Mode signal terminal and a Select signal terminal, the gate of the second PMOS transistor being connected to the Prog_Mode signal terminal, and the Select signal terminal being connected to the drain of the second PMOS transistor through a buffer.
[0007] In a preferred embodiment of the bit line switch circuit of this utility model: the gate of the first PMOS transistor is grounded through resistor R0, and the source of the first PMOS transistor is connected to the gate of the first deep N-well high voltage transistor.
[0008] In a preferred embodiment of the bit-line switch circuit of this utility model: the drain of the second PMOS transistor is connected to the output terminal of the buffer, and the input terminal of the buffer is connected to the Select signal.
[0009] In a preferred embodiment of the bit line switch circuit of this utility model: the deep N-well ports DNW of the first deep N-well high-voltage transistor and the second deep N-well high-voltage transistor are connected to a positive low voltage, and the chip substrate where the first deep N-well high-voltage transistor and the second deep N-well high-voltage transistor are located is grounded at voltage VSS.
[0010] In a preferred embodiment of the bit-line switch circuit of this utility model: the gate of the first deep N-well high-voltage transistor is connected to the Select signal, and the gate of the second deep N-well high-voltage transistor is connected to the Prog_Mode signal.
[0011] To address the aforementioned problems, this utility model also proposes the following technical solution: a pixel array circuit, comprising the aforementioned bit line switch circuit, and a pixel array comprising several independently configured pixel units, each pixel unit being connected to a bit line and a word line; several sets of bit line switch circuits, respectively connected between each bit line and the readout circuit; and a pixel array substrate electrically connected to the pixel units.
[0012] In a preferred embodiment of the pixel array circuit of this utility model: the pixel array substrate is also connected to the power supply port of the power supply unit. The pixel array substrate is connected to a negative voltage in programming mode and to a positive high voltage in erasing mode; the bit line switch circuit is used to control the on / off connection between the pixel array and the readout circuit.
[0013] In a preferred embodiment of the pixel array circuit of this utility model: several groups of pixel units connected to each bit line are connected to at least one group of pixel array substrates simultaneously.
[0014] This utility model also provides the following technical solution: an image sensor, which includes the above-mentioned pixel array circuit.
[0015] This utility model also provides the following technical solution: a camera, which includes the above-mentioned image sensor.
[0016] The beneficial effects of this utility model are as follows:
[0017] When the present invention is in readout mode, the bit line switch is open, and the voltage on the pixel device is normally transmitted to the readout circuit, which converts it into an image signal related to exposure. When in programming or erase mode, the bit line switch is open, and the voltage on the pixel device cannot be transmitted to the readout circuit, thus achieving effective isolation between the bit line voltage and the readout circuit voltage. The present invention effectively solves the problem of overvoltage damage to the readout circuit of the image sensor in existing cameras during the operation of editing and erase modes. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings of the embodiments of this utility model will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this utility model and are not intended to limit the scope of this utility model. Wherein:
[0019] Figure 1 The specific structural diagram of the bit line switch circuit is shown;
[0020] Figure 2 The overall structure of the bit line switch circuit and pixel array circuit is shown. Detailed Implementation
[0021] To enable those skilled in the art to better understand this utility model, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0022] The terminology used in this invention refers to those general terms currently widely used in the art in consideration of the functionality of this invention; however, these terms may vary according to the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this invention. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this invention.
[0023] Reference Figure 1 This embodiment provides a bit line switch circuit, which includes a high voltage domain 100, including a first deep N-well high voltage transistor NM0 and a second deep N-well high voltage transistor NM1 connected to each other. The first deep N-well high voltage transistor NM0 is connected to the readout circuit, and the second deep N-well high voltage transistor NM1 is connected to the pixel unit.
[0024] The low voltage domain 200 includes a first PMOS transistor PM2 and a second PMOS transistor PM3 connected in series, with the first PMOS transistor PM2 connected to a first deep N-well high voltage transistor NM0.
[0025] The control signal terminal 300 includes a Prog_Mode signal terminal and a Select signal terminal. The gate of the second PMOS transistor PM3 is connected to the Prog_Mode signal terminal, and the Select signal terminal is connected to the drain of the second PMOS transistor PM3 through a buffer.
[0026] Specifically, the gate of the first PMOS transistor PM2 is grounded through resistor R0, and the source of the first PMOS transistor PM2 is connected to the gate of the first deep N-well high-voltage transistor NM0.
[0027] The drain of the second PMOS transistor PM3 is connected to the output of the buffer, as shown in the reference. Figure 1In this context, Buffer represents a buffer, and the input of the buffer is connected to the Select signal.
[0028] The deep N-well ports DNW of the first deep N-well high-voltage transistor NM0 and the second deep N-well high-voltage transistor NM1 are connected to a positive low voltage, and the chip substrate where the first deep N-well high-voltage transistor NM0 and the second deep N-well high-voltage transistor NM1 are located is grounded at voltage VSS.
[0029] The gate of the first deep N-well high-voltage transistor NM0 is connected to the Select signal, and the gate of the second deep N-well high-voltage transistor NM1 is connected to the Prog_Mode signal.
[0030] Furthermore, this solution performs the following actions when in programming mode, erase mode, and read mode:
[0031] 1. Programming Mode: In this mode, the pixel unit needs to be programmed. At this time, the P-well substrate voltage (VSUB) is set to negative, the Prog_Mode signal is high, the Select signal is low, and the gate of the second PMOS transistor PM3 is high to ensure that PM3 is cut off.
[0032] At this time, the second deep N-well high-voltage transistor NM1 is turned on, the gate of the first deep N-well high-voltage transistor NM0 is pulled low, and the first deep N-well high-voltage transistor NM0 is turned off. (Refer to...) Figure 1 The signal is transmitted from end B to end A, but due to the combination of the on and off states of the first deep N-well high-voltage tube NM0 and the second deep N-well high-voltage tube NM1, the signal cannot be transmitted to the readout circuit, thus protecting the readout circuit.
[0033] 2. Erase Mode: In erase mode, the pixel unit is erased. VSUB is set to positive high voltage, the Prog_Mode signal is low, and the Select signal is also low. The second deep N-well high-voltage transistor NM1 and the first PMOS transistor PM2 are kept on because their gates are grounded through resistor R0. The second PMOS transistor PM3 is turned on because its gate is connected to the low level of the Prog_Mode signal.
[0034] At this time, current flows from the pixel unit to the bit line (BL), but due to the combination of the cut-off and conduction states of the first deep N-well high-voltage transistor NM0 and the second deep N-well high-voltage transistor NM1, the signal cannot be transmitted to the readout circuit, thus avoiding damage to the readout circuit.
[0035] 3. Readout Mode: In readout mode, the signal in the pixel unit needs to be read out to the readout circuit. At this time, VSUB is grounded, the Prog_Mode signal is low, and the Select signal is high. The first PMOS transistor PM2 is turned on, and the second PMOS transistor PM3 is also turned on under the influence of the low Prog_Mode signal. The high-level Select signal is transmitted to the first deep N-well high-voltage transistor NM0, causing NM0 to turn on and NM1 to turn off. Current flows from the pixel unit through the bit line switch to the readout circuit. The readout circuit receives the signal and converts it into an image signal, completing the signal reading.
[0036] Reference Figure 1 and Figure 2 In order to better apply the above-mentioned bit line switching circuit to image sensors, this utility model also provides the following technical solution: a pixel array circuit, which includes the above-mentioned bit line switching circuit, and also includes a pixel array 400, which includes several groups of independently configured pixel units VPS, and each pixel unit VPS is connected to the bit line BL and the word line WL.
[0037] Specifically, several sets of bit line switch circuits are connected between each bit line BL and the readout circuit, as shown in the reference. Figure 2 In this context, readout refers to the readout circuit, and BL Switch refers to the bit line switch.
[0038] The pixel array substrate PW is electrically connected to the pixel unit VPS, as shown in the reference. Figure 2 PW0, PW1, PW2, PW3, PW4...
[0039] The pixel array substrate PW is also connected to the power supply port of the power supply unit. The pixel array substrate PW is connected to a negative voltage in programming mode and to a positive high voltage in erasing mode. The bit line switch circuit is used to control the on / off connection between the pixel array 400 and the readout circuit.
[0040] The output voltage of the power supply unit can be adjusted according to different modes.
[0041] In programming mode: the pixel array substrate PW is connected to -3V, and the positive high voltage of the word line WL turns on the pixel unit VPS.
[0042] Erasure mode: The pixel array substrate PW is connected to 10V, and the word line WL is negatively voltaged to turn on the parasitic diode.
[0043] Readout mode: Pixel array substrate PW connected to 0V, normal signal transmission state.
[0044] The bit line switch circuit is used to control the connection and disconnection between the pixel array 400 and the readout circuit.
[0045] The gate of the pixel unit VPS is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the source line SL.
[0046] The drain of the pixel unit VPS is connected to the bit line BL, the bit line BL is connected to the bit line switch, and the bit line switch is connected to the readout circuit.
[0047] Specifically, the pixel array circuit consists of multiple pixel units (VPS), as shown in the reference. Figure 2 VPS0, VPS1, VPS2, VPS3, VPS4... in the diagram, each pixel unit VPS contains a transistor used to read control signals.
[0048] The gate of a pixel unit (VPS) is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the source line SL. The bit line BL is connected to the drain of each column of pixel units (VPS) to transmit signals from the pixel units (VPS) to the readout circuit. A bit line switch is connected between the bit line BL and the readout circuit to control whether signals are transmitted to the bit line BL.
[0049] In summary, based on the reference Figure 1 and Figure 2 In programming mode, a positive voltage, typically around 10V, is applied to the word line WL, while a negative voltage, typically around -3V, is applied to all source lines SL and the pixel array substrate PW.
[0050] Each bit line BL connects to at least one set of pixel units VPS, which are simultaneously connected to a set of pixel array substrates PW to avoid mutual interference.
[0051] In pixel array 400, the gate of the pixel cell VPS in each row is connected to the word line WL of that row, while the source is connected to the source line SL. When a positive high voltage is applied to the word line WL, the pixel cell VPS transistor will turn on. After the pixel cell VPS transistor is turned on, the voltage on the source line SL is transmitted to the drain of the pixel cell VPS, i.e., the bit line BL.
[0052] At this time, the P-well substrate voltage VSUB in the bit line switch circuit will be set to a negative voltage, the Prog_Mode signal will become high level, and the gate of the second PMOS transistor PM3 will be connected to Prog_Mode at a high level. This will cause the second PMOS transistor PM3 to turn off, the second deep N-well high voltage transistor NM1 to turn on, and the gate of the first deep N-well high voltage transistor NM0 to be pulled down to a negative voltage, thus turning it off. As a result of this setting, current cannot flow from the pixel array 400 to the readout circuit, thereby protecting the readout circuit from the influence of high voltage.
[0053] Furthermore, when in erase mode, a positive voltage is applied to the pixel array substrate PW, while a negative voltage is applied to the word line WL.
[0054] At this time, the parasitic diode between the drain of the pixel unit VPS and the pixel array substrate PW is forward biased, and the positive high voltage on the pixel array substrate PW reduces the voltage drop of the parasitic diode and transmits it to the bit line BL.
[0055] Meanwhile, in the bit line switching circuit, the P-well substrate voltage VSUB is grounded, and both the Prog_Mode and Select signals are set to low level. This turns off the second deep N-well high-voltage transistor NM1, keeps the first PMOS transistor PM2 normally open, turns on the second PMOS transistor PM3, and pulls the gate of the first deep N-well high-voltage transistor NM0 low to turn it off. This state blocks the path of current from the pixel array 400 to the readout circuit.
[0056] Furthermore, in readout mode, the bit line switch is turned on, allowing signals from the pixel unit VPS to flow through the bit line BL to the readout circuit. At this time, the P-well substrate voltage VSUB in the bit line switch circuit is grounded, the Prog_Mode signal is low, and the Select signal is high. Both the first PMOS transistor PM2 and the second PMOS transistor PM3 are turned on, the first deep N-well high-voltage transistor NM0 is turned on, and the second deep N-well high-voltage transistor NM1 is turned off. Thus, current can flow smoothly from the pixel array through the bit line switch to the readout circuit. The readout circuit receives the signal and converts it into an image signal, thereby completing the image reading.
[0057] An image sensor comprising the pixel array circuit described above.
[0058] A camera that includes the image sensor described above.
[0059] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of this utility model.
Claims
1. A bit line switch circuit, characterized by: include, The high voltage domain (100) includes a first deep N-well high voltage transistor (NM0) and a second deep N-well high voltage transistor (NM1) connected to each other. The first deep N-well high voltage transistor (NM0) is connected to the readout circuit, and the second deep N-well high voltage transistor (NM1) is connected to the pixel unit. The low voltage domain (200) includes a first PMOS transistor (PM2) and a second PMOS transistor (PM3) connected in series, with the first PMOS transistor (PM2) connected to a first deep N-well high voltage transistor (NM0). The control signal terminal (300) includes a Prog_Mode signal terminal and a Select signal terminal. The gate of the second PMOS transistor (PM3) is connected to the Prog_Mode signal terminal, and the Select signal terminal is connected to the drain of the second PMOS transistor (PM3) through a buffer.
2. The bit line switch circuit of claim 1, wherein: The gate of the first PMOS transistor (PM2) is grounded through resistor R0, and the source of the first PMOS transistor (PM2) is connected to the gate of the first deep N-well high voltage transistor (NMO).
3. The bit line switch circuit of claim 2, wherein: The drain of the second PMOS transistor (PM3) is connected to the output of the buffer, and the input of the buffer is connected to the Select signal.
4. The bit line switch circuit of claim 3, wherein: The deep N-well ports DNW of the first deep N-well high-voltage transistor (NM0) and the second deep N-well high-voltage transistor (NM1) are connected to a positive low voltage, and the chip substrate where the first deep N-well high-voltage transistor (NM0) and the second deep N-well high-voltage transistor (NM1) are located is grounded at voltage VSS.
5. The bit line switch circuit of claim 4, wherein: The gate of the first deep N-well high-voltage transistor (NM0) is connected to the Select signal, and the gate of the second deep N-well high-voltage transistor (NM1) is connected to the Prog_Mode signal.
6. A pixel array circuit, comprising a bit line switching circuit as described in any one of claims 1-5, wherein the gate of a pixel unit (VPS) is connected to a word line (WL), the drain is connected to a bit line (BL), and the source is connected to a source line (SL), characterized in that: It also includes, The pixel array (400) includes several groups of independently configured pixel units (VPS), each pixel unit (VPS) being connected to a bit line (BL) and a word line (WL). Several sets of bit line switch circuits are connected between each bit line (BL) and the readout circuit; A pixel array substrate (PW) electrically connected to pixel cells (VPS).
7. The pixel array circuit of claim 6, wherein: The pixel array substrate (PW) is also connected to the power supply port of the power supply unit. The pixel array substrate (PW) is connected to a negative voltage in programming mode and to a positive high voltage in erasing mode. The bit line switch circuit is used to control the connection and disconnection between the pixel array (400) and the readout circuit.
8. The pixel array circuit according to claim 7, characterized in that: Each bit line (BL) is connected to at least one set of pixel array substrates (PW) simultaneously.
9. An image sensor, characterized in that: Includes the pixel array circuit as described in claim 7 or 8.
10. A camera, characterized in that: Including the image sensor as described in claim 9.