A power semiconductor device with reduced gate resistance

Abstract

The utility model discloses a kind of power semiconductor devices of reducing gate resistance, including silicon substrate, epitaxial layer and silicon dioxide dielectric layer, gate trench is formed on the epitaxial layer, a layer of gate oxide layer is formed on the groove wall of the gate trench, gate polysilicon is arranged in the gate trench, gate metal wiring is arranged in one side or both sides of the gate polysilicon;Body area is formed in the two sides of the gate trench, active region is formed in the upper portion of the body area;Source area via hole, which extends into source area downwards, is formed on the silicon dioxide dielectric layer, metal peg is arranged in the source area via hole.In the utility model, by setting gate metal wiring in gate polysilicon, gate signal of cell in power semiconductor chip is mainly transmitted by metal instead of traditional polysilicon, since the resistivity of metal is greatly lower than polysilicon, therefore, gate resistance is greatly reduced, switching speed and linear region capability are improved, and device performance is optimized.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors, and in particular relates to a power semiconductor device that reduces gate resistance. Background Technology

[0002] With the increasing frequency of power MOSFETs and the growing demand for linearity, gate resistance has become a crucial parameter for improving switching losses and robustness against high current surges. Traditional methods require adding a gate runner, affecting the active area (the effective conducting region in the MOSFET, such as the channel region) and increasing Rdson resistance, thus impacting device performance. Traditional power MOSFETs transmit gate signals via polysilicon doped with group III or group V elements, connecting to the gate metal pad to communicate with external gate control signals. Since the concentration of group III or group V elements doped in the polysilicon is typically E19cm⁻¹, this method is less effective. -3 ~E20cm -3 The resistivity of polysilicon gates is typically 5E-4 ohms·cm, far exceeding that of metals such as aluminum (2.65E-6 ohms·cm), copper (1.678E-6 ohms·cm), tungsten (8E-6 ohms·cm), and titanium (60E-6 ohms·cm). Therefore, the high resistivity of polysilicon gates leads to high gate resistance and uneven gate resistance distribution within the chip. This limits the device's turn-on speed, and the uneven turn-on speed of cells within the chip can easily cause uneven current distribution, resulting in dynamic performance issues such as localized overheating and burnout. Utility Model Content

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by this utility model is to provide a power semiconductor device with reduced gate resistance.

[0004] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0005] A power semiconductor device for reducing gate resistance includes a silicon substrate, an epitaxial layer formed on the silicon substrate, and a silicon dioxide dielectric layer formed on the epitaxial layer. A gate trench is formed on the epitaxial layer, a gate oxide layer is formed on the trench wall, a gate polysilicon is disposed in the gate trench, and a gate metal wiring is disposed on one or both sides of the gate polysilicon. Body regions are formed on both sides of the gate trench, and a source region is formed on the upper part of the body region. A source region via extending downward into the source region is formed on the silicon dioxide dielectric layer, and a metal plug is disposed in the source region via.

[0006] Furthermore, the upper part of the gate polysilicon has a polysilicon protrusion that extends upward from the gate trench and into the silicon dioxide dielectric layer.

[0007] Furthermore, a gate metal wiring is formed on each side of the gate polysilicon, the width of the polysilicon protrusion is smaller than the width of the lower part of the gate polysilicon, and the two gate metal wirings are respectively disposed on both sides of the polysilicon protrusion.

[0008] Furthermore, the gate metal wiring is made of tungsten, and a barrier layer is formed between the gate metal wiring and the gate polysilicon.

[0009] Furthermore, the barrier layer is a silicide formed by rapidly thermally annealing titanium and titanium nitride after deposition.

[0010] Furthermore, the width of the gate metal wiring is 500A to 2000A.

[0011] Furthermore, an ohmic contact area is formed at the bottom of the source region via.

[0012] Furthermore, the metal plug is a tungsten plug, and a contact hole protective layer is provided between the tungsten plug and the hole wall of the source region through hole.

[0013] Furthermore, the contact hole protective layer is a silicide formed by depositing protective metal and nitrides through a physical vapor deposition process and utilizing rapid thermal annealing.

[0014] Furthermore, the protective metal is one or more of titanium, cobalt, and tantalum.

[0015] In this invention, by setting gate metal wiring in the gate polysilicon, the gate signal of the cell within the power semiconductor chip is mainly transmitted through the metal instead of the traditional polysilicon. Since the resistivity of the metal is much lower than that of polysilicon, the gate resistance is greatly reduced, the switching speed and linearity capability are improved, and the device performance is optimized. In addition, by forming polysilicon bumps, the sensitivity of the polysilicon gate etching process window to channel doping in short-channel devices can be avoided. This solves the problem that the gate etch-back depth after polysilicon etching causes source-implanted ions to affect the channel from the gate sidewall, thereby increasing channel leakage current. This allows power devices with lower on-resistance to be mass-produced smoothly. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 This is a schematic diagram of an embodiment of a power semiconductor device for reducing gate resistance according to the present invention.

[0018] Figure 2This is a schematic diagram of the structure after a hard mask is formed on the epitaxial layer.

[0019] Figure 3 This is a schematic diagram of the structure after the gate trench pattern has been etched on a hard mask.

[0020] Figure 4 This is a schematic diagram of the structure after growing a sacrificial oxide layer in the gate trench.

[0021] Figure 5 This is a schematic diagram of the structure after the sacrificial oxide layer has been etched away.

[0022] Figure 6 This is a schematic diagram of the structure after the gate oxide layer has been grown.

[0023] Figure 7 This is a schematic diagram of the structure after the gate polysilicon is formed.

[0024] Figure 8 This is a schematic diagram of the structure after impurity formation.

[0025] Figure 9 This is a schematic diagram of the structure after impurities are injected to form the source region.

[0026] Figure 10 This is a schematic diagram of the structure after silicon nitride film deposition.

[0027] Figure 11 A schematic diagram of the structure after vertical etching of a silicon nitride thin film to form silicon nitride sidewalls.

[0028] Figure 12 This is a schematic diagram of the structure after the silicon oxide isolation layer is deposited.

[0029] Figure 13 This is a schematic diagram of the structure after the silicon oxide isolation layer has been thinned by grinding.

[0030] Figure 14 This is a schematic diagram of the structure after the deposition of wiring metal.

[0031] Figure 15 This is a schematic diagram of the structure after the gate metal wiring is formed by dry etching of the wiring metal.

[0032] Figure 16 This is a schematic diagram of the structure after the silicon dioxide dielectric layer is formed.

[0033] Figure 17 This is a schematic diagram of the structure after the source region via is formed.

[0034] Figure 18 A schematic diagram of the structure after forming an ohmic contact region and activating impurities through thermal annealing.

[0035] The diagrams in the instruction manual are labeled as follows:

[0036] Silicon substrate - 100; Epitaxial layer - 200; Bulk region - 210; Source region - 220; Silicon dioxide pad - 310; First mask layer - 320; Second mask layer - 330; Mask pattern - 340; Gate trench - 400; Sacrificial oxide layer - 410; Gate oxide layer - 420; Gate polysilicon - 500; Polysilicon bump - 510; Silicon nitride thin film - 600; Silicon nitride sidewall - 610; Silicon oxide isolation layer - 700; Wiring metal - 800; Gate metal wiring - 810; Silicon dioxide dielectric layer - 900; Source via - 910; Metal plug - 920; Ohmic contact region - 930. Detailed Implementation

[0037] The following specific examples illustrate the implementation of this utility model. The illustrations provided in the following embodiments are only schematic representations of the basic concept of this utility model. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of an embodiment of a power semiconductor device for reducing gate resistance according to the present invention. It should be noted that... Figures 1 to 18 These are schematic diagrams of a relevant region of a cell structure during the fabrication of power semiconductor devices, not complete structural diagrams.

[0039] This embodiment of a power semiconductor device for reducing gate resistance includes a silicon substrate 100, an epitaxial layer 200 formed on the silicon substrate 100, and a silicon dioxide dielectric layer 900 formed on the epitaxial layer 200. The power semiconductor device for reducing gate resistance also has the necessary structures of other trench-type power semiconductor devices; these are prior art and not related to the improvements of this invention, and will not be described in detail here. The epitaxial layer 200 is generally doped with trivalent elements (e.g., boron) or pentavalent elements (e.g., arsenic, phosphorus) according to the device polarity. The thickness of the epitaxial layer 200 can be determined according to the operating voltage, or it can be a multilayer epitaxial layer 200.

[0040] A gate trench 400 is formed on the epitaxial layer 200, the gate trench 400 including a cell gate trench and a gate interconnect trench. A gate oxide layer 420 is formed on the trench wall of the gate trench 400, the thickness of the gate oxide layer 420 preferably being 5nm to 50nm. A gate polysilicon 500 is disposed in the gate trench 400. In this embodiment, the upper part of the gate polysilicon 500 has a polysilicon bump 510 extending upward from the gate trench 400 and into the silicon dioxide dielectric layer 900. By forming the polysilicon bump 510, the sensitivity of the polysilicon gate etching process window of short-channel devices to channel doping becomes too large, solving the problem that the gate etch-back depth after polysilicon etching causes ions implanted from the source region 220 to affect the channel from the gate sidewall, thereby increasing the channel leakage current, and enabling the smooth mass production of power devices with smaller on-resistance.

[0041] Gate metal wiring 810 is provided on one or both sides of the gate polysilicon 500. For example, a gate metal wiring 810 can be formed on each side of the gate polysilicon 500. The width of the polysilicon bump 510 is smaller than the width of the lower part of the gate polysilicon 500. The two gate metal wirings 810 are respectively provided on both sides of the polysilicon bump 510, so that the sum of the widths of the polysilicon bump 510 and the gate metal wirings 810 on both sides is substantially the same as the width of the lower part of the gate polysilicon 500. In this embodiment, the width of the gate metal wiring 810 is preferably 500 Å to 2000 Å; the material of the gate metal wiring 810 is tungsten, and a barrier layer is formed between the gate metal wiring 810 and the gate polysilicon 500 to avoid uncontrollable intersolution and puncture between tungsten and silicon. The barrier layer can be a silicide formed by depositing titanium and titanium nitride and then rapidly thermally annealing the titanium and titanium nitride.

[0042] A body region 210 is formed on both sides of the gate trench 400, and an active region 220 is formed on the upper part of the body region 210. The impurities implanted in the body region 210 are either trivalent or pentavalent elements, the specific type of which is determined according to the polarity of the device. The impurities implanted in the source region 220 can be either pentavalent or trivalent elements, and the impurities implanted in the source region 220 are opposite to those implanted in the body region 210; that is, when the impurity implanted in the body region 210 is a trivalent element, the impurity implanted in the source region 220 is a pentavalent element; when the impurity implanted in the body region 210 is a pentavalent element, the impurity implanted in the source region 220 is a trivalent element.

[0043] A source region via 910 extending downward into the source region 220 is formed on the silicon dioxide dielectric layer 900. An ohmic contact region 930 is formed at the bottom of the source region via 910 through ion implantation. The polarity of the impurity element implanted into the ohmic contact region 930 is opposite to that implanted into the source region 220. A metal plug 920 is disposed in the source region via 910. In this embodiment, the metal plug 920 is a tungsten plug. A contact hole protection layer (not shown in the figure) is disposed between the tungsten plug and the hole wall of the source region via 910. The contact hole protection layer is a silicide formed by depositing a protective metal and nitride through a physical vapor deposition process and then rapidly thermally annealing. The protective metal may include one or more of titanium, cobalt, and tantalum.

[0044] The method for fabricating the power semiconductor device in this embodiment may include the following steps:

[0045] S100: Deposit an epitaxial layer 200 on the silicon substrate 100, and etch a gate trench 400 on the epitaxial layer 200. This step may include the following sub-steps:

[0046] S110, please refer to Figure 2 One or more epitaxial layers 200 are deposited on a silicon substrate 100. The epitaxial layers 200 are generally formed by chemical vapor deposition.

[0047] S120, please continue reading Figure 2 A silicon dioxide pad layer 310, a first mask layer 320, and a second mask layer 330 are sequentially fabricated on the epitaxial layer 200. In this embodiment, the first mask layer 320 is made of silicon nitride, and the second mask layer 330 is made of silicon dioxide, thereby forming a hard mask with a multilayer insulator composite structure of silicon dioxide-silicon nitride-silicon dioxide. Both silicon dioxide and silicon nitride can be prepared by chemical vapor deposition.

[0048] S130, Photoresist is covered on the second mask layer 330, and the pattern of the gate trench 400 is exposed on the photoresist through the mask.

[0049] S140, please refer to Figure 3 The second mask layer 330, the first mask layer 320 and the silicon dioxide pad layer 310 are etched by dry etching using photoresist patterning to form mask pattern 340.

[0050] S150, please refer to Figure 4 The gate trench 400 is formed on the epitaxial layer 200 by dry etching using the mask pattern 340.

[0051] S160, please continue reading Figure 4The photoresist and the second mask layer 330 are removed by wet etching, followed by wet cleaning. Since both the silicon dioxide pad layer 310 and the second mask layer 330 in this embodiment are made of silicon dioxide, a portion of the silicon dioxide pad layer 310 is also removed during the wet etching process to remove the second mask layer 330.

[0052] S200: Form a gate oxide layer 420 on the trench wall of the gate trench 400. This step may include the following sub-steps:

[0053] S210, please continue reading Figure 4 A silicon dioxide layer is grown on the wall of the gate trench 400 as a sacrificial oxide layer 410 using a thermal oxidation process; the thickness of the sacrificial oxide layer 410 is generally 5nm to 50nm.

[0054] S220, please refer to Figure 5 The sacrificial oxide layer 410 is removed by wet etching. By forming and removing the sacrificial oxide layer 410, the cell gate trench and gate interconnect trench can be rounded and plasma damage repaired by thermal oxidation process.

[0055] S230, please refer to Figure 6 A gate oxide layer 420 is grown on the trench wall of the gate trench 400 using a thermal oxidation process. The thickness of the grown gate oxide layer 420 is determined according to the requirements of device performance, and the thickness of the gate oxide layer 420 is generally 5nm to 50nm.

[0056] S300, Deposit gate polysilicon 500 in gate trench 400, the gate polysilicon 500 having polysilicon bumps 510 extending upwardly out of gate trench 400. This step may include the following sub-steps:

[0057] S310. Oxidize the polysilicon layer (not shown in the figure) by low-pressure chemical vapor deposition. The polysilicon layer needs to fill the gate trench 400. The thickness of the polysilicon layer depends on the actual depth of the gate trench 400.

[0058] S320: The polysilicon layer on the surface of the first mask layer 320 is removed by chemical mechanical polishing. Because the stop position cannot be set very precisely during chemical mechanical polishing, in the actual process, after polishing to the surface of the first mask layer 320, a further portion is polished downwards.

[0059] S330, please refer to Figure 7The first mask layer 320 is removed by wet etching, forming a polysilicon protrusion 510 extending upwards from the gate trench 400 on the upper part of the gate polysilicon 500. Subsequently, the morphology of the gate polysilicon 500 on the silicon plateau region can be adjusted by dry etching, mainly to remove the gate polysilicon 500 extending laterally from the gate trench 400 to the silicon plateau region to avoid affecting subsequent ion implantation and to adjust the gate resistance. Of course, in this step, it is not necessary to remove all the polysilicon extending laterally from the gate trench 400 to the silicon plateau region; a small amount of polysilicon can remain in the area of ​​the silicon plateau region that does not affect the implantation of the body region 210.

[0060] S400, formed by ion implantation of body region 210 and source region 220. See also... Figure 8 First, a body region 210 can be formed on the upper surface of the epitaxial layer 200 by ion implantation of impurities, wherein the impurities are trivalent or pentavalent elements, and the specific type is determined according to the polarity of the device. Then, the impurities in the body region 210 are activated by a thermal process. At this time, the exposed polysilicon surface (including the surface of the silicon platform region and the surface of the polysilicon bump 510) will also be oxidized to form silicon dioxide. Therefore, the small amount of gate polysilicon 500 remaining on the silicon platform region in step S330 will be oxidized to form silicon dioxide, and the width of the polysilicon bump 510 becomes smaller after oxidation, making the width of the polysilicon bump 510 smaller than the width of the gate polysilicon 500 below.

[0061] Please see Figure 9 Next, a source region 220 is formed on the upper surface of the body region 210 by ion implantation of impurities. The implanted impurities can be pentavalent or trivalent elements. The impurities implanted in the source region 220 are opposite to those in the body region 210. Finally, the impurities in the source region 220 are activated by a thermal process to obtain a cellular structure. After the implantation of the body region 210 and the source region 220 is completed, the silicon dioxide formed on the exposed polycrystalline silicon surface during the thermal activation of impurities in this step is removed.

[0062] S500: A silicon dioxide dielectric layer 900 is formed on the epitaxial layer 200, and a gate metal wiring 810 is formed on one or both sides of the polysilicon bump 510. This step may include the following sub-steps:

[0063] S510, please refer to Figure 10 A silicon nitride thin film 600 is deposited by chemical vapor deposition. This silicon nitride thin film 600 is used to define the subsequent silicon nitride sidewall 610, and its thickness defines the thickness of the silicon nitride sidewall 610. In this embodiment, the thickness of the silicon nitride thin film 600 is 500 Å to 2000 Å.

[0064] S520, please refer to Figure 11The silicon nitride thin film 600 is vertically etched using the anisotropic properties of dry etching, thereby retaining the silicon nitride thin film 600 on both sides of the polysilicon protrusion 510 to form the silicon nitride sidewall 610.

[0065] S530, please refer to Figure 12 A silicon oxide isolation layer 700 is deposited by chemical vapor deposition to cover the entire polycrystalline silicon protrusion 510 and silicon nitride sidewall 610. The thickness of the silicon oxide isolation layer 700 is generally 3000 Å to 5000 Å.

[0066] S540, please refer to Figure 13 The silicon oxide isolation layer 700 is thinned by chemical mechanical polishing until the polysilicon bumps 510 and silicon nitride sidewalls 610 are exposed.

[0067] S550, use hot phosphoric acid chemical etching to remove the silicon nitride sidewall 610, thereby forming a sidewall gap on each side of the polysilicon protrusion 510.

[0068] S560, please refer to Figure 14 A layer of wiring metal 800 is deposited, which fills the sidewall gaps. In this embodiment, the material of the wiring metal 800 is preferably tungsten, and chemical vapor deposition of tungsten can be used to fill the narrow sidewall gaps with wiring metal 800. Before depositing tungsten, titanium and titanium nitride can be deposited first, and rapid thermal annealing can be used to form silicides from the titanium and titanium nitride to reduce contact resistance and form a barrier layer between tungsten and silicon, preventing uncontrollable intersolution and puncture between tungsten and silicon. The annealing temperature is generally 500℃~800℃.

[0069] S570, please refer to Figure 15 Dry etching removes the wiring metal 800 outside the sidewall gaps, while retaining the wiring metal 800 inside the sidewall gaps, thereby forming gate metal wiring 810 on both sides of the polysilicon bump 510.

[0070] S600, a silicon dioxide dielectric layer 900 is deposited, and a source region via 910 is formed on the silicon dioxide dielectric layer 900, and a metal plug 920 is formed in the source region via 910. The steps include the following sub-steps:

[0071] S610, please refer to Figure 16 A silicon dioxide layer is deposited on the epitaxial layer 200 by chemical vapor deposition, thereby forming a silicon dioxide dielectric layer 900 together with the mechanically ground and thinned silicon dioxide isolation layer 700.

[0072] S620, please refer to Figure 17 The source region via 910 is patterned using photoresist, and the silicon dioxide dielectric layer 900 and epitaxial layer 200 are formed by dry etching.

[0073] S630, please refer to Figure 18 High-concentration impurities are doped into the bottom of the source region via 910 by ion implantation, forming an ohmic contact region 930 at the bottom of the via 910. The impurities are then activated by rapid thermal annealing. In this step, the polarity of the impurity element implanted should be opposite to that of the element implanted in the source region 220.

[0074] S640, please continue reading Figure 1 Contact metal is deposited in the source region via 910. In this embodiment, tungsten metal is deposited in the source region via 910 as the contact metal using a tungsten plug process. Before depositing the tungsten metal, a protective metal and nitride can be deposited on the via wall of the source region via 910 as a contact hole protective layer using a physical vapor deposition process, and silicide can be formed using rapid thermal annealing.

[0075] S660, please continue reading Figure 1 The contact metal outside the source region via 910 is removed by dry etching, and a metal plug 920, i.e. a tungsten plug, is formed in the source region via 910.

[0076] S700: Complete the subsequent fabrication process of the trench-type power semiconductor device. This subsequent fabrication process generally includes: depositing an aluminum-copper compound on top of a tungsten plug using physical vapor deposition, and forming the circuit using photolithography and dry etching. A passivation layer is deposited and etched away using photolithography; the passivation layer generally includes silicon nitride or silicon dioxide, and undergoes alloy annealing, etc. The subsequent fabrication processes after the formation of the tungsten plug are all existing technologies and will not be described in detail here. After completing the above subsequent fabrication processes, a power semiconductor device with reduced gate resistance is obtained.

[0077] In this embodiment, by setting a gate metal wiring 810 in the gate polysilicon 500, the gate signal of the cell within the power semiconductor chip is mainly transmitted through the metal (i.e., the gate metal wiring 810) instead of the traditional polysilicon. Since the resistivity of the metal is much lower than that of polysilicon, the gate resistance is greatly reduced, the switching speed and linearity are improved, and the device performance is optimized. In addition, by forming the polysilicon bump 510, the sensitivity of the polysilicon gate etching process window to channel doping in short-channel devices can be avoided. This solves the problem that the gate etch-back depth after polysilicon etching causes ions implanted from the source region 220 to affect the channel from the gate sidewall, thereby increasing channel leakage current. This allows power devices with lower on-resistance to be mass-produced smoothly.

[0078] The above embodiments only illustrate preferred implementations of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A power semiconductor device with reduced gate resistance, characterized in that: The device includes a silicon substrate, an epitaxial layer formed on the silicon substrate, and a silicon dioxide dielectric layer formed on the epitaxial layer. A gate trench is formed on the epitaxial layer, and a gate oxide layer is formed on the trench wall. A gate polysilicon is disposed in the gate trench, and a gate metal wiring is disposed on one or both sides of the gate polysilicon. Body regions are formed on both sides of the gate trench, and a source region is formed on the upper part of the body regions. A source region via extending downward into the source region is formed on the silicon dioxide dielectric layer, and a metal plug is disposed in the source region via.

2. The power semiconductor device with reduced gate resistance as described in claim 1, characterized in that: The upper part of the gate polysilicon has a polysilicon protrusion that extends upward from the gate trench and into the silicon dioxide dielectric layer.

3. The power semiconductor device with reduced gate resistance as described in claim 2, characterized in that: A gate metal wiring is formed on each side of the gate polysilicon. The width of the polysilicon protrusion is smaller than the width of the lower part of the gate polysilicon. The two gate metal wirings are respectively disposed on both sides of the polysilicon protrusion.

4. A power semiconductor device with reduced gate resistance as described in claim 1, characterized in that: The gate metal wiring is made of tungsten, and a barrier layer is formed between the gate metal wiring and the gate polysilicon.

5. A power semiconductor device with reduced gate resistance as described in claim 4, characterized in that: The barrier layer is a silicide formed by rapidly thermally annealing titanium and titanium nitride after deposition.

6. A power semiconductor device with reduced gate resistance as described in claim 1, characterized in that: The width of the gate metal wiring is 500A to 2000A.

7. A power semiconductor device with reduced gate resistance as described in claim 1, characterized in that: An ohmic contact area is formed at the bottom of the source region via.

8. A power semiconductor device with reduced gate resistance as described in claim 1, characterized in that: The metal plug is a tungsten plug, and a contact hole protective layer is provided between the tungsten plug and the hole wall of the source region through hole.

9. A power semiconductor device with reduced gate resistance as described in claim 8, characterized in that: The contact hole protective layer is a silicide formed by depositing protective metal and nitrides through physical vapor deposition and rapid thermal annealing.

10. A power semiconductor device with reduced gate resistance as described in claim 9, characterized in that: The protective metal is one or more of titanium, cobalt, and tantalum.

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