Semiconductor device structure

Abstract

The present disclosure is directed to semiconductor device structures. The structures can include gate-all-around field effect transistors (GAAFETs) on a substrate. The GAAFETs can include a stack of channel layers and a masking layer on the channel layers. The GAAFETs can further include gate structures having gate electrodes that surround each of the channel layers and the masking layer. The gate structures can further include barrier layers between the gate electrodes. The GAAFETs can further include gate contact vias that pass through the masking layer to contact a portion of the barrier layer between the masking layer and the stack of channel layers. The presence of the barrier layers can prevent oxidation of the gate electrodes that surround each of the channel layers during formation of the gate contact vias.

Description

Technical Field

[0001] This disclosure relates to the structure of a semiconductor device. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs). This shrinkage has increased the complexity of semiconductor manufacturing processes. Utility Model Content

[0003] According to some embodiments of this disclosure, a structure for a semiconductor device is provided, the structure comprising: a nanostructure on a substrate; a masking layer on the nanostructure; a first dielectric layer surrounding the nanostructure; a first work function metal layer surrounding the first dielectric layer; a second dielectric layer surrounding the masking layer; a second work function metal layer surrounding the second dielectric layer; a barrier layer between the first work function metal layer and the second work function metal layer; and a contact structure passing through the second dielectric layer, the second work function metal layer and the masking layer and contacting the barrier layer.

[0004] According to some embodiments of the present disclosure, a structure for a semiconductor device is provided, the structure comprising: a fin structure on a substrate, wherein the fin structure includes a nanostructure and a masking layer on the nanostructure; a gate structure on the fin structure and comprising: a dielectric layer surrounding the nanostructure and the masking layer; a work function metal layer surrounding the dielectric layer; a barrier layer between the nanostructure and the masking layer; and a contact structure passing through the masking layer and contacting the barrier layer. Attached Figure Description

[0005] The nature of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to common industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0006] Figure 1A This is an isotropic view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0007] Figure 1B and 1C This is a cross-sectional view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0008] Figure 2 This is a flowchart of a method for forming a semiconductor transistor according to some embodiments.

[0009] Figure 3 and 4 This is an isometric view of an intermediate structure during the manufacture of a semiconductor transistor, according to some embodiments.

[0010] Figures 5 to 8 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A and 13B are cross-sectional views of intermediate structures during the manufacture of semiconductor transistors according to some embodiments.

[0011] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally indicate the same, functionally similar and / or structurally similar elements. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In the context of this application, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition itself does not specify a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of explanation, this application may use spatial relative terms such as "under," "below," "below," "above," "on top," and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0014] In some embodiments, the terms "about" and "substantially" may indicate a value of a given amount that varies within 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of the values ​​that the teachings in this document would be interpreted by one skilled in the art.

[0015] It should be noted that references to "an embodiment," "an example embodiment," "an exemplary embodiment," "exemplary," etc., in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0016] It should be understood that the wording or terminology used in this document is for illustrative rather than restrictive purposes, and that the wording or terminology used in this specification should be interpreted by a person skilled in the art in light of the teachings in this document.

[0017] By way of example and not limitation, nanostructured transistors with nanostructured (such as nanosheets (NS) or nanowires (NW)) channel regions, such as GAA nanosheet (NS) or nanowire (NW) FETs (collectively referred to as "GAAFETs"), can be formed as follows: A fin-like structure having alternating silicon-germanium (SiGe) and silicon (Si) NS or NW layers is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed on the middle portion of the fin-like structure to cover the top and sidewall surfaces of the fin-like structure, such that the edge portions of the fin-like structure are not covered by the sacrificial gate structure. The edge portions of the fin-like structure not covered by the sacrificial gate structure are removed. Subsequently, the edge portions of the SiGe NS or NW layers are recessed relative to the edge portions of the SiGe NS or NW layers, and an inner spacer structure is formed by depositing dielectric material to fill the spaces formed by the etched portions of the SiGe NS or NW layers. Next, a source / drain (S / D) epitaxial structure is formed to abut (or contact) the edge portion of the fin-like structure, such that the S / D epitaxial structure contacts the Si NS or NW layer and is isolated (or separated) from the SiGe NS or NW layer by an inner spacer structure. The source / drain may refer to the source or drain individually or collectively depending on the context. In subsequent operations, the sacrificial gate structure is removed to expose the top and sidewall surfaces of the fin-like structure. The SiGe NS or NW layer is selectively removed from the fin-like structure. During the selective removal process, the Si NS or NW layer and the inner spacer structure are not removed. Subsequently, a metal gate structure is formed to surround the Si NS or NW layer. Similar to the SiGe NS or NW layer, the metal gate structure is isolated (or separated) from the S / D epitaxial structure by an inner spacer structure before their selective removal.

[0018] The structure of a GAAFET can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes that include dual or multiple patterning procedures. Dual or multiple patterning procedures combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be created compared to those achievable using a single direct photolithography process in other ways. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0019] As semiconductor devices continue to shrink, critical dimensions of the GAAFET, such as the length / width of the Si NS or NW layer serving as the channel and the gate structure, become smaller in the exemplary GAAFET formed by the process described above. Consequently, forming a gate structure with reliable performance has become increasingly challenging. For example, a higher aspect ratio (e.g., the height-to-width ratio) of the gate structure results in stronger parasitic coupling with the surrounding conductive elements (e.g., contact structures with S / D epitaxial structures). A large height of the gate structure relative to its width also increases the resistance of the gate structure, which further affects the performance of the semiconductor device, such as its operating speed. One approach to address these challenges is to implement a top hard mask (HM), which is formed as the top layer of a fin-like structure above the Si and SiGe NS or NW layers. Accordingly, the gate structure is formed around the Si NS or NW layer and the mask layer. Subsequently, a gate contact can be formed through the mask layer, with the contact gate structure located between the mask layer and the topmost Si NS or NW layer. Therefore, the presence of the masking layer defines the upper boundary of the gate structure, resulting in a significantly reduced gate structure height compared to schemes without a top HM. However, the top HM scheme introduces issues that may compromise the reliability of the gate structure. Specifically, forming the gate contact requires etching through the masking layer, during which a portion of the gate structure will oxidize if exposed to air. The contact formed between the gate contact and the oxidized portion of the gate structure results in high contact resistance and a high critical voltage, especially for GAAFETs using n-type work function metals as the gate electrodes in the gate structure.

[0020] The embodiments described herein relate to overcoming the challenges mentioned above. In some embodiments, the structure of a semiconductor device may include a fin structure, which may include nanostructures serving as channels and a masking layer on the nanostructures. The structure may further include a gate structure and a gate contact. The gate structure may include a high-k dielectric layer surrounding the masking layer and each of the nanostructures, and a work function metal layer. The gate structure may further include a barrier layer between the work function metal layers. The gate contact may protrude through the masking layer and contact a portion of the barrier layer below the masking layer and above the nanostructures. The structure may further include a source / drain region adjacent to the nanostructures and an inner spacer between the source / drain regions and the gate structure. In some embodiments, a method of forming the structure may include forming the gate structure by depositing the barrier layer between the work function metal layers. The method may further include forming the gate contact by forming an opening through a portion beneath the masking layer and the high-k dielectric layer, depositing tungsten in the opening using tungsten chloride (WClx, such as tungsten chloride (V)(WCl5)) and hydrogen (H2) as precursors, while simultaneously removing the oxidized portion of the work function metal layer in the opening. During the formation of the gate contact, the presence of the barrier layer prevents further oxidation of the work function metal layer surrounding the nanostructure and maintains the low resistivity of the work function metal layer. The removal of the oxidized portion further ensures high conductivity between the gate contact and the gate structure.

[0021] According to some embodiments, a semiconductor device 100 having a plurality of transistors 105 formed above a substrate 102 is referenced. Figure 1A-1C To illustrate. The semiconductor device 100 may be included in a microprocessor, memory unit or other integrated circuit (IC). Figure 1A An isometric view of a semiconductor device 100 is shown. Figure 1B Examples along Figure 1A A cross-sectional view of the semiconductor device 100 taken by line B-B' (e.g., along the xz plane). Figure 1C Examples along Figure 1A A cross-sectional view of the semiconductor device 100 taken by line C-C' (e.g., along the yz plane).

[0022] Referring to FIG1, substrate 102 may be a semiconductor material, such as silicon. In some embodiments, substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 102 may include (i) an elemental semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Additionally, substrate 102 may be doped depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0023] Although Figure 1A The diagram shows a fin structure 110 housing two transistors 105, but any number of transistors 105 may be arranged along the fin structure 110. In some embodiments, the transistors 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in the x-direction) and a gate structure 115 traversing the plurality of fin structures 110 along a second horizontal direction (e.g., in the y-direction). In some embodiments, the crystal orientation of the fin structures 110 may be the same as the crystal orientation of the substrate 102.

[0024] Reference Figure 1A-1COne or more nanosheet (NS) layers 120 may be disposed above the fin structure 110. Each NS layer 120 may be surrounded by a gate structure 115 to function as a channel of a transistor 105. For example, the top, side, and bottom surfaces of each NS layer 120 may be surrounded by and in contact with the gate structure 115. The fin structure 110 and NS layers 120 may be made of a material similar to (e.g., with a lattice mismatch of about 5%) a substrate 102. In some embodiments, the crystal orientation of the NS layers 120 may be the same as the crystal orientation of the fin structure 110. In some embodiments, the fin structure 110 and NS layers 120 may be made of Si or SiGe. The fin structure 110 and NS layers 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and NS layers 120 may be doped together with a p-type dopant or with an n-type dopant. Each NS layer 120 may have a thickness Tc representing the channel thickness of the transistor 105, such as Figure 1C As shown in the diagram. The thickness Tc can have any suitable axial (e.g., z-direction) dimension, such as from about 3 nm to about 15 nm. For example, the thickness Tc can be between about 5 nm and about 8 nm. The NS layer 120 can have a width Wc representing the channel width of the transistor 105, as shown in the diagram. Figure 1C As shown in the diagram. The width Wc can have any suitable horizontal (e.g., in the y-direction) dimension, such as from about 5 nm to about 150 nm. For example, the width Wc can be between about 15 nm and about 50 nm. In some embodiments, the NS layers 120 can be perpendicularly spaced by a perpendicular spacing H1. In some embodiments, the perpendicular spacing H1 can be between about 3 nm and about 30 nm. For example, the perpendicular spacing H1 can be between about 8 nm and about 12 mm. Although Figure 1A Each transistor 105 is shown to include three NS layers 120, and Figure 1B and 1C Each transistor 105 is shown to include two NS layers 120, but any number of NS layers 120 may be included in each transistor 105. For example, each transistor 105 may include one, four, five, or six NS layers 120.

[0025] Reference Figure 1A-1CEach transistor 105 may include a masking layer 140 disposed above the NS layer 120. For example, the masking layer 140 may be spaced from the topmost NS layer 120 by a vertical spacing H2. In some embodiments, the vertical spacing H2 may be substantially the same as the vertical spacing H1 between the NS layers 120. The masking layer may have similar dimensions to the NS layer 120. For example, the width of the masking layer may be substantially the same as the width Wc. In some embodiments, the masking layer 140 and the NS layer 120 may also have substantially the same length along the x-direction. The masking layer 140 may have a thickness Tb. In some embodiments, the thickness Tb may be substantially the same as the thickness Tc of the NS layer 120. In some embodiments, the thickness Tb may be greater than the thickness Tc. The masking layer 140 may include a low-k material having a dielectric constant of less than about 3.9, such as silicon carbon nitride (SiCN) or silicon carbonitride oxynitride (SiOCN). In some embodiments, the masking layer 140 may include a silicon nitride layer. Mask layer 140 is also known as top HM 140.

[0026] Reference Figure 1A-1C The gate structure 115 can be a multilayer structure, surrounding each N / S layer 120 to regulate the transistor 105. For example, such as Figure 1C As shown, the surfaces of each NS layer 120 along the z- and y- directions are surrounded by a gate structure 115. The gate structure 115 may also surround a mask layer 140. The gate structure 115 may have a length Lc representing the channel length of the transistor 105, such as... Figure 1A and 1B As shown in the figure. The length Lc can have any suitable horizontal (e.g., in the x-direction) dimension, such as from about 3 nm to about 200 nm. In some embodiments, the ratio of width Wc to length Lc can be between about 3:1 and about 10:1. For example, the ratio of width Wc to length Lc can be about 5:1. In some embodiments, the height Hg of the gate structure 115 along the vertical direction (e.g., in the z-direction) can be defined as the vertical distance between the fin structure 110 and the mask layer 140, and can be between about 10 nm and about 100 nm.

[0027] As an example and not a limitation, each gate structure 115 may include a dielectric stack formed by an interface dielectric layer 115a and a gate dielectric layer 115b. For example, such as Figure 1CAs shown, each NS layer 120 may be surrounded by an interface dielectric layer 115a and further surrounded by a gate dielectric layer 115b. In some embodiments, the masking layer 140 may also be surrounded by a gate dielectric layer 115b. In some embodiments, the interface dielectric layer 115a and the gate dielectric layer 115b may also be disposed on the fin structure 110 and below the bottommost NS layer 120. The gate dielectric layer 115b may comprise any suitable dielectric material having any suitable thickness that provides channel conditioning for the transistor 105. In some embodiments, the gate dielectric layer 115b may be made of silicon oxide or a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). In some embodiments, the gate dielectric layer 115b may have a thickness ranging from about 1 nm to about 5 nm. Other materials and thicknesses of the gate dielectric layer 115b are within the scope and spirit of this disclosure based on the present disclosure.

[0028] Additionally, the gate structure 115 may include gate electrodes 115c, each surrounding a gate dielectric layer 115b, which in turn surrounds the NS layer 120 or the masking layer 140. Figure 1C As shown in the figure. In some embodiments, the gate electrode 115c may also be disposed on the fin structure 110 and below the bottom NS layer 120. The gate electrode 115c may function as the gate terminal of the transistor 105 by adjusting the conductivity of the NS layer 120. Each gate electrode 115c may include one or more work function metal layers, such as n-type and / or p-type work function metal layers. For example, the n-type work function metal layer in the gate electrode 115c may include an aluminum-containing metal carbide, such as titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), niobium aluminum carbide (NbAlC), titanium aluminum silicon carbide (TiAlSiC), and / or any suitable conductive material that provides a suitable work function to adjust the transistor 105.

[0029] In some embodiments, the gate structure 115 may further include a barrier layer 115d surrounding the gate electrode 115c, such as Figure 1CAs shown in the diagram. Specifically, the barrier layer 115d includes a barrier layer portion 115dt disposed between the mask layer 140 and the topmost NS layer 120 to separate the two topmost gate electrodes 115c surrounding the mask layer 140 and the topmost NS layer 120. In some embodiments, the barrier layer 115d may also be disposed between adjacent gate electrodes 115c surrounding the adjacent NS layer 120. In some embodiments, the barrier layer 115d may also be disposed on the side surface of the gate electrode 115c. In some embodiments, the barrier layer 115d may also be disposed on the fin structure 110 and below the bottommost NS layer 120. The barrier layer 115d may include a conductive material that is insensitive to oxidation during the etching process of the mask layer 140. In some embodiments, the barrier layer 115d may include titanium nitride (TiN) and / or tantalum nitride (TaN). In some embodiments, the barrier layer 115d may be doped with aluminum and / or silicon. In some embodiments, the thickness of the barrier layer 115d between the gate electrodes 115c can be between about 1 nm and about 5 nm. As discussed below, the presence of the barrier layer 115d prevents oxidation of the gate electrodes 115c surrounding the NS layer 120 during the etching process used to form the gate contact. In some embodiments, the etching process may include a fluorine-based etchant, allowing fluorine atoms to diffuse vertically into the barrier layer 115d from above. For example, the first fluorine atom concentration in the barrier layer portion 115dt between the mask layer 140 and the topmost NS layer 120 can be greater than the second fluorine atom concentration in other portions of the barrier layer 115d, such as the portions between the NS layers 120. In some embodiments, the ratio of the first concentration to the second concentration can be between about 2:1 and about 10:1.

[0030] Reference Figure 1A-1CEach transistor 105 of the semiconductor device 100 may further include a gate contact via 167 for a contact barrier layer 115d and a gate electrode 115c. The gate contact via 167 may be disposed through a mask layer 140 to form an electrical contact with a portion of the gate structure 115 beneath the mask layer 140. The gate contact via 167 may also extend perpendicularly through a gate dielectric layer 115b and a gate electrode 115c surrounding the mask layer 140. In some embodiments, the gate contact via 167 may directly contact a portion 115dt of the barrier layer between the mask layer 140 and the topmost NS layer 120. In some embodiments, the interface between the gate contact via 167 and the barrier layer 115d may be substantially flat. In some embodiments, the interface between the gate contact via 167 and the barrier layer 115d may be curved. In some embodiments, the horizontal cross-section of the gate contact via 167 may have a rectangular or cylindrical shape. In some embodiments, the gate contact via 167 may have a tapered shape, wherein the width of the top surface is greater than the width of the bottom surface. In some embodiments, the gate contact via 167 may have a uniform width from its top surface to its bottom surface. In some embodiments, the width of the top surface of the gate contact via 167 may be between about 2 nm and about 40 nm. In some embodiments, the height of the gate contact via 167 may be between about 10 nm and about 50 nm. In some embodiments, the aspect ratio of the gate contact via 167 may be between about 2:1 and about 20:1. In some embodiments, if the aspect ratio of the gate contact via 167 is less than about 2:1, the width of the gate contact via 167 may exceed the width of the gate electrode 115c and interfere with the surrounding contact structure. In some embodiments, if the aspect ratio of the gate contact via 167 is greater than about 20:1, the gate contact via 167 may be too narrow and may have high resistance. In some embodiments, the gate contact via 167 may include a metal with low resistivity, such as tungsten, cobalt, and / or ruthenium.

[0031] Reference Figure 1AThe transistor 105 of the semiconductor device 100 may further include an S / D epitaxial structure 125 disposed above opposite sides (e.g., along the x-direction) of the respective NS layers 120 to function as the source and drain terminals of the transistor 105. The S / D epitaxial structure 125 may be disposed on the fin structure 110. In some embodiments, the S / D epitaxial structure 125 may be disposed on the fin structure 110. The S / D epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch within about 5%) the NS layers 120. In some embodiments, the S / D epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The S / D epitaxial structure 125 may be doped with a p-type dopant, an n-type dopant, or an intrinsic dopant. In some embodiments, the S / D epitaxial structure 125 may have a different doping type than the NS layers 120. In some embodiments, the n-type dopant in the S / D epitaxial structure 125 may include P, As, Sb, or combinations thereof. In some embodiments, the crystal orientation of the S / D epitaxial structure 125 may be the same as the crystal orientation of the NS layer 120.

[0032] Reference Figure 1A The semiconductor device 100 may include an inner spacer structure 130 that abuts (or contacts) a side surface of the gate structure 115. The inner spacer structure 130 may separate the gate structure 115 from the S / D epitaxial structure 125. For example, the inner spacer structure 130 may be formed along the channel direction of the transistor 105 (e.g., along the x-direction) on opposite sides of the gate structure 115 to separate the gate structure 115 from the S / D epitaxial structure 125. In some embodiments, the inner spacer structure 130 may be formed between two orthogonally adjacent (e.g., in the z-direction) NS layers 120. In some embodiments, the inner spacer structure 130 may be formed between the fin structure 110 and the bottommost NS layer 120. In some embodiments, the inner spacer structure 130 may be formed between the mask layer 140 and the topmost NS layer 120. In some embodiments, the inner spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon oxycarbon nitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxynitride (SiON). In some embodiments, the inner spacer structure 130 may include a low-k material, such as a porous material, and a dielectric based on carbon-rich silicon oxide.

[0033] Reference Figure 1AThe semiconductor device 100 may further include a gate spacer 135 formed between the gate structure 115 and the S / D epitaxial structure 125. The gate spacer 135 may provide structural support during the formation of the gate structure 115. Furthermore, the gate spacer 135 may provide electrical isolation and protection for the gate structure 115 during the formation of the S / D junction. The gate spacer 135 may be made of any suitable dielectric material. In some embodiments, the gate spacer 135 may be made of silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9. In some embodiments, the gate spacer 135 may have any suitable thickness, such as from about 5 nm to about 15 nm. Other materials and thicknesses of the gate spacer 135 are within the scope and spirit of this disclosure.

[0034] Reference Figure 1A The semiconductor device 100 may further include shallow trench isolation (STI) regions 138, which are configured to provide electrical isolation between fin structures 110. STI regions 138 may also provide electrical isolation between transistor 105 and adjacent active and passive components integrated with or disposed on substrate 102. STI regions 138 may include one or more dielectric material layers, such as nitride layers, oxide layers disposed on nitride layers, and insulating layers disposed on nitride layers. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. Other dielectric materials for STI regions 138 are within the scope and spirit of this disclosure.

[0035] Reference Figure 1A The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation for structural elements such as the gate structure 115 and the S / D epitaxial structure 125. In some embodiments, a gate spacer 135 may be disposed between the gate structure 115 and the ILD layer 165. The ILD layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbonate, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride. The ILD layer 165 may have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Based on the disclosure of this application, other insulating materials and thicknesses of the ILD layer 165 are within the scope and spirit of this disclosure. (See also...) Figure 1AThe semiconductor device 100 may further include an S / D contact 163 that contacts the S / D epitaxial structure 125. The S / D contact 163 may be disposed on the S / D epitaxial structure 125 and surrounded by an ILD layer 165. In some embodiments, a silicide layer 164 may be disposed between the S / D contact 163 and the S / D epitaxial structure 125. In some embodiments, the height of the S / D contact 163 may be between about 10 nm and about 50 nm. The S / D contact 163 may include any suitable conductive material that provides low contact resistance with the S / D epitaxial structure 125. In some embodiments, the S / D contact 163 may be made of polysilicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, cobalt, aluminum, copper, tungsten, tantalum, nickel, or combinations thereof. Other materials for the S / D contact 163 are within the scope and spirit of this disclosure.

[0036] Reference Figure 1A and 1B The semiconductor device 100 may further include a dielectric layer 152 on the transistor 105. In some embodiments, the dielectric layer 152 may include silicon oxide and / or silicon nitride. In some embodiments, the dielectric layer 152 may be an etch stop layer. In some embodiments, the S / D contact 163 and the gate contact via 167 may extend perpendicularly through the dielectric layer 152.

[0037] According to some embodiments, Figure 2 Examples used to form Figure 1A-1C The flowchart illustrates a method 200 for manufacturing transistor 105. This disclosure is not limited to this description of operations, and additional operations may be performed. Other manufacturing operations may be performed between various operations of method 200, and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, several operations may be performed simultaneously or in different sequences. Figure 2 The operations are performed in the sequence shown. In some embodiments, one or more other operations may be performed in addition to or in lieu of the operations currently described. For illustrative purposes, method 200 refers to... Figure 3-13B The structure shown is used for illustration. Unless otherwise stated, those with the same annotations... Figure 1A-1C The discussion of the components in the text is applicable to Figure 3-13B .

[0038] Reference Figure 2 Method 200 begins with operation 210 and a process of forming a fin structure having a channel layer, a sacrificial layer, and a masking layer on a substrate (e.g., substrate 102). In some embodiments, the process of forming the fin structure may include forming an alternating stack of first NS layers and second NS layers on the substrate. Figure 3An isometric view of the substrate 102 and a stack 320 comprising alternating first NS layers 320a and second NS layers 320b, covered by a masking layer 340. In some embodiments, the first NS layers 320a and second NS layers 320b are formed on the exposed top surface of the substrate 102. In some embodiments, the first NS layer 320a is a sacrificial NS layer that undergoes subsequent removal, and the second NS layer 320b corresponds to... Figure 1A-1C The NS layer 120 shown. In some embodiments, the mask layer 340 corresponds to Figure 1A-1C The masking layer 140 is shown. In some embodiments, the material of the first NS layer 320a in the stack 320 is selected such that the first NS layer 320a can be selectively removed from the stack 320 by etching, without removing the second NS layer 320b and the masking layer 340. For example, the first NS layer 320a may be a SiGe NS layer and the second NS layer 320b may be a Si NS layer.

[0039] The first NS layer 320a and the second NS layer 320b can be grown using any suitable method. For example, the first NS layer 320a and the second NS layer 320b can be grown using a chemical vapor deposition (CVD) process with a precursor gas, such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first NS layer 320a may include Ge at a concentration between about 20% and about 30%, while the second NS layer 320b is substantially free of germanium—for example, having a Ge concentration of less than about 1%. In some embodiments, the second NS layer 320b, which corresponds to... Figure 1A The NS layer 120 of B is the channel layer forming the transistor 105 and can be lightly doped or inherently (e.g., undoped). If lightly doped, the doping level of the second NS layer 320b is less than approximately 10. 13 atoms / cm 3 The first NS layer 320a and the second NS layer 320b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any interposer layer. In some embodiments, the first NS layer 320a may be doped in subsequent etching operations to increase its etch selectivity compared to the second NS layer 320b.

[0040] In some embodiments, the thickness of the first NS layer 320a defines the spacing between every other second NS layer 320b in the stack 320. The thickness of the second NS layer 320b can range, for example, from about 3 nm to about 15 nm. The thickness of the first NS layer 320a can range, for example, from about 3 nm to about 30 nm. The thickness of the first NS layer 320a corresponds to the vertical spacing H1 between the NS layers 120 and the vertical spacing H2 between the topmost NS layer 120 and the mask layer 140, as shown below. Figure 1C As shown in the diagram. Since the first NS layer 320a and the second NS layer 320b are grown individually, the thickness of each NS layer can be adjusted independently, for example, based on the deposition time. In some embodiments, additional or fewer first NS layers 320a and second NS layers 320b may be formed in the stack 320. In some embodiments, the total number of NS layers may be 2n+1, where n+1 is the number of first NS layers 320a and n is the number of second NS layers 320b in the stack 320. In some embodiments, n may be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0041] In some embodiments, the mask layer 340 may be formed by depositing a dielectric material layer, such as silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9, on the topmost first NS layer 320a. In some embodiments, the dielectric material is selected to resist subsequent etching processes that remove the first NS layer 320a. In some embodiments, the dielectric material layer may be deposited by a CVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a sputtering process, or an evaporation process.

[0042] Reference Figure 2 Operation 210 may further include a process of patterning the stack 320 to form a fin structure. In some embodiments, the stack 320 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The width along the y-direction corresponds to, for example,... Figure 1C The width Wc shown is used. The fin structure can be formed by patterning using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be created compared to those achievable using a single direct photolithography process in other ways. In some embodiments, a sacrificial layer is formed on top of the stack 320 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask structure to pattern the fin structure.

[0043] As an example, not a limitation, Figure 4 This is an isometric view of the fin structure 420 formed from the stack 320 using the aforementioned patterning process. In some embodiments, the fin structure 420 may be formed by etching the first NS layer 320a, the second NS layer 320b, and the mask layer 340 into the first NS layer 420a, the second NS layer 420b, and the mask layer 440. In some embodiments, the aforementioned patterning process does not terminate on the top surface of the substrate 102, but continues to etch the top portion of the substrate 102 to form the fin structure 110 from the substrate 102 below the fin structure 420. Since the fin structure 420 and the fin structure 110 are formed using the same patterning process, the fin structure 420 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 420 in the xz plane and the yz plane are substantially aligned with the respective sidewall surfaces of the fin structure 110, such as... Figure 4 As shown in the image.

[0044] Additional fin structures, such as fin structure 420, may be formed on the substrate 102 in the same or different regions of the substrate 102. For simplicity, these additional fin structures are not shown on the substrate 102. Figure 4 As shown in the figure. By way of example and not limitation, each fin structure 420 has a width along the y-direction between approximately 15 nm and approximately 150 nm.

[0045] In some embodiments, NS layers 420a and 420b are referred to as "nanosheets" when their width along the y-direction is substantially different from their height along the z-direction—for example, when their width is greater than / narrower than their height. In some embodiments, NS layers 420a and 420b may also be referred to as "nanowires" when their width along the y-direction is substantially equal to their height along the z-direction. In some embodiments, NS layers 420a and 420b are deposited as nanosheets and subsequently patterned to form nanowires with substantially equal height and width. By way of example and not limitation, NS layers 420a and 420b are illustrated in the context of nanosheet (NS) layers. Nanowires (NW) are within the spirit and scope of this disclosure based on the present disclosure. Furthermore, for illustrative purposes and without limiting the scope of this disclosure, the first NS layer 420a and the second NS layer 420b in method 200 are illustrated in the context of SiGe and Si NS layers, respectively.

[0046] In some embodiments, after the fin structure 420 is formed, an STI region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the STI region 138 may include one or more silicon oxide-based dielectrics that electrically isolate the fin structure 110. By way of example and not limitation, the STI region 138 may be formed as follows: An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket-deposited over the fin structure 420 and the substrate 102. The deposited isolation structure material is planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 420. The planarized isolation structure material is then etched back such that the resulting STI region 138 has a height substantially similar to that of the fin structure 110, such as Figure 4 As shown in the figure. In some embodiments, the fin structure 420 protrudes from the STI region 138 such that the STI region 138 does not cover the sidewall portion of the fin structure 420, as shown in the figure. Figure 4 As shown in the image.

[0047] Method 200 continues with operation 220 and the procedure of forming an inner spacer in the fin structure. Operation 220 may begin by removing a portion of the fin structure to form an opening in the fin structure, including (i) forming a sacrificial gate structure 500, as referenced. Figure 5 As described above, and (ii) removing portions of the fin structure 420 exposed by the sacrificial gate structure 500, as referenced. Figure 6 As explained.

[0048] As an example, not a limitation, Figure 5 for Figure 4 A cross-sectional view taken along the cutting line AB. Figure 5 The sacrificial gate structure 500 is shown formed on a portion of the fin structure 420. Because Figure 5 This is a cross-sectional view, not an isometric view, therefore the portion of the sacrificial gate structure 500 covering the sidewall portion of the fin structure 420 is not shown. Additionally, in Figure 5 In the cross-sectional view, only Figure 4 One of the fin structures 420. In some embodiments, portions of the sacrificial gate structure 500 are formed between and on the fin structures 420. Figure 4 The STI region 138 is shown.

[0049] In some embodiments, the sacrificial gate structures 500 are formed wherein their length is along the y-direction—for example, perpendicular to the y-direction. Figure 4The isometric view shows the fin structures 420—and their widths along the x-direction. In some embodiments, the sacrificial gate structure 500 may cover the top and sidewall portions of the fin structure 420. During a subsequent gate replacement procedure, the sacrificial gate structure 500 is then replaced with... Figure 1A-1C The gate structure 115 is shown. The sacrificial gate structure 500 may include a sacrificial gate electrode 500a formed on the mask layer 440. The sacrificial gate structure 500 may also include a capping layer 505 formed on the top surface of the sacrificial gate structure 500. In some embodiments, the capping layer 505 may protect the sacrificial gate electrode 500a from subsequent etching operations. During this manufacturing stage, a gate spacer 135 may be formed on the side surface of the sacrificial gate structure 500. As discussed above, the gate spacer 135 is not removed during the gate replacement procedure; rather, the gate spacer 135 facilitates... Figure 1A The formation of the gate structure 115 shown.

[0050] By way of example and not limitation, the sacrificial gate structure 500 may be formed by depositing and patterning a sacrificial gate electrode 500a over the fin structure 420. In some embodiments, the sacrificial gate structure 500 is formed over a plurality of fin structures 420. Figure 5 As shown, a portion of the fin structure 420 is not covered by the sacrificial gate structure 500. This is because the width of the sacrificial gate structure 500 is narrower than the length of the fin structure 420 along the x-direction. In some embodiments, the sacrificial gate structure 500 serves as a mask structure in subsequent etching operations to define... Figure 1A The channel region of transistor 105 is shown. For this reason, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 500 and gate structure 115 are substantially similar.

[0051] Reference Figure 6The portion of the fin structure 420 not covered by the sacrificial gate structure 500 can be removed to form an opening 680. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective for the mask layer 440, the first NS layer 420a, and the second NS layer 420b, shaping them into the mask layer 640, the first NS layer 620a, and the NS layer 120, respectively. In some embodiments, the dry etching process includes an etchant having the following components: oxygen-containing gas; fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemistry may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; solutions containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH); or combinations thereof.

[0052] In some embodiments, the etchant used in the aforementioned etching process does not substantially etch. Figure 6 The sacrificial gate structure 500 shown is protected by a capping layer 505 and a gate spacer 135. Figure 4 The STI region 138 is shown. This is because the capping layer 505, the gate spacer 135, and the STI region 138 comprise materials with low etch selectivity, such as silicon nitride-based materials (e.g., silicon nitride, silicon carbonitride, and silicon carbonitride-oxide) or silicon oxide-based materials. In some embodiments, Figure 4 The STI region 138 shown is used as an etch stop layer in the above etch process.

[0053] After removing portions of the fin structures 420 not covered by the sacrificial gate structure 500, openings 680 are formed in each fin structure 420, such as Figure 6 As shown, opening 680 divides each fin structure 420 into separate portions, each of which is covered by the sacrificial gate structure 500.

[0054] Reference Figure 2 Operation 220 can continue the process of forming an inner spacer in the opening 680. The process of forming the inner spacer may include (i) selectively etching the edge portion of the first NS layer 620a to form a recessed structure 745, as shown in the reference. Figure 7 As explained, and (ii) the formation of an inner spacer structure 130 in the recessed structure 745, as shown in reference Figure 8As described. According to some embodiments, Figure 7 The exposed edge of the first NS layer 620a is shown after being laterally etched (e.g., recessed) along the x-direction and becoming the first NS layer 720a. Figure 6 The structure. According to some embodiments, the exposed edge of the first NS layer 620a is along, as shown in the figure. Figure 7 The shown x-direction recess (e.g., partial etching) is made in an amount ranging from about 3 nm to about 10 nm to form a recessed structure 745.

[0055] In some embodiments, selective etching of the first NS layer 620a can be achieved using a dry etching process selective for SiGe. For example, halogen-based chemicals exhibit high etching selectivity for Ge and low etching selectivity for Si. Therefore, halogen gases etch Ge-containing layers, such as the first NS layer 620a, at a higher etch rate than substantially Ge-free layers (such as NS layer 120). In some embodiments, halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, wet etching chemicals with high selectivity for SiGe can be used. By way of example and not limitation, wet etching chemicals may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonium hydroxide with H2O2 and water (APM). The aforementioned etching process is timed to remove the desired amount of SiGe.

[0056] In some embodiments, the first NS layer 620a with a higher Ge atom concentration has a higher etch rate than the NS layer 120 with a lower or zero Ge atom concentration. Therefore, the etch rate of the aforementioned etching process can be adjusted by regulating the Ge atom concentration (e.g., Ge content) in the first NS layer 620a. As discussed above, the Ge content in the first NS layer 620a can be in the range of about 20% to about 30%. A SiGe nanosheet layer with about 20% Ge can be etched more slowly than a SiGe nanosheet layer with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve the desired etch rate and selectivity between the first NS layer 620a and the NS layer 120.

[0057] Reference Figure 7 and 8 Once the recessed structure 745 is formed, the dielectric layer can be deposited in a blanket-like manner. Figure 7 The portion of the dielectric layer above the entire structure, and outside the recess structure 745, can be removed, leaving the inner spacer structure 130 filling the recess structure 745, as shown in the reference. Figure 8 As explained.

[0058] Reference Figure 2After forming the inner spacer structure 130, method 200 can continue with operation 230 and the process of forming the S / D epitaxial structure in the opening 680 and adjacent to the NS layer 120. For example, as shown in reference Figure 9A As explained, the S / D epitaxial structure 125 can be formed by epitaxial growth of semiconductor material in the opening 680.

[0059] In some embodiments, such as reference Figure 9A As explained, the S / D epitaxial structure 125 can be epitaxially grown using a CVD process, which is similar to the process used in operation 210 to form the first N / S layer 320a and the second N / S layer 320b, as shown in the reference. Figure 3 As described above. In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the side surface of the NS layer 120 in a horizontal direction (e.g., along the x-axis). In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the top surface of the fin structure 110 in a vertical direction (e.g., along the z-axis). In some embodiments, the S / D epitaxial structure 125 may be grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, or a combination thereof) may be used to grow a semiconductor material (e.g., Si) having the same or similar crystalline structure as the NS layer 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove semiconductor material having an amorphous structure formed on the dielectric surface (e.g., the side surfaces of the inner spacer structure 130 and the gate spacer 135). Removing the semiconductor material with an amorphous structure ensures that the crystalline structure of the S / D epitaxial structure 125 is crystalline. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsine (AsH3), antimonyane (SbH3), or a combination thereof, may be used in a CVD or PECVD process to dope the S / D epitaxial structure 125.

[0060] Figure 9B Example corresponding to Figure 9A The cross-sectional view of line C-C' in the diagram. Note that... Figure 9B Indicates corresponding to Figure 5-9A The same cross-sectional view at the same location in the diagram, and it remains unchanged between operations 220 and 230.

[0061] Reference Figure 2 Method 200 can then proceed with operation 240 and the removal of the sacrifice layer. For example, see reference... Figure 10A and 10BAs explained, the first NS layer 720a can be removed together with the sacrificial gate structure 500. In some embodiments, removing the sacrificial gate structure 500 may include removing the capping layer 505 to expose the sacrificial gate electrode 500a, and subsequently removing the sacrificial gate electrode 500a to expose the top surface of the masking layer 640. In some embodiments, removing the first NS layer 720a may include selectively etching the first NS layer 720a without removing the NS layer 120 and the masking layer 640, as shown in the reference. Figure 10A and 10B This allows the upper, lower, and side surfaces of the NS layer 120 and the masking layer 640 to be exposed. In some embodiments, the top surface of the fin structure 110 beneath the NS layer 120 may also be exposed.

[0062] Reference Figure 2 Method 200 can continue with operation 250 and the process of forming the gate structure, including (i) depositing a high-k dielectric layer surrounding the channel layer and the masking layer, (ii) depositing a gate electrode surrounding the high-k dielectric layer, and (iii) forming a barrier layer between the gate electrodes, as shown in the reference. Figure 11A and 11B As explained.

[0063] In some embodiments, an interface dielectric layer 115a may be formed on the exposed surface of the NS layer 120 prior to the deposition of a high-k dielectric layer. The interface dielectric layer 115a may be formed by treating the NS layer 120 in an environment containing oxygen free radicals, such as oxygen, ozone, deionized water, deionized water (DI water), carbonated deionized water (DICO2), ozonated deionized water (DIO3), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), chloric acid (HCl), ammonia (NH4OH), or combinations thereof. In some embodiments, the NS layer 120 may be treated with oxygen free radicals in a thermal process. In some embodiments, the interface dielectric layer 115a may be formed on the exposed top surface of the fin structure 110. In some embodiments, the presence of the interface dielectric layer 115a may facilitate subsequent deposition of a high-k dielectric layer on the NS layer 120.

[0064] In some embodiments, the process of forming the gate dielectric layer 115b on the interface dielectric layer 115a may include depositing a high-k dielectric material (e.g., HfO2, Al2O3, ScO2, ZrO2, CaO, MgO, and / or ZrSiO4) in a CVD or ALD process. In some embodiments, depositing the gate electrode 115c may include depositing one or more work function metal layers (e.g., TiAlC) in a CVD or ALD process. In some embodiments, the gate dielectric layer 115b and the gate electrode 115c may also be deposited on the exposed top surface of the fin structure 110. Deposition parameters (e.g., deposition time, deposition pressure, and / or deposition temperature) may be selected to control the thickness of the gate dielectric layer 115b and the gate electrode 115c and to ensure that the gate electrodes 115c surrounding the different NS layers 120 and the masking layer 640 do not merge with each other, such that there is sufficient spacing between the gate electrodes 115c for subsequent deposition of the barrier layer 115d. In some embodiments, the deposition of the barrier layer 115d may include depositing TiN or TaN in a CVD or ALD process to fill the space between the gate electrodes 115c. In some embodiments, titanium nitride (TiCl) x Precursors of ammonia (NH3) and / or NH3 can be used to deposit the barrier layer 115d. In some embodiments, the deposition temperature may be between about 300°C and about 500°C. In some embodiments, the barrier layer 115d may be deposited on the side surface of the gate electrode 115c to surround the gate electrode 115c. In some embodiments, the barrier layer 115d may also be deposited on the masking layer 640.

[0065] Reference Figure 2 Method 200 continues with operation 260, wherein a contact opening is formed on the mask layer. For example, see reference... Figure 12A and 12B As described, the contact opening 1280 may be formed through a portion of the barrier layer 115d above the masking layer 640 and the upper portion of the topmost gate electrode 115c. In some embodiments, a dielectric layer 152 may be deposited over the gate structure 115 before forming the contact opening 1280. The contact opening 1280 may be formed through the dielectric layer 152. The contact opening 1280 may also be formed through the masking layer 640, thus becoming the masking layer 140. The contact opening 1280 may also be formed through the topmost gate dielectric layer 115b surrounding the masking layer 640 to expose the lower portion 115ct of the topmost gate electrode 115c surrounding the masking layer 640. In some embodiments, the contact opening 1280 may have a straight cross-sectional profile with straight or sloping side surfaces. In some embodiments, the contact opening 1280 may have a horizontal cross-sectional profile with a rectangular or circular shape.

[0066] In some embodiments, the process of forming the contact opening 1280 may include a dry etching process having one or more etchants, such as fluorine-based etching gases (e.g., tungsten hexafluoride (WF6) or hydrogen fluoride (HF)). In some embodiments, fluorine atoms of the etchant may diffuse into the region below the opening 1280, and the concentration of fluorine atoms may decrease with increasing diffusion depth. Therefore, the first concentration of fluorine atoms in the first portion of the barrier layer 115d between the mask layer 140 and the topmost NS layer 120 may be greater than the second concentration of fluorine atoms in the second portion of the barrier layer 115d between the NS layers 120. For example, the ratio between the first and second concentrations of fluorine atoms may be about 2:1 and about 10:1.

[0067] In some embodiments, during the formation of the contact opening 1280, the lower portion 115ct of the topmost gate electrode 115c exposed in the contact opening 1280 may be partially or completely oxidized due to the reaction between the etchant and the exposed metal material (e.g., TiAlC) of the gate electrode 115c. The oxidized lower portion 115ct affects the quality of the contact resistance between the gate electrode 115c and the subsequently formed gate contact via, and is removed in subsequent operation 270.

[0068] Reference Figure 2 Method 200 continues with operation 270, wherein a gate contact via is formed in the contact opening. For example, see reference... Figure 13A and 13B As described, a gate contact via 1367 may be formed in the contact opening 1280. In some embodiments, the process of forming the gate contact via 1367 may include depositing a metal material layer (e.g., a metal with low resistivity, such as tungsten, cobalt, and / or ruthenium) using precursors WCl5 and H2 in a CVD process. In some embodiments, the CVD process may be a cyclic process that alternately introduces precursors WCl5 and H2. In some embodiments, the precursor WCl5 / H2 may remove the oxidized portion of the topmost gate electrode 115c while depositing tungsten on the barrier layer 115d. In some embodiments, using the precursor WCl5 / H2, the tungsten deposition may be a bottom-up process, such that tungsten may be deposited from the bottom surface of the contact opening 1280 but not on its side surfaces, thereby avoiding the formation of overhangs or void structures in the contact opening 1280. In some embodiments, the deposition temperature may be between about 350°C and about 500°C. For example, the deposition temperature may be between about 375°C and about 475°C. In some embodiments, the presence of the barrier layer 115d can act as a seed layer to promote uniform tungsten growth. In some embodiments, the CVD process used to deposit tungsten to form the gate contact via 1367 can be a fluorine-free process. In some embodiments, the absence of fluorine during tungsten deposition can promote uniform tungsten growth.

[0069] Reference Figure 2 Operation 200 can continue the procedure for operation 280 and forming S / D contact 163, as shown in the reference. Figure 1A As described above. In some embodiments, the process of forming the S / D contact 163 may include (i) forming an ILD layer 165 on the S / D epitaxial structure 125 and between the gate structure 115, (ii) forming an opening through the ILD layer 165 to expose the S / D epitaxial structure 125, (iii) depositing a metal material (e.g., W, Cu and / or Mo) in the opening and contacting the S / D epitaxial structure 125 to form the S / D contact 163, and (iv) forming a silicide layer 164 between the S / D contact 163 and the S / D epitaxial structure 125.

[0070] The embodiments described herein pertain to the structure of a semiconductor device and a method of forming such a structure. The structure may include a GAAFET on a substrate. The GAAFET may include a stack of channel layers and a masking layer on the channel layers. The GAAFET may further include a gate structure and an S / D region. The gate structure may include a gate dielectric layer surrounding each of the channel layers and the masking layer, and a gate electrode. The gate structure may further include a barrier layer surrounding the different channel layers and the masking layer between the gate electrodes. The GAAFET may further include a gate contact via through the masking layer and the topmost gate dielectric layer and surrounding the topmost gate electrode of the masking layer. The presence of the masking layer can reduce the height of the gate structure and improve the performance of the GAAFET. The method of forming this structure may include forming an opening through the masking layer to expose a portion of the topmost gate electrode surrounding the masking layer and depositing tungsten in the opening to form the gate contact via, while removing the oxidized portion of the topmost gate electrode. The presence of the barrier layer can prevent oxidation of other gate electrodes surrounding the channel layers. The presence of this barrier layer also promotes uniform tungsten deposition on the barrier layer, thereby obtaining a high-quality gate contact via. Removing the oxidized portion of the exposed topmost gate electrode during tungsten deposition ensures low contact resistance between the gate contact via and the gate structure.

[0071] In some embodiments, the structure of a semiconductor device includes a nanostructure on a substrate, a masking layer on the nanostructure, a first dielectric layer surrounding the nanostructure, a first work function metal layer surrounding the first dielectric layer, a second dielectric layer surrounding the masking layer, a second work function metal layer surrounding the second dielectric layer, a barrier layer between the first work function metal layer and the second work function metal layer, and a contact structure that passes through the second dielectric layer, the second work function metal layer and the masking layer and contacts the barrier layer.

[0072] In some samples, the barrier layer contains titanium nitride.

[0073] In some cases, the first work function metal layer and the second work function metal layer comprise titanium aluminum carbide.

[0074] In some embodiments, the first dielectric layer and the second dielectric layer comprise a high-k dielectric material, and the masking layer comprises a low-k dielectric material or silicon nitride.

[0075] In some cases, the width of the masking layer is substantially the same as the width of the nanostructure.

[0076] In some cases, the contact structure contains tungsten, cobalt, or ruthenium.

[0077] In some states, the structure further includes source / drain regions adjacent to the nanostructure.

[0078] In some embodiments, the structure further includes an inner spacer structure between the nanostructure and the masking layer.

[0079] In some embodiments, the semiconductor device structure includes a fin structure on a substrate and a gate structure on the fin structure. The fin structure includes a nanostructure and a masking layer on the nanostructure. The gate structure includes a dielectric layer surrounding the nanostructure and the masking layer, a work function metal layer surrounding the dielectric layer, and a barrier layer between the nanostructure and the masking layer. The structure further includes a contact structure that passes through the masking layer and contacts the barrier layer.

[0080] In some cases, the width of the masking layer is substantially the same as the width of the nanostructure, and the length of the masking layer is substantially the same as the length of the nanostructure.

[0081] In some configurations, a portion of the barrier layer is above a first portion of the work function metal layer and below a second portion of the work function metal layer.

[0082] In some configurations, the contact structure extends through a first portion of the work function metal layer above the masking layer and a second portion of the work function metal layer below the masking layer.

[0083] In some configurations, the contact structure extends through a first portion of the dielectric layer above the masking layer and a second portion of the dielectric layer below the masking layer.

[0084] In some embodiments, the method includes alternately forming channel layers and sacrificial layers on a substrate, forming a masking layer on the topmost sacrificial layer of the sacrificial layers, and forming a fin structure by patterning the channel layers, the sacrificial layers, and the masking layer. The method further includes forming source / drain (S / D) regions adjacent to the fin structure and removing the sacrificial layers. The method further includes depositing a high-k dielectric layer surrounding each of the channel layers, depositing a work function metal layer on the high-k dielectric layer, and depositing a barrier layer on the work function metal layer and between adjacent nanostructures in the nanostructure. The method further includes forming a contact structure that passes through the masking layer and contacts the barrier layer on a portion beneath the masking layer.

[0085] In some embodiments, a method of forming a structure of a semiconductor device includes: alternately forming a plurality of channel layers and a plurality of sacrificial layers on a substrate; forming a mask layer on the topmost sacrificial layer of the plurality of sacrificial layers; forming a fin structure by patterning the plurality of channel layers, the plurality of sacrificial layers and the mask layer; forming a source / drain (S / D) region adjacent to the fin structure; removing the plurality of sacrificial layers; depositing a high-k dielectric layer surrounding each of the plurality of channel layers; depositing a work function metal layer on the high-k dielectric layer; depositing a barrier layer on the work function metal layer and between the mask layer and the plurality of channel layers; and forming a contact structure that passes through the mask layer and contacts the barrier layer on a portion below the mask layer.

[0086] In some cases, depositing the barrier layer involves depositing a titanium nitride or tantalum nitride layer.

[0087] In some cases, the barrier layer is deposited on a first horizontal surface of the work function metal layer and below a second horizontal surface of the work function metal layer.

[0088] In some cases, forming the contact structure involves using tungsten chloride (V) and hydrogen as precursors to remove the oxidized portion of the work function metal layer, while simultaneously depositing tungsten into the portion of the contact barrier layer.

[0089] In some cases, forming the contact structure involves removing the oxidized portion of the work function metal layer to expose that portion of the barrier layer.

[0090] In some configurations, forming the contact structure includes forming an opening that extends through the upper portion of the high-k dielectric layer on the masking layer, the masking layer, and the lower portion of the high-k dielectric layer below the masking layer.

[0091] In some cases, depositing the work function metal layer involves depositing a titanium aluminum carbide layer to surround the plurality of channel layers and the masking layer.

[0092] It will be understood that the detailed description section, rather than the summary section of the disclosure, is intended to interpret the claims. The summary section of this disclosure may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0093] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other programs and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this application without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, Include: Nanostructures, which are on a matrix; A masking layer is applied to this nanostructure. A first dielectric layer surrounds the nanostructure; A first work function metal layer surrounds the first dielectric layer; A second dielectric layer surrounds the shielding layer; A second work function metal layer surrounds the second dielectric layer; A barrier layer is formed between the first work function metal layer and the second work function metal layer; and The contact structure passes through the second dielectric layer, the second work function metal layer, and the shielding layer and contacts the barrier layer.

2. The semiconductor device structure as described in claim 1, characterized in that, The barrier layer is composed of titanium nitride.

3. The semiconductor device structure as described in claim 1 or 2, characterized in that, The first work function metal layer and the second work function metal layer are composed of titanium aluminum carbide.

4. The semiconductor device structure as described in claim 1 or 2, characterized in that, The first dielectric layer and the second dielectric layer are made of high-k dielectric material, and the masking layer is made of low-k dielectric material or silicon nitride.

5. The semiconductor device structure as described in claim 1 or 2, characterized in that, The contact structure is made of tungsten, cobalt, or ruthenium.

6. The semiconductor device structure as described in claim 1, characterized in that, The structure of the semiconductor device further includes an inner spacer structure between the nanostructure and the masking layer.

7. The semiconductor device structure as claimed in claim 1, characterized in that, The structure of the semiconductor device further includes source / drain regions adjacent to the nanostructure.

8. A semiconductor device structure, characterized in that, Include: A fin structure on a substrate, wherein the fin structure comprises a nanostructure and a masking layer on the nanostructure. A gate structure, which is on the fin structure and includes: A dielectric layer that surrounds the nanostructure and the masking layer; A work function metal layer surrounding the dielectric layer; and A barrier layer is formed between the nanostructure and the shielding layer; and The contact structure passes through the shielding layer and contacts the barrier layer.

9. The semiconductor device structure as described in claim 8, characterized in that, The width of the masking layer is substantially the same as the width of the nanostructure; and The length of the masking layer is essentially the same as the length of the nanostructure.

10. The semiconductor device structure as described in claim 8 or 9, characterized in that, A portion of the barrier layer is above the first portion of the work function metal layer and below the second portion of the work function metal layer.

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