Semiconductor device
Patent Information
- Application Number
- CN202521905963.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-04
- Publication Date
- 2026-08-18
- Estimated Expiration
- 2035-09-04
AI Technical Summary
[0003]在功率半导体器件的制造中，除了在基底上形成如LDMOS器件(横向双扩散MOSFET)、DEMOS器件(漏端扩展MOSFET)及VDMOS器件(垂直双扩散MOSFET)等功率半导体器件，还需使所述功率半导体器件与基底上设置的其它元件隔开，但是，目前在功率半导体器件周围设置的隔离结构的隔离效果不理想
[0016]本实用新型提供的半导体装置中，半导体基底包括用于形成功率半导体器件的功率器件区以及围绕所述功率器件区设置的隔离结构，所述隔离结构包括围绕所述功率器件区且在远离所述功率器件区的方向依次排布的N个隔离环，N为大于3的整数，该N个隔离环形成多级隔离，能够逐级拦截扩散至隔离结构处的载流子，并且由于N较大，使得各级隔离环均由于载流子饱和而失效的风险很低，因此可以提高功率半导体器件与半导体基底上设置的其它元件之间的隔离效果，此外，通过设置合适的N(如N＝5)以及功率器件区以及各隔离环占据的基底面积，可以在提高所述隔离效果的同时，不会引起半导体装置的面积明显增加。
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Figure CN224653869U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductors, and more particularly to a semiconductor device. Background Technology
[0002] Power semiconductor devices are core components of electrical energy / power processing. They are mainly used in the fields of power conversion and circuit control in power equipment. They can be used for frequency conversion, voltage conversion, current conversion, power amplification and power management, playing a key role in the normal operation of equipment.
[0003] In the manufacturing of power semiconductor devices, in addition to forming power semiconductor devices such as LDMOS (lateral double-diffused MOSFET), DEMOS (drain extended MOSFET) and VDMOS (vertical double-diffused MOSFET) on the substrate, it is also necessary to isolate the power semiconductor devices from other components disposed on the substrate. However, the isolation effect of the isolation structure disposed around the power semiconductor devices is not ideal at present. Utility Model Content
[0004] In order to improve the isolation between power semiconductor devices and other components disposed on the substrate, this invention provides a semiconductor device.
[0005] The semiconductor device provided by this utility model includes:
[0006] A semiconductor substrate includes a power device region for forming a power semiconductor device and an isolation structure disposed around the power device region, the isolation structure including N isolation rings that expand sequentially in a direction away from the power device region, where N is an integer greater than 3.
[0007] Optionally, each of the isolation rings is a doped well formed in the semiconductor substrate, and the doping types of two adjacent isolation rings are opposite.
[0008] Optionally, the isolation structure further includes a first shallow trench isolation structure disposed between the power device region and the isolation ring closest to the power device region.
[0009] Optionally, the isolation structure further includes a second shallow trench isolation structure disposed between two adjacent isolation rings and on the outer side of the isolation ring furthest from the power device region.
[0010] Optionally, N equals 5.
[0011] Optionally, the semiconductor device includes a body region disposed in the power device region and having a first conductivity type doping, a drift region located on both sides of the body region and having a second conductivity type doping, and a first conductivity type doped buried layer located below the body region and the drift region.
[0012] Optionally, the semiconductor substrate includes a substrate and an epitaxial layer formed on the substrate, wherein the power device region and the isolation structure are located in the epitaxial layer.
[0013] Optionally, the semiconductor device includes a second conductivity type doped buried layer disposed on top of the substrate and below the isolation structure and the power device region, the second conductivity type doped buried layer being connected to at least a portion of the lower end of the isolation ring.
[0014] Optionally, the power semiconductor device includes at least one of NLDMOSFET, NVDMOSFET, NDEMOSFET and PDEMOSFET.
[0015] Optionally, the semiconductor device includes BJT devices, CMOS devices, and DMOS power devices integrated on the semiconductor substrate.
[0016] In the semiconductor device provided by this utility model, the semiconductor substrate includes a power device region for forming a power semiconductor device and an isolation structure disposed around the power device region. The isolation structure includes N isolation rings arranged sequentially around the power device region in a direction away from the power device region, where N is an integer greater than 3. These N isolation rings form a multi-level isolation, which can intercept carriers diffused to the isolation structure level by level. Furthermore, since N is relatively large, the risk of each isolation ring failing due to carrier saturation is very low. Therefore, the isolation effect between the power semiconductor device and other components disposed on the semiconductor substrate can be improved. In addition, by setting an appropriate N (e.g., N=5) and the substrate area occupied by the power device region and each isolation ring, the isolation effect can be improved without causing a significant increase in the area of the semiconductor device. Attached Figure Description
[0017] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Detailed Implementation
[0018] The semiconductor device of this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be understood that the drawings in this specification are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this utility model. It should be understood that spatial relative terms are intended to include different orientations in use or operation other than the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (such as rotation), the exemplary term "on" may also include "below" and other orientational relationships.
[0019] Reference Figure 1 This utility model relates to a semiconductor device, which includes a semiconductor substrate 100. The semiconductor substrate 100 includes a power device region A1 for forming a power semiconductor device and an isolation structure 110 disposed around the power device region A1. The isolation structure 110 includes N isolation rings that surround the power device region A1 and expand sequentially in the direction away from the power device region A1, where N is an integer greater than 3.
[0020] The semiconductor device may be any device having the semiconductor substrate 100 described above, such as a wafer, a chip, or a device containing the chip having the semiconductor substrate 100. As an example, the semiconductor device is formed using a BCD process and may include BJT devices, CMOS devices, and DMOS power devices integrated on the semiconductor substrate 100.
[0021] The semiconductor substrate 100 may include known materials such as silicon, germanium, silicon-germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. Optionally, the semiconductor substrate 100 includes a substrate 101 and an epitaxial layer 102 formed on the substrate 101, with the power device region A1 and the aforementioned isolation structure 110 located, for example, on the epitaxial layer 102. The substrate 101 is, for example, a silicon substrate and has a first conductivity type doping, such as P-type doping (P-Si, for example, doped with boron or indium), and the epitaxial layer 102 is, for example, a second conductivity type doping, such as N-type doping (for example, doped with arsenic or phosphorus).
[0022] In some embodiments, the semiconductor device, in addition to the semiconductor substrate 100 described above, also includes a power semiconductor device formed in the power device region A1. The power semiconductor device includes, for example, at least one of NLDMOSFET (i.e., N-type lateral double-diffused MOSFET), NVDMOSFET (i.e., N-type vertical double-diffused MOSFET), NDEMOSFET (i.e., N-type drain extended MOSFET), and PDEMOSFET (i.e., P-type drain extended MOSFET). Figure 1 Two NLD MOSFETs symmetrically arranged in the power device region A1 are shown as an example. (Refer to...) Figure 1The two LDMOSFETs share a body region PBD doped with a first conductivity type (e.g., P-type doping). A body contact region (not shown) heavily doped with the first conductivity type can be formed on top of the body region PBD. Each LDMOSFET includes a drift region NDFT located on one side of the body region PBD and doped with a second conductivity type (e.g., N-type doping), a gate structure formed above the body region PBD and the drift region NDFT, a source region NS (e.g., N-type) formed on top of the body region PBD and heavily doped with the second conductivity type, and a drain region ND formed on top of the drift region NDFT and offset relative to the gate structure by a certain distance and doped with the second conductivity type. The gate structure includes a gate dielectric layer 103 and a gate G stacked sequentially on the surface of the epitaxial layer 102, and also includes sidewalls SP located on the sides of the gate dielectric layer 103 and the gate GT. Optionally, each LDMOSFET further includes a field oxide layer 104 and a field electrode 105. The field oxide layer 104 covers the surface of the drift region NDFT between the drain region ND and the gate G and extends from the side of the gate G to the upper surface of the gate G. The field electrode 105 is formed on the surface of the field oxide layer 104. The field electrode 105 can weaken the surface electric field of the drift region NDFT, which is beneficial to improving the breakdown voltage. Optionally, a first conductivity type doped buried layer BL1 is also formed below the body region PBD and the drift region NDFT. The doping type of the first conductivity type doped buried layer BL1 is opposite to that of the drift region NDFT. The first conductivity type doped buried layer BL1 can be used to balance the charge of the drift region NDFT so that the lateral depletion depth of the drift region NDFT matches the vertical depth.
[0023] like Figure 1 As shown, in the isolation structure 110, each isolation ring is a doped well formed in the semiconductor substrate 100, and the doping types of adjacent isolation rings are opposite. As an example, in the direction away from the power device region A1, the first, third, and fifth isolation rings are medium-voltage P-wells (MPW), and the second and fourth isolation rings are medium-voltage N-wells (MNW). A heavily doped (e.g., P-type heavily doped (P+) or N-type heavily doped (N+)) lead-out region may be formed on the top of each doped well. The doped wells constituting each isolation ring extend, for example, from the surface of the epitaxial layer 102 to the bottom of the epitaxial layer 102.
[0024] Optionally, the semiconductor device further includes a second conductivity type doped buried layer BL2 disposed on top of the substrate 101 and below the isolation structure 110 and the power device region A1. The second conductivity type doped buried layer BL2 can be connected to at least a portion of the lower end of the aforementioned isolation ring. For example, the second conductivity type doped buried layer BL2 is an N-type buried layer that extends from the power device region A1 to both sides and connects to each N-type doped isolation ring (such as...). Figure 1It can be connected to the “MNW” shown, and can also be connected to the P-type doped isolation ring located inside the N-type doped isolation ring (i.e., on the side where the power device region A1 is located). Figure 1 The connection is shown as "MPW".
[0025] Optionally, N is less than or equal to 5, for example, N = 5. When N = 5, the isolation structure 110 includes five isolation rings that surround the power device region A1 and expand sequentially in the direction away from the power device region A1. These five isolation rings form a multi-level isolation, which can intercept carriers diffused to the isolation structure 110 step by step. Compared with three or fewer isolation rings, the isolation effect between the power semiconductor device surrounded by the isolation structure 110 and other components disposed on the semiconductor substrate 100 can be improved. Furthermore, by appropriately adjusting the width of each isolation ring and the distance between devices on the semiconductor substrate 100, the five isolation rings do not significantly increase the area of the semiconductor device and have little impact on the overall size of the semiconductor device.
[0026] like Figure 1 As shown, in some embodiments, the isolation structure 110 may further include a first shallow trench isolation structure STI1 disposed between the power device region A1 and the isolation ring closest to the power device region A1. In other embodiments, the isolation structure 110 may further include a second shallow trench isolation structure STI2 disposed between two adjacent isolation rings and on the outer side of the isolation ring furthest from the power device region A1. By utilizing the first trench isolation structure STI1 and the second trench isolation structure STI2, combined with the aforementioned N isolation rings, the isolation effect between the power semiconductor device surrounded by the isolation structure 110 and other components disposed on the semiconductor substrate 100 can be enhanced.
[0027] In the semiconductor device described in the above embodiments, the semiconductor substrate 100 includes a power device region A1 for forming a power semiconductor device and an isolation structure 110 surrounding the power device region A1. The isolation structure 110 includes N isolation rings that surround the power device region A1 and expand sequentially in the direction away from the power device region A1, where N is an integer greater than 3. These N isolation rings form a multi-level isolation, which can intercept carriers diffused to the isolation structure 110 step by step. Since N is relatively large, the risk of each isolation ring failing due to carrier saturation is very low. Therefore, the isolation effect between the power semiconductor device surrounded by the isolation structure 110 and other components disposed on the semiconductor substrate 100 can be improved. In addition, by setting an appropriate N (e.g., N=5) and reasonably setting the power device region A1, the substrate area occupied by each isolation ring, and the distance between devices on the semiconductor substrate 100, the isolation effect can be improved without significantly increasing the area of the semiconductor device.
[0028] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor substrate includes a power device region for forming a power semiconductor device and an isolation structure disposed around the power device region, the isolation structure including N isolation rings that expand sequentially in a direction away from the power device region, where N is an integer greater than 3.
2. The semiconductor device as claimed in claim 1, characterized in that, Each of the isolation rings is a doped well formed in the semiconductor substrate, and the doping types of two adjacent isolation rings are opposite.
3. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure further includes a first shallow trench isolation structure disposed between the power device region and the isolation ring closest to the power device region.
4. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure also includes a second shallow trench isolation structure disposed between two adjacent isolation rings and on the outer side of the isolation ring furthest from the power device region.
5. The semiconductor device as claimed in claim 1, characterized in that, N equals 5.
6. The semiconductor device as claimed in claim 1, characterized in that, It includes a body region disposed in the power device region and having a first conductivity type doping, a drift region located on both sides of the body region and having a second conductivity type doping, and a first conductivity type doped buried layer located below the body region and the drift region.
7. The semiconductor device as claimed in claim 1, characterized in that, It includes a substrate and an epitaxial layer formed on the substrate, wherein the power device region and the isolation structure are located on the epitaxial layer.
8. The semiconductor device as claimed in claim 7, characterized in that, It includes a second conductivity type doped buried layer disposed on top of the substrate and below the isolation structure and the power device region, the second conductivity type doped buried layer being connected to at least a portion of the lower end of the isolation ring.
9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The power semiconductor device includes at least one of NLDMOSFET, NVDMOSFET, NDEMOSFET and PDEMOSFET.
10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device includes BJT devices, CMOS devices, and DMOS power devices integrated on the semiconductor substrate.