A photovoltaic cell

Abstract

The utility model provides a kind of photovoltaic cell, it is related to photovoltaic technical field to solve the technical problem of low photoelectric conversion efficiency of photovoltaic cell.The photovoltaic cell, including substrate, substrate has first surface, first surface includes first area, second area and third area between first area and second area;First area is stacked with first laminated structure, second area is stacked with second laminated structure, third area is stacked with third laminated structure;Wherein, first laminated structure at least includes first doped silicon-containing layer, second laminated structure at least includes second doped silicon-containing layer;The doping type of first doped silicon-containing layer and second doped silicon-containing layer is opposite;The surface of first laminated structure, second laminated structure, third laminated structure away from substrate is sequentially stacked with laser blocking layer and conductive layer;Wherein, at least part of the part of conductive layer on third area is provided with first discontinuous structure.The photovoltaic cell photoelectric conversion efficiency is high.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic technology, and in particular to a photovoltaic cell. Background Technology

[0002] The statements in this section are merely background information related to this utility model and do not necessarily constitute prior art.

[0003] Heterojunction (HJT) solar cells are mainly composed of a PN heterojunction of silicon and doped amorphous silicon, with an intrinsic amorphous silicon passivation layer embedded at the heterojunction interface. Back contact (BC) cell technology is used to improve the photoelectric conversion performance of heterojunction cells, resulting in back contact heterojunction (HBC) solar cells.

[0004] In HBC cells, the overlap of n-type electron collecting layers and p-type hole collecting layers is unavoidable. It is necessary to electrically insulate the n-type conductive layer and p-type conductive layer (transparent conductive oxide (TCO) thin film) in the overlap region (isolation region); otherwise, internal short circuits or significant leakage problems may occur. In related fabrication processes, laser etching is typically used to remove at least a portion of the TCO layer in the overlap region (isolation region) to achieve electrical isolation. However, laser etching requires high energy and can easily damage the active layer of the cell, reducing the photoelectric conversion efficiency of the HBC cell. Utility Model Content

[0005] The purpose of this invention is to provide a photovoltaic cell to solve the technical problem of low photoelectric conversion efficiency of photovoltaic cells.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] In a first aspect, the present invention provides a photovoltaic cell, including a substrate, the substrate having a first surface, the first surface including a first region, a second region and a third region located between the first region and the second region;

[0008] A first stacked structure is stacked on the first region, a second stacked structure is stacked on the second region, and a third stacked structure is stacked on the third region; wherein, the first stacked structure includes at least a first doped silicon-containing layer, and the second stacked structure includes at least a second doped silicon-containing layer; the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are opposite.

[0009] The first stacked structure, the second stacked structure, and the third stacked structure all have a laser blocking layer and a conductive layer located outside the laser blocking layer stacked sequentially on their surfaces away from the substrate; wherein, at least a portion of the conductive layer located in the third region has a first discontinuity structure.

[0010] According to at least one embodiment of the present invention, the band gap of the laser blocking layer is greater than 2eV and less than 4eV.

[0011] According to at least one embodiment of the present invention, the laser blocking layer comprises a conductive film or a non-conductive film.

[0012] When the laser blocking layer is the non-conductive film, the non-conductive film is a membrane layer with a nanoscale or microscale porous structure.

[0013] According to at least one embodiment of the present invention, the pore size of the porous structure of the non-conductive film ranges from 10 nm to 2000 nm.

[0014] According to at least one embodiment of the present invention, the thickness of the laser blocking layer is greater than or equal to 30 nm and less than or equal to 500 nm.

[0015] According to at least one embodiment of the present invention, when the laser blocking layer includes the conductive film, the material of the conductive film includes at least one of copper, aluminum, indium oxide, tin oxide, cadmium oxide, doped zinc oxide, and titanium nitride, and the doping element includes one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine; or,

[0016] When the laser blocking layer includes the non-conductive film, the material of the non-conductive film includes one of titanium dioxide, zinc oxide, silicon nitride, or silicon oxide.

[0017] According to at least one embodiment of the present invention, the portion of the laser blocking layer opposite to the first discontinuity structure is formed with a groove or a second discontinuity structure.

[0018] According to at least one embodiment of the present invention, the width of the first discontinuous structure ranges from 50 μm to 150 μm; and / or,

[0019] The width of the second discontinuous structure ranges from 50 μm to 150 μm;

[0020] The width direction of the first discontinuous structure and the second discontinuous structure refers to the arrangement direction from the first region to the second region.

[0021] According to at least one embodiment of the present invention, the first stacked structure further includes a tunneling oxide layer, the tunneling oxide layer being located between the substrate and the first doped silicon-containing layer; and / or,

[0022] The second stacked structure further includes an intrinsic silicon-containing layer, the intrinsic silicon-containing layer being located between the substrate and the second doped silicon-containing layer; and / or,

[0023] Along a direction away from the substrate, the third stacked structure sequentially includes the tunneling oxide layer, the first doped silicon-containing layer, the insulating isolation layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer.

[0024] According to at least one embodiment of the present invention, a protective layer is stacked on the side of the conductive layer opposite to the laser blocking layer, and the material of the protective layer includes at least one of silicon nitride, aluminum oxide and silicon dioxide.

[0025] Secondly, this utility model also provides a method for preparing a photovoltaic cell, comprising:

[0026] A substrate is provided, the substrate having a first surface, the first surface including a first region, a second region, and a third region located between the first region and the second region;

[0027] A first stacked structure is stacked on the first region, a second stacked structure is stacked on the second region, and a third stacked structure is stacked on the third region; wherein the first stacked structure includes at least a first doped silicon-containing layer, and the second stacked structure includes at least a second doped silicon-containing layer; the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are opposite.

[0028] A laser blocking layer and a conductive layer are sequentially stacked on the surfaces of the first stacked structure, the second stacked structure, and the third stacked structure that are away from the substrate;

[0029] A first discontinuity structure is created by laser etching at least a portion of the conductive layer located in the third region.

[0030] According to at least one embodiment of the present invention, the laser wavelength in the laser etching process is 300nm to 400nm, or 495nm to 570nm, and the duration of the laser pulse is one of nanosecond, picosecond, or femtosecond.

[0031] According to at least one embodiment of the present invention, when a first stacked structure is stacked on the first region, a second stacked structure is stacked on the second region, and a third stacked structure is stacked on the third region, the method includes:

[0032] A tunneling oxide layer, a first doped silicon-containing layer, and an insulating isolation layer are sequentially stacked on the first region and the third region.

[0033] An intrinsic silicon-containing layer and a second doped silicon-containing layer are sequentially stacked on the second region and the insulating isolation layer;

[0034] Remove the second doped silicon layer, the intrinsic silicon layer, and the insulating isolation layer from the first region.

[0035] According to at least one embodiment of the present invention, when a tunneling oxide layer, a first doped silicon-containing layer, and an insulating isolation layer are sequentially stacked on the first region and the third region, the method includes:

[0036] The tunneling oxide layer, the first doped silicon-containing layer, and the insulating isolation layer are sequentially stacked on the first surface;

[0037] The tunneling oxide layer, the first doped silicon-containing layer, and the insulating isolation layer on the second region are removed, and a first textured structure is formed on the portion of the substrate located in the second region, and a second textured structure is formed on the second surface of the substrate; wherein the second surface is opposite to the first surface.

[0038] According to at least one embodiment of the present invention, before stacking a laser blocking layer on the first surface of the first stacked structure, the second stacked structure, and the third stacked structure away from the substrate, the fabrication method further includes:

[0039] A passivation layer and an antireflection layer are sequentially stacked on the second velvet structure.

[0040] According to at least one embodiment of the present invention, after forming a first discontinuity structure at least a portion of the conductive layer located in the third region by laser etching, the fabrication method further includes:

[0041] A protective layer is stacked on the side of the conductive layer opposite to the laser blocking layer. The material of the protective layer includes one of silicon nitride, aluminum oxide, or silicon dioxide.

[0042] In one or more technical solutions provided in the exemplary embodiments of this utility model, at least one of the following beneficial effects can be achieved.

[0043] The photovoltaic cell of an exemplary embodiment of this utility model has a first region, a second region, and a third region separating the two regions on a first surface (back side) of a substrate. One of the first and second regions can be a P-region, and the other can be an N-region. Specifically, a first stacked structure is stacked on the first region, a second stacked structure is stacked on the second region, and a third stacked structure is stacked on the third region. A laser blocking layer is disposed between the first surface of the first, second, and third stacked structures facing away from the substrate and the conductive layer. When a first discontinuous structure is formed by laser grooving at least a portion of the conductive layer located in the third region, the laser blocking layer can block laser energy from being conducted to the functional layers (each stacked structure) of the cell, thereby protecting the functional layers from damage as much as possible, thus ensuring the photoelectric conversion efficiency of the formed photovoltaic cell.

[0044] Furthermore, in the exemplary embodiment of this invention, the laser blocking layer of the photovoltaic cell is laid across the entire stacked structure of the first surface, resulting in a more uniform laser blocking layer and a more stable property. For example, compared to partially laying the laser blocking layer only in the third region, the stress in the laser blocking layer and the conductive layer is lower. Simultaneously, the fact that the laser blocking layer is laid across the entire stacked structure of the first surface allows for a larger laser processing window during laser grooving, reducing the requirement for laser positioning accuracy and thus simplifying the production process. Attached Figure Description

[0045] The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description thereof, serve to explain the principles of the present invention. These drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification.

[0046] Figure 1 This is a schematic diagram of the photovoltaic cell preparation method according to an embodiment of the present invention;

[0047] Figures 2 to 12 These are schematic cross-sectional views of the process structure after each step in the photovoltaic cell preparation method according to the embodiments of this utility model.

[0048] Figure 13 This is a schematic diagram of the structure of the laser blocking layer of a photovoltaic cell according to an embodiment of the present invention.

[0049] Figure label:

[0050] 10. Substrate; 11. First surface; 12. Second surface; 11a. First textured surface structure; 12a. Second textured surface structure;

[0051] 21. First doped silicon-containing layer; 22. Tunneling oxide layer; 23. Insulating isolation layer;

[0052] 31. Intrinsic silicon-containing layer; 32. Second-doped silicon-containing layer;

[0053] 41. Passivation layer; 42. Anti-reflection layer;

[0054] 50. Conductive layer; 51. First discontinuity structure;

[0055] 61. First electrode; 62. Second electrode;

[0056] 70. Laser blocking layer;

[0057] 80. Protective layer. Detailed Implementation

[0058] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0059] High-conversion-capacity (HBC) cells can achieve a maximum photoelectric conversion efficiency of 27.1%. Both the P-region and N-region are located on the back side of the substrate and require a conductive layer, such as a TCO layer, to cover them. In the HBC cell fabrication process, the TCO layer needs to be broken at the interface between the P-region and N-region for insulation. Related technologies use laser grooving to break this interface, but this process damages the functional layer beneath the TCO layer, reducing the cell's photoelectric conversion efficiency. Alternatively, using etchant printing to break the TCO layer at the interface in one step is difficult to control in terms of etching precision, easily leading to overlap of the functional layers in the P and N regions. Furthermore, the chemical etchant process has poor stability and is prone to leaving reagent residues, limiting the cell's current collection capacity.

[0060] To address the aforementioned problems, the photovoltaic cell provided in the exemplary embodiment of this invention forms a laser blocking layer between the TCO layer and the functional layer. This layer protects the functional layer from damage during laser etching of the TCO layer. Therefore, it achieves both reduced laser etching damage and effective control of leakage current.

[0061] It should be noted that the photovoltaic cell and preparation method provided in the exemplary embodiments of this utility model are applicable not only to HBC cells, but also to other types of photovoltaic cells using BC cell technology.

[0062] like Figure 12 As shown, an exemplary embodiment of the present invention provides a photovoltaic cell, including a substrate 10, the substrate 10 having a first surface 11, the first surface 11 including a first region E1, a second region E2 and a third region E3 located between the first region E1 and the second region E2.

[0063] For example, a first stacked structure is stacked on a first region, a second stacked structure is stacked on a second region, and a third stacked structure is stacked on a third region.

[0064] Along the direction away from the substrate 10, the first stacked structure sequentially comprises a tunneling oxide layer 22 and a first doped silicon-containing layer 21; the second stacked structure sequentially comprises an intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32; and the third stacked structure sequentially comprises a tunneling oxide layer 22, a first doped silicon-containing layer 21, an insulating isolation layer 23, an intrinsic silicon-containing layer 31, and a second doped silicon-containing layer 32. The doping types of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 are opposite.

[0065] For example, the substrate 10 can be a p-type silicon substrate or an n-type silicon substrate. One of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 is a p-type doped silicon-containing layer, and the other is an n-type doped silicon-containing layer. The following description uses an n-type silicon substrate and an n-type doped first silicon-containing layer 21 as an example.

[0066] It should be noted that the front side (light-receiving surface) of the substrate 10 is the second surface 12, and the back side is the first surface 11.

[0067] The first stacked structure, the second stacked structure, and the third stacked structure all have a laser blocking layer 70 and a conductive layer 50 located outside the laser blocking layer 70 stacked sequentially on the surfaces away from the substrate 10; wherein, at least a portion of the conductive layer 50 located in the third region has a first discontinuity structure 51.

[0068] In practical applications, after stacking the laser blocking layer 70 and the conductive layer 50 sequentially on the three-layer structure, a first discontinuity structure 51 needs to be formed on the conductive layer 50 in the third region by laser etching to separate the conductive layers 50 with opposite polarities into two mutually insulating parts, preventing internal short circuits or leakage. During the laser etching process, even though the laser energy is relatively large and the conductive layer 50 is generally a transparent material, the laser blocking layer 70 located on one side of the conductive layer 50 can absorb the laser energy, thereby reducing damage to the functional layers (three-layer structure). Furthermore, the manufacturing process of this photovoltaic cell does not require the use of chemical paste to etch the conductive layer 50 to form the first discontinuity structure 51, the etching precision is easier to control, which can improve the reliability of the photovoltaic cell, and the chemical cleaning process is omitted, reducing costs.

[0069] Figure 13 This is a schematic diagram of the laser blocking layer 70 of a photovoltaic cell according to an embodiment of the present invention. Figure 13As shown, in the photovoltaic cell provided by the exemplary embodiment of this utility model, the band gap of the laser blocking layer 70 is greater than 2eV and less than 4eV. When the band gap is less than 2eV, commonly used laser wavelengths can easily penetrate the layer, thus failing to provide protection. When the band gap is greater than 4eV, the conductivity of the material forming the laser blocking layer 70 is relatively low, which increases the series resistance of the photovoltaic cell, hinders the transport and extraction of electrons, and reduces the efficiency of the photovoltaic cell. The band gap of the laser blocking layer 70 can optionally be greater than 2eV and less than 3.5eV, for example, it can be 2.1eV, 2.2eV, 2.3eV, 2.5eV, 2.7eV, 2.9eV, 3eV, 3.1eV, 3.2eV, 3.3eV, 3.4eV, etc.

[0070] The laser blocking layer 70 can be made of transparent or opaque material. Considering that the current needs to be able to be smoothly discharged from the battery, the laser blocking layer 70 includes either a conductive film or a non-conductive film. When the laser blocking layer 70 is a non-conductive film, the non-conductive film is a film layer with a nanoscale or microscale porous structure.

[0071] It should be noted that when the laser blocking layer 70 is a conductive film, it may or may not have a nano- or micro-scale porous structure.

[0072] For example, a non-conductive film with a band gap greater than 3 eV and less than 3.5 eV can have a micron-scale porous structure; a non-conductive film with a band gap greater than 2 eV and less than 3 eV can have a nano-scale porous structure.

[0073] For example, the pore size of the porous structure of the non-conductive film ranges from 10 nm to 2000 nm, and optionally includes 20 nm, 30 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 500 nm, 700 nm, 900 nm, 1000 nm, 1200 nm, 1400 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, etc. The conductive layer 50 can conduct current from the battery through the porous structure with the above-mentioned pore size.

[0074] For example, the thickness of the laser blocking layer 70 is greater than or equal to 30 nm and less than or equal to 500 nm, such as 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 480 nm, etc., to absorb the penetrating energy of the laser. When the thickness of the laser blocking layer 70 is less than 30 nm, the laser can easily penetrate the layer, failing to function as a protective layer. Using a laser blocking layer with a thickness of less than 500 nm can effectively protect against commonly used lasers of up to 40 W. However, if the layer thickness is too large, the production cost is high.

[0075] For example, the conductive film is made of at least one of copper, aluminum, indium oxide, tin oxide, cadmium oxide, doped zinc oxide, and titanium nitride, and the doping element includes one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine.

[0076] For example, the material of the non-conductive film includes at least one of titanium dioxide, zinc oxide, silicon nitride, and silicon oxide.

[0077] In some embodiments, the portion of the laser blocking layer 70 opposite to the first interruption structure 51 is formed with a groove or a second interruption structure.

[0078] In practical applications, during the laser etching process, the laser energy may be relatively high when the first discontinuity structure 51 is formed at the corresponding location of the conductive layer 50, thereby forming a groove on the laser blocking layer 70 until it is completely cut off. Based on this, a higher energy laser can be used to expand the process window without damaging the internal functional layers in the presence of the laser blocking layer 70.

[0079] To prevent leakage or short circuits between the P and N regions, the width of the first interruption structure 51 ranges from 50 μm to 150 μm, for example, it can be 60 μm, 70 μm, 90 μm, 110 μm, 130 μm, 140 μm, etc. For example, the width of the third region is 50 μm to 200 μm. That is, the conductive layer 50 on the third region can be completely removed or partially cut off.

[0080] It should be noted that the width direction of the first discontinuous structure 51, the second discontinuous structure, and the third region refers to the arrangement direction from the first region to the second region.

[0081] like Figure 12As shown, in some embodiments, a protective layer 80 is stacked on the side of the conductive layer 50 facing away from the laser blocking layer 70. The protective layer 80 is made of silicon nitride, aluminum oxide, or silicon dioxide. This protective layer 80 is a non-conductive film layer that can provide water-proof protection for the first surface 11 of the battery and enhance back reflection capability. Specifically, some light penetrates the photovoltaic cell and reaches the back glass, but cannot be utilized by the photovoltaic cell. By providing the aforementioned protective layer 80 on the side of the conductive layer 50 facing away from the substrate, this portion of the penetrated light can be reflected back into the photovoltaic cell and absorbed again, thereby enhancing the back reflection capability of the photovoltaic cell.

[0082] In some embodiments, the substrate 10 has a second surface 12 opposite to the first surface 11, on which a passivation layer 41 and an antireflection layer 42 are stacked sequentially.

[0083] In some embodiments, the second region E2 and the second surface 12 of the substrate 10 are respectively formed with a textured structure.

[0084] In some embodiments, the tunneling oxide layer 22 is made of silicon oxide and has a thickness of 0.5 nm to 3 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm.

[0085] In some embodiments, the first doped silicon layer 21 is made of n-type doped polycrystalline silicon and has a thickness of 30nm to 300nm, such as 30nm, 100nm, 150nm, 200nm, 250nm or 300nm.

[0086] In some embodiments, the insulating layer 23 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0087] In some embodiments, the intrinsic silicon-containing layer 31 is made of at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0088] In some embodiments, the material of the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0089] In some embodiments, the conductive layer 50 is made of at least one of transparent conductive metal oxide or transparent conductive metal nitride.

[0090] Figure 1 This is a schematic diagram of the photovoltaic cell preparation method according to an embodiment of the present invention; Figures 2 to 12 This is a schematic cross-sectional view of the process structure after each step in the photovoltaic cell fabrication method according to the embodiments of this utility model. For example... Figure 1As shown in the exemplary embodiment of this utility model, a method for preparing a photovoltaic cell is provided, which may include the following steps:

[0091] Step 101: Provide a substrate 10, the substrate 10 having a first surface 11 and a second surface 12 opposite to each other, the first surface 11 including a first region E1, a second region E2 and a third region E3 located between the first region E1 and the second region E2, such as Figure 2 As shown.

[0092] It should be noted that, Figure 2 The first surface 11 of the substrate 10 does not have only one set of first region E1, second region E2 and third region E3, but may have multiple sets of the above-mentioned regions.

[0093] For example, the first surface 11 may have a first region E1, a third region E3, a second region E2, a third region E3, a first region E1, a third region E3, and a second region E2 arranged sequentially; or, the first surface 11 may have a first region E1, a third region E3, a second region E2, a third region E3, a second region E2, a third region E3, and a first region E1 arranged sequentially, that is, each group of regions has a third region E3.

[0094] Step 102: Stack a first stacked structure on a first region, stack a second stacked structure on a second region, and stack a third stacked structure on a third region; wherein the first stacked structure includes at least a first doped silicon-containing layer 21, and the second stacked structure includes at least a second doped silicon-containing layer 32; the doping types of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 are opposite.

[0095] Step 1021: Texturing and polishing are performed on the first surface 11 and the second surface 12 of the substrate 10 (silicon substrate) to form a tower base structure.

[0096] In practical applications, a textured surface can be formed on both the first surface 11 and the second surface 12 of the substrate 10 through alkaline washing. Simultaneously, alkaline washing removes contaminants, impurities, and metal ions from the surface of the substrate 10, followed by polishing. The alkaline etching solution used for the alkaline washing can be potassium hydroxide, sodium hydroxide, etc. The tower base structure is the bottom structure remaining after the textured surface has been polished.

[0097] Step 1022: A tunneling oxide layer 22, a first doped silicon-containing layer 21, and an insulating isolation layer 23 are sequentially stacked on the first surface 11 to form a structure as shown in the figure. Figure 3 The structure shown.

[0098] A tunneling oxide layer 22, a first doped silicon-containing layer 21, and an insulating isolation layer 23 can be deposited sequentially on the substrate 10 over the entire area of ​​the first surface 11.

[0099] The deposition process can be carried out by any one of the following deposition methods or a combination of multiple deposition methods: vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0100] The following example illustrates the formation of an n-region (negative electrode region) in the first region E1, a p-region (positive electrode region) in the second region E2, and an intervening region between the p-region and the n-region in the third region E3.

[0101] For example, the tunneling oxide layer 22 is a silicon oxide layer with a thickness of 0.5 nm to 3.0 nm, such as 0.7 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, etc. By reasonably controlling the thickness of the tunneling oxide layer 22, the collection probability of majority carriers can be increased, thereby improving the photoelectric conversion efficiency of the battery.

[0102] For example, the material of the first doped silicon layer 21 is n-type doped polycrystalline silicon, and the thickness is 30nm to 300nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.

[0103] For example, the insulating layer 23 is made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0104] Step 1023: Remove the insulating layer 23 on the second region E2 to form as shown. Figure 4 The structure shown; the first doped silicon-containing layer 21 and tunneling oxide layer 22 on the second region E2 are removed to form the structure shown. Figure 5 The structure shown.

[0105] A combination of one or more methods, such as laser lift-off or chemical cleaning etching, is used to remove the tunneling oxide layer 22, the first doped silicon-containing layer 21, and the insulating isolation layer 23 on the second region E2.

[0106] For example, the insulating isolation layer 23 on the second region E2 is removed by laser film opening, and the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 are removed by chemical etching; further, a textured structure is formed on the second region E2 and the second surface 12 of the substrate 10 by texturing.

[0107] Specifically, after removing the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 by alkaline etching, a first textured structure 11a and a second textured structure 12a are formed on the exposed substrate 10 in the second region E2 and on the second surface 12, respectively, through texturing. These textured structures can be pyramidal in shape. The chemical etching can include alkaline solutions and acid solutions; the alkaline solution can be sodium hydroxide, and the acid solution can be hydrofluoric acid or nitric acid. The chemical reagent used in the texturing process can also be an alkaline solution.

[0108] In another optional embodiment, the insulating isolation layer 23, the tunneling oxide layer 22 and the first doped silicon-containing layer 21 on the second region E2 are removed by laser film opening; and a textured structure is formed on the second region E2 and the second surface 12 of the substrate 10 by texturing.

[0109] The specific process of laser film removal (laser ablation) involves emitting a laser beam from a laser source and using the laser to bombard the surface to remove the corresponding layer.

[0110] Step 1024a: An intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 are sequentially stacked on the first textured structure 11a of the second region E2, the insulating isolation layer 23 of the third region E3, and the insulating isolation layer 23 of the first region E1, to form a structure as shown in the figure. Figure 6 The structure shown.

[0111] An intrinsic silicon-containing layer 31 is first deposited on the first textured structure 11a of the second region E2, the insulating isolation layer 23 of the third region E3, and the insulating isolation layer 23 of the first region E1 by chemical deposition, and then a second doped silicon-containing layer 32 is deposited.

[0112] For example, the intrinsic silicon-containing layer 31 is made of at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide. For instance, the intrinsic silicon-containing layer 31 is a single layer with the same properties, or a multilayer or stack of several different properties, or a mixture of silicon-containing thin films, such as microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0113] For example, the second doped silicon-containing layer 32 is at least one of p-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide. For instance, it is a single layer with the same properties or a multilayer or stack of several types of silicon-containing thin films with different properties, such as boron-doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0114] For example, the thickness of the second doped silicon-containing layer 32 is 30nm to 300nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.

[0115] Step 1024b: Passivation layer 41 and antireflection layer 42 are sequentially stacked on the textured surface of the second surface 12 to form a structure as shown in the figure. Figure 6 The structure shown.

[0116] A passivation layer 41 is first deposited on the textured surface (second textured surface 12a) of the second surface 12 by chemical deposition, followed by the deposition of an antireflection layer 42.

[0117] For example, the passivation layer 41 is one of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, or a combination of the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32, wherein the thickness of the intrinsic silicon-containing layer 31 is 1 nm to 15 nm, and the thickness of the second doped silicon-containing layer 32 is 0 nm to 15 nm.

[0118] For example, the antireflection layer 42 is made of at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide, and has a thickness of 40nm to 200nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 190nm, etc.

[0119] It should be noted that the passivation layer 41 formation step in this step can be carried out simultaneously with the formation of the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 in step 1024a, thereby shortening the process flow and simplifying the operation.

[0120] Step 1025: Removing the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the insulating isolation layer 23 on the first region E1 includes: removing the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 on the first region E1 by laser film opening; removing the insulating isolation layer 23 on the first region E1 by alkaline washing, forming as shown in the figure. Figure 7 The structure shown.

[0121] In practical applications, on the first region E1, the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 are first removed by laser film opening; then the insulating isolation layer 23 is etched away by alkaline washing, such as sodium hydroxide or potassium hydroxide solution, to expose the first doped silicon-containing layer 21.

[0122] Step 103: A laser blocking layer 70 and a conductive layer 50 are sequentially stacked on the first surface 11 of the first stacked structure, the second stacked structure, and the third stacked structure away from the substrate 10.

[0123] Specifically, laser blocking layers 70 are stacked on the second doped silicon-containing layer 32 in the second region E2, the second doped silicon-containing layer 32 in the third region E3, and the first doped silicon-containing layer 21 in the first region E1, forming a laser blocking layer 70. Figure 8 The structure shown is then stacked with a conductive layer 50 to form a structure as shown. Figure 9 The structure shown.

[0124] Step 1031: On the structural surface formed on the first surface 11 of the substrate 10 in step 1025, a porous laser blocking layer 70 with nanometer or micrometer pores is formed by methods such as scraping, spin coating, and evaporation. Its two-dimensional morphology is as follows: Figure 13 As shown.

[0125] For example, the band gap of the laser blocking layer 70 is greater than 2 eV and less than 4 eV. When the band gap is less than 2 eV, commonly used laser wavelengths can easily penetrate the layer, thus failing to provide protection. When the band gap is greater than 4 eV, the conductivity of the material forming the laser blocking layer 70 is relatively low, which will increase the series resistance of the photovoltaic cell, hinder the transport and extraction of electrons, and reduce the efficiency of the photovoltaic cell. The band gap of the laser blocking layer 70 can optionally be greater than 2 eV and less than 3.5 eV, for example, it can be 2.1 eV, 2.2 eV, 2.3 eV, 2.5 eV, 2.7 eV, 2.9 eV, 3 eV, 3.1 eV, 3.2 eV, 3.3 eV, 3.4 eV, etc.

[0126] Considering that current needs to be able to be smoothly discharged from the battery, the laser blocking layer 70 can be a transparent or opaque material, including a conductive film or a non-conductive film; wherein, when the laser blocking layer 70 is a non-conductive film, the non-conductive film is a film layer with a nanoscale or microscale porous structure.

[0127] It should be noted that when the laser blocking layer 70 is a conductive film, it may or may not have a nano- or micro-scale porous structure.

[0128] For example, a non-conductive film with a band gap greater than 3 eV and less than 3.5 eV can have a micron-scale porous structure; a non-conductive film with a band gap greater than 2 eV and less than 3 eV can have a nano-scale porous structure.

[0129] For example, the pore size of the porous structure of the non-conductive film ranges from 10 nm to 2000 nm, and optionally includes 20 nm, 30 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 500 nm, 700 nm, 900 nm, 1000 nm, 1200 nm, 1400 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, etc. The conductive layer 50 can conduct current from the battery through the porous structure with the aforementioned pore size, and the pore size of the laser blocking layer 70 does not affect the blocking effect of the laser blocking layer 70, effectively blocking laser light and thus protecting other functional layers.

[0130] For example, the thickness of the laser blocking layer 70 is greater than or equal to 30 nm, so that it can absorb the penetrating energy of the laser.

[0131] For example, the conductive film may be made of copper, aluminum, indium oxide, tin oxide, cadmium oxide, doped zinc oxide or titanium nitride, and the doping element may be one of indium, tin, calcium, aluminum, cadmium, zinc, cerium or fluorine.

[0132] For example, the material of the non-conductive film includes one of titanium dioxide, zinc oxide, silicon nitride, or silicon oxide.

[0133] Step 1032: A conductive layer 50 is formed on the laser blocking layer 70 by methods such as chemical deposition and magnetron sputtering.

[0134] The conductive layer 50 is made of at least one of transparent conductive metal oxide or transparent conductive metal nitride.

[0135] Specifically, the conductive layer 50 is a TCO film layer, which is a multilayer or stacked layer or mixture of one or more doped metal oxides or nitrides. The metal oxides can be indium oxide, tin oxide, zinc oxide, cadmium oxide, or titanium nitride, and the metal nitrides can be titanium nitride. The doping elements can be indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine.

[0136] Step 104: A first discontinuity structure 51 is formed at least a portion of the conductive layer 50 located in the third region by laser etching, forming a structure as shown in the figure. Figure 10 The structure shown.

[0137] In practical applications, a green laser with a wavelength of about 495 to 570 nm (nanosecond, picosecond, or femtosecond) or an ultraviolet laser with a wavelength of about 300 to 400 nm (nanosecond, picosecond, or femtosecond) is used to groove the conductive layer 50 in the third region to form the first discontinuous structure 51.

[0138] In some embodiments, in addition to forming the first discontinuity structure 51, a groove or a second discontinuity structure is formed on the laser blocking layer 70 at the location opposite to the first discontinuity structure 51.

[0139] For example, the portion of the conductive layer 50 opposite to the third region E3 is partially etched away, leaving a portion of the conductive layer 50 on the third region E3. This allows light inside the battery to pass from a high refractive index to a low refractive index, increasing the reflectivity of the internal light and thus increasing the secondary absorption of light and improving the utilization rate of sunlight.

[0140] Step 105: Form metal electrodes on the structures in the first region E1 and the second region E2 respectively, forming as shown in the figure. Figure 11 The structure shown.

[0141] In practical applications, a first electrode 61 is disposed on the conductive layer 50 in the first region E1; and a second electrode 62 is disposed on the conductive layer 50 in the second region E2.

[0142] The corresponding metal electrodes are prepared on the first region E1 and the second region E2 by screen printing electrode paste, electroplating, or transfer printing. For example, one end of the first electrode 61 is located outside the conductive layer 50, and the other end is electrically connected to the conductive layer 50; one end of the second electrode 62 is located outside the conductive layer 50, and the other end is electrically connected to the conductive layer 50, thereby forming a photovoltaic cell.

[0143] For example, when the first doped silicon layer 21 is a boron-doped silicon layer, the first electrode 61 is a positive electrode, and correspondingly, the second electrode 62 is a negative electrode.

[0144] In some embodiments, when the first doped silicon layer 21 is a phosphorus-doped silicon layer, the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0145] For example, the first electrode 61 and the second electrode 62 can be one or more stacks of silver electrode, silver alloy electrode, copper electrode, copper alloy electrode, nickel / copper / silver multilayer electrode.

[0146] Step 106: Stack a protective layer 80 on the side of the conductive layer 50 facing away from the laser blocking layer 70. The protective layer 80 is made of one of silicon nitride, aluminum oxide, or silicon dioxide, forming a structure as shown in the figure. Figure 12 The structure shown is illustrated. The protective layer 80 can provide water-proof protection for the first surface 11 and enhance back reflection capability. Specifically, some light penetrates the photovoltaic cell and reaches the back glass, but cannot be utilized by the photovoltaic cell. By providing the aforementioned protective layer 80 on the side of the conductive layer 50 away from the substrate, the transmitted light can be reflected back into the photovoltaic cell and absorbed and utilized again, thereby enhancing the back reflection capability of the photovoltaic cell.

[0147] The advantages of the above-mentioned photovoltaic cell preparation method over existing technologies are the same as those of the photovoltaic cells themselves, and will not be repeated here.

[0148] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating the present invention and are not intended to limit the scope of the present invention. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present invention.

Claims

1. A photovoltaic cell, characterized in that, The substrate includes a substrate having a first surface, the first surface including a first region, a second region and a third region located between the first region and the second region; A first stacked structure is stacked on the first region, a second stacked structure is stacked on the second region, and a third stacked structure is stacked on the third region; wherein, the first stacked structure includes at least a first doped silicon-containing layer, and the second stacked structure includes at least a second doped silicon-containing layer; the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are opposite. The first stacked structure, the second stacked structure, and the third stacked structure all have a laser blocking layer and a conductive layer located outside the laser blocking layer stacked sequentially on their surfaces away from the substrate; wherein, at least a portion of the conductive layer located in the third region has a first discontinuity structure.

2. The photovoltaic cell according to claim 1, characterized in that, The band gap of the laser blocking layer is greater than 2 eV and less than 4 eV.

3. The photovoltaic cell according to claim 2, characterized in that, The laser blocking layer includes either a conductive film or a non-conductive film. When the laser blocking layer is the non-conductive film, the non-conductive film is a membrane layer with a nanoscale or microscale porous structure.

4. The photovoltaic cell according to claim 3, characterized in that, The pore size of the porous structure of the non-conductive film ranges from 10 nm to 2000 nm.

5. The photovoltaic cell according to claim 3, characterized in that, The thickness of the laser blocking layer is greater than or equal to 30 nm and less than or equal to 500 nm.

6. The photovoltaic cell according to claim 3, characterized in that, When the laser blocking layer includes the conductive film, the conductive film is made of one of copper, aluminum, indium oxide, tin oxide, cadmium oxide, doped zinc oxide, and titanium nitride, and the doping element includes one of indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine; or, When the laser blocking layer includes the non-conductive film, the material of the non-conductive film includes one of titanium dioxide, zinc oxide, silicon nitride, and silicon oxide.

7. The photovoltaic cell according to claim 3, characterized in that, The portion of the laser blocking layer opposite to the first discontinuity structure has a groove or a second discontinuity structure.

8. The photovoltaic cell according to claim 7, characterized in that, The width of the first discontinuous structure ranges from 50 μm to 150 μm; and / or, The width of the second discontinuous structure ranges from 50 μm to 150 μm; The width direction of the first discontinuous structure and the second discontinuous structure refers to the arrangement direction from the first region to the second region.

9. The photovoltaic cell according to claim 1, characterized in that, The first stacked structure further includes a tunneling oxide layer located between the substrate and the first doped silicon-containing layer; and / or, The second stacked structure further includes an intrinsic silicon-containing layer, the intrinsic silicon-containing layer being located between the substrate and the second doped silicon-containing layer; and / or, Along a direction away from the substrate, the third stacked structure includes the tunneling oxide layer, the first doped silicon-containing layer, the insulating isolation layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer disposed sequentially.

10. The photovoltaic cell according to claim 9, characterized in that, A protective layer is stacked on the side of the conductive layer opposite to the laser blocking layer. The material of the protective layer includes one of silicon nitride, aluminum oxide, and silicon dioxide.

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