Packaging structure and electronic device

Abstract

The utility model discloses a kind of packaging structure and electronic equipment, applied to semiconductor technical field.The utility model packaging structure mainly with glass and wafer itself as support, first redistribution layer is made on the substrate of photoelectric sensing chip by TSV technology, product is welded on second redistribution layer by flip, packaging structure does not need WB wire, photoelectric sensing chip is smaller to outward expansion size, so that the size advantage of this packaging structure is much larger than iBGA packaging structure;More I / O is led out to the back of photoelectric sensing chip from solder pad by the mode of redistribution layer with TSV technology, conductive bump is formed on the back of photoelectric sensing chip, and is welded in another layer size larger redistribution layer, in this way fan-out is done, to make larger solder ball and wider solder ball pitch, solve the contradiction problem of more I / O quantity and small packaging size.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure and electronic device. Background Technology

[0002] WLCSP (Wafer Level Chip Scale Packaging) packaging structures are packaged and diced directly on the wafer, eliminating the need for a traditional substrate, resulting in extremely small package sizes. However, due to the small size, I / O (Input / Output) can only be brought out through solder balls distributed in a limited area on the chip edge or surface, greatly limiting the number of I / O pins.

[0003] The iBGA (Image Sensor Ball Grid Array) package structure uses an additional substrate onto which the chip is flip-chip bonded. I / O pins are brought out through an array of solder balls beneath the substrate, resulting in a large number of I / O pins. However, the substrate itself increases the area and thickness of the package structure and needs to accommodate a larger array of solder balls, leading to a larger package size. Therefore, a package structure is needed to resolve the contradiction between a large number of I / O pins and a small package size in existing technologies. Utility Model Content

[0004] In view of this, the purpose of this utility model is to provide a packaging structure and electronic device to solve the contradiction between the large number of I / Os and the small package size in the prior art.

[0005] To solve the above-mentioned technical problems, this utility model provides a packaging structure, including: a photoelectric sensor chip, glass, a first wiring layer, a second wiring layer, conductive bumps, and solder balls;

[0006] The glass is disposed above the photoelectric sensing chip;

[0007] The upper surface of the photoelectric sensor chip is provided with a photosensitive area and a plurality of pads surrounding the photosensitive area; the side surface and the lower surface of the photoelectric sensor chip are also provided with a first super-wiring layer, the first super-wiring layer is provided with a plurality of through holes corresponding one-to-one with the positions of the pads, the pads are electrically connected to the metal portion of the lower surface of the first super-wiring layer through the metal in the through holes, and the metal portion of the lower surface of the first super-wiring layer is also provided with the conductive bumps respectively.

[0008] The second redistribution layer is disposed below the conductive bumps, and the area of ​​the second redistribution layer is larger than the area of ​​the photoelectric sensor chip; the metal portion on the upper surface of the second redistribution layer is electrically contacted with the conductive bumps respectively; the metal portion on the upper surface and the metal portion on the lower surface of the second redistribution layer are electrically connected; the metal portion on the lower surface of the second redistribution layer is also provided with solder balls respectively; the size of the solder balls is larger than the size of the conductive bumps, and the spacing between the solder balls is larger than the spacing between the conductive bumps.

[0009] Optionally, the packaging structure further includes: a dam; the dam is disposed between the glass and the photoelectric sensing chip; the glass, the photoelectric sensing chip, and the dam enclose a sealed cavity; the photosensitive area is located within the sealed cavity.

[0010] Optionally, the height of the dam is equal to the distance between the glass and the photosensitive area; the height of the dam is 20μm-30μm, including the values ​​at both ends.

[0011] Optionally, the packaging structure further includes: a molding layer; the molding layer is disposed on the upper surface of the second redistribution layer, wraps the sides of the glass and the photoelectric sensing chip, and fills the gap between the photoelectric sensing chip and the second redistribution layer.

[0012] Optionally, an insulating layer is provided between the photoelectric sensing chip and the first redistribution layer; the insulating layer does not cover the pads.

[0013] Optionally, the lower surface of the first rewiring is provided with a solder resist layer in addition to the positions of the conductive bumps.

[0014] Optionally, the photosensitive area includes a photosensitive layer and a microlens covering the photosensitive layer.

[0015] Optionally, the through hole is a stepped hole.

[0016] Optionally, the diameter of the conductive bump is less than or equal to 150 μm;

[0017] And / or, the diameter of the solder balls is greater than or equal to 300 μm; the spacing between the solder balls is greater than 150 μm.

[0018] To solve the above-mentioned technical problems, this utility model also provides an electronic device, including the packaging structure described above.

[0019] As can be seen, the packaging structure provided by this utility model has the following advantages compared with the traditional WLCSP packaging structure and iBGA packaging structure:

[0020] 1. Small package size: This packaging structure mainly relies on glass and the wafer itself. Using TSV technology, the first wiring layer is created on the substrate of the optoelectronic sensor chip. The product is then flip-chip bonded to the second wiring layer. The packaging structure eliminates the need for wire bonding (WB), resulting in a smaller outward expansion dimension of the optoelectronic sensor chip. This makes the size advantage of this packaging structure far greater than that of the iBGA packaging structure. The package height is also much smaller than that of the iBGA packaging structure, effectively reducing the package volume. The package volume of the same optoelectronic sensor chip using WLCSP is half the volume of the iBGA package. This effective reduction in package volume better meets customers' high-density requirements for device space.

[0021] 2. Good heat dissipation performance: This packaging structure is small in size and thin, with a packaging thickness of 1 / 2 that of iBGA packages of the same specifications, resulting in good heat dissipation during operation of the optoelectronic sensor chip.

[0022] 3. Excellent electrical performance: This package structure adopts redistribution technology, and the internal wiring length is much shorter than that of the iBGA package structure. The linewidth ratio is also larger. Therefore, the parasitic lead capacitance, resistance and inductance parameters are very small, the signal transmission delay time is short, which is conducive to improving the high-frequency performance of the circuit, effectively increasing the bandwidth of data transmission, reducing current loss, and improving the stability of data transmission.

[0023] 4. High interconnect density: This packaging structure uses TSV (Through Silicon Via) technology to bring more I / Os from the pads to the back of the optoelectronic sensor chip via a redistribution layer. Conductive bumps are formed on the back of the optoelectronic sensor chip and soldered to another larger redistribution layer. This fan-out method allows for the creation of larger solder balls and a wider solder ball pitch, solving the contradiction between a large number of I / Os and a small package size. Compared with various packages of the same size, more I / Os can be placed in a smaller space to meet the needs of subsequent high-density interconnection, while keeping costs extremely low.

[0024] This utility model also provides an electronic device that has the above-mentioned beneficial effects. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of the present utility model;

[0027] Figures 2 to 6 This is a schematic flowchart illustrating a method for preparing a packaging structure according to an embodiment of the present invention.

[0028] The annotations in the attached figures are explained as follows:

[0029] 1-Photoelectric sensor chip; 11-Substrate; 12-Photosensitive area; 13-Pad; 2-Glass; 3-First redistribution layer; 4-Conductive bump; 5-Second redistribution layer; 6-Solder ball; 7-Damage; 8-Encapsulation layer; 91-First insulating layer; 92-Second insulating layer; 93-Solder resist layer; 10-Carrier board. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0031] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of the present invention. The packaging structure may include: a photoelectric sensor chip 1, glass 2, a first rewiring layer 3, a second rewiring layer 5, conductive bumps 4, and solder balls 6;

[0032] Glass 2 is positioned above photoelectric sensor chip 1;

[0033] The upper surface of the photoelectric sensor chip 1 is provided with a photosensitive area 12 and a plurality of pads 13 surrounding the photosensitive area 12; the side surface and the lower surface of the photoelectric sensor chip 1 are also provided with a first super-wiring layer 3, the first super-wiring layer 3 is provided with a plurality of through holes corresponding one-to-one with the positions of the pads 13, the pads 13 are electrically connected to the metal part of the lower surface of the first super-wiring layer 3 through the metal in the through holes, and the metal part of the lower surface of the first super-wiring layer 3 is also provided with conductive bumps 4 respectively.

[0034] The second wiring layer 5 is disposed below the conductive bumps 4, and the area of ​​the second wiring layer 5 is larger than the area of ​​the photoelectric sensor chip 1; the metal portion on the upper surface of the second wiring layer 5 is electrically contacted with the conductive bumps 4 respectively; the metal portion on the upper surface and the metal portion on the lower surface of the second wiring layer 5 are electrically connected; the metal portion on the lower surface of the second wiring layer 5 is also provided with solder balls 6 respectively; the size of the solder balls 6 is larger than the size of the conductive bumps 4, and the spacing between the solder balls 6 is larger than the spacing between the conductive bumps 4.

[0035] It should be noted that this embodiment can be applied to any type of photoelectric sensor chip 1, including but not limited to SPAD (Single-Photon Avalanche Diode) lidar chips. The photoelectric sensor chip 1 in this embodiment includes a substrate 11, a photosensitive area 12 disposed on the upper surface of the substrate 11, and at least two pads 13 surrounding the photosensitive area 12; wherein the substrate 11 can be, but is not limited to, a silicon substrate. Silicon is a common material in the prior art, and this embodiment does not limit the internal composition of the substrate 11, but directly uses a silicon substrate 11 made of existing materials. This embodiment does not limit the specific number of pads 13, which can be determined according to the actual needs of the product. Furthermore, in this embodiment, the photosensitive area 12 may include a photosensitive layer and a microlens covering the photosensitive layer. It should be noted that in this embodiment, the microlens can improve the light collection efficiency of the photosensitive layer by focusing the light.

[0036] It should be noted that, in this embodiment, the first wiring layer 3 refers to the metal lines disposed on the side and bottom surfaces of the photoelectric sensor chip 1.

[0037] Furthermore, in this embodiment, an insulating layer may be provided between the photoelectric sensor chip 1 and the first redistribution layer 3; the insulating layer does not cover the pads 13. It should be noted that in this embodiment, by providing an insulating layer, electrical isolation between the substrate 11 of the photoelectric sensor chip 1 and the first redistribution layer 3 can be achieved.

[0038] This embodiment does not limit the specific type of insulating layer, as long as it can ensure insulation. This embodiment also does not limit the specific number of insulating layers; it may include one insulating layer or at least two insulating layers. Preferably, it may include a first insulating layer 91 and a second insulating layer 92. The first insulating layer 91 is disposed on the side closer to the photoelectric sensor chip 1, and the second insulating layer 92 is disposed on the side closer to the first redistribution layer 3. It should be noted that the first insulating layer 91 can be used to achieve electrical isolation between the substrate 11 of the photoelectric sensor chip 1 and the first redistribution layer 3; the first insulating layer 91 can also be used to prevent metal atoms in the first redistribution layer from diffusing into the substrate 11.

[0039] Furthermore, in this embodiment, the lower surface of the first wiring layer may also be provided with a solder resist layer 93 in addition to the positions of the conductive bumps 4. It should be noted that in this embodiment, the solder resist layer 93 can prevent the first wiring layer 3 from being corroded.

[0040] It should be noted that the vias in this embodiment are formed in the substrate 11 of the photoelectric sensor chip 1 using TSV technology. This embodiment does not limit the specific number of vias; the number of vias is the same as the number of pads 13. This embodiment does not limit the specific shape of the vias; it can be determined according to actual product requirements. For example, the vias can be stepped holes. It should be noted that using stepped holes in this embodiment can improve structural reliability.

[0041] This embodiment does not limit the specific type of conductive bumps 4, as long as they are conductive. This embodiment does not limit the specific number of conductive bumps 4, which can be determined according to actual product requirements. This embodiment does not limit the specific shape of conductive bumps 4, which can be determined according to actual product requirements; for example, conductive bumps 4 can be spherical. It should be noted that in this embodiment, the size of the conductive bumps 4 is smaller than the size of the solder balls 6 to ensure that larger conductive bumps 4 can be provided on the lower surface of the first layer of wiring. This embodiment does not limit the specific size of the conductive bumps 4; for example, the diameter of the conductive bumps 4 can be less than or equal to 150 μm.

[0042] Furthermore, the encapsulation structure in this embodiment may further include: a dam 7; the dam 7 is disposed between the glass 2 and the photoelectric sensor chip 1; the glass 2, the photoelectric sensor chip 1, and the dam 7 enclose a sealed cavity; the photosensitive area 12 is located within the sealed cavity. It should be noted that in this embodiment, the dam 7 can fix the glass 2 and the photoelectric sensor chip 1 together, while the formed sealed cavity can also seal the photosensitive area 12. This embodiment does not limit the specific type of dam 7, as long as it can fix the glass 2 and the photoelectric sensor chip 1 together. For example, the dam 7 can be epoxy resin. It should be noted that epoxy resin is a common material in the prior art. This embodiment does not limit the internal components of the dam 7, but directly uses a dam 7 made of existing materials.

[0043] In this embodiment, the height of the dam 7 can be equal to the distance between the glass 2 and the photosensitive area 12; the height of the dam 7 can be 20μm-30μm, including the values ​​at both ends. It should be noted that in the iBGA package structure, the distance between the inner surface of the glass 2 and the photosensitive area 12 is relatively large, between 80μm and 120μm, resulting in an excessively long light propagation path and a large amount of interfering light entering, thus reducing detection accuracy. However, in this embodiment, the dam 7 can be implemented using a wafer-level cover glass 2 process, thereby maintaining the distance between the inner surface of the glass 2 and the photosensitive area 12 between 20μm and 30μm, thus solving the problem of an excessively long light path. Through an extremely short light path, the amount of light entering is effectively increased, the amount of interfering light entering is reduced, and the detection accuracy of the photoelectric sensor chip 1 is improved. The wafer-level cover glass 2 process involves first coating a damming material (such as epoxy resin) onto the surface of the photoelectric sensor chip 1, then performing patterning processing through exposure and development to retain the damming material around the edges of the photoelectric sensor chip 1, thus forming the damming material 7. Finally, the glass 2 is placed over the damming material 7. The damming material 7 formed by the wafer-level cover glass 2 process has controllable precision and thickness. Moreover, in traditional packaging structures, the cover glass 2 is applied to a single photoelectric sensor chip 1, resulting in poor uniformity. However, the packaging structure in this embodiment uses the wafer-level cover glass 2 process, which can achieve better uniformity and meet automotive-grade consistency requirements.

[0044] It should be noted that the second wiring layer 5 in this embodiment includes metal lines and a solder mask layer filled between the metal lines.

[0045] This embodiment does not limit the specific number of solder balls 6, which can be determined according to the actual needs of the product. This embodiment also does not limit the specific type of solder balls 6, as long as it ensures simultaneous electrical and soldering connections with other external devices. For example, solder balls 6 may include tin balls. It should be noted that tin is a common material in the prior art, and this embodiment does not limit the internal composition of the solder balls 6, but directly uses tin balls made from existing materials.

[0046] It should be noted that the area of ​​the second wiring layer 5 in this embodiment is larger than the area of ​​the photoelectric sensor chip 1. Larger solder balls 6 and wider solder ball spacing can be provided on the lower surface of the second wiring layer 5 to meet the requirements of conventional SMT (Surface Mount Technology). This embodiment does not limit the specific size of the solder balls 6; for example, the diameter of the solder balls 6 can be greater than or equal to 300 μm. This embodiment does not limit the specific spacing of the solder balls 6; for example, the spacing of the solder balls 6 can be greater than 150 μm.

[0047] Furthermore, the packaging structure in this embodiment may also include: a molding compound 8; the molding compound 8 is disposed on the upper surface of the second wiring layer 5, wrapping the sides of the glass 2 and the photoelectric sensor chip 1, and filling the gap between the photoelectric sensor chip 1 and the second wiring layer 5. It should be noted that in this embodiment, the molding compound 8 is used to seal the photoelectric sensor chip 1 and the second wiring layer 5, which can improve the reliability of the packaging structure.

[0048] This embodiment does not limit the specific type of the encapsulation layer 8, as long as it can achieve a seal. For example, the encapsulation layer 8 can be an encapsulating adhesive. It should be noted that encapsulating adhesive is a common material in the prior art. This embodiment does not limit the internal components of the encapsulation layer 8, but directly uses an encapsulation layer 8 made of existing materials.

[0049] It should be noted that in this embodiment, the sides of glass 2 and photoelectric sensor chip 1 can be flush. Furthermore, in this embodiment, the thickness of the molding compound 8 (in this embodiment, the thickness refers to the distance from the side of glass 2 and photoelectric sensor chip 1 to the side of the molding compound 8) can be equal to the distance from the side of glass 2 and photoelectric sensor chip 1 to the edge of the second redistribution layer 5, that is, the molding compound 8 can extend from the side of glass 2 and photoelectric sensor chip 1 to the edge of the second redistribution layer 5; specifically, the thickness of the molding compound 8 can be greater than 500 μm. It should be noted that in this embodiment, the side molding compound 8 extends from the side of glass 2 and photoelectric sensor chip 1 to the edge of the second redistribution layer 5 and fills all gaps, resulting in better sealing and better prevention of the risk of moisture erosion of the solder pads 13; the overall structural enhancement brought by the molding compound makes the package more reliable, allowing it to withstand more stringent reliability conditions and be suitable for high-end applications such as automotive.

[0050] Based on the above embodiments, the present invention has the following advantages over traditional WLCSP and iBGA packaging structures:

[0051] 1. Small package size: This package structure mainly relies on glass 2 and the wafer itself. The first wiring layer 3 is made on the substrate 11 of the optoelectronic sensor chip 1 using TSV technology. The product is soldered onto the second wiring layer 5 by flip-chip bonding. The package structure does not require WB bonding. The outward expansion size of the optoelectronic sensor chip 1 is small, so the size advantage of this package structure is much greater than that of the iBGA package structure. The package height is much smaller than that of the iBGA package structure, which effectively reduces the package volume. The package volume of the same optoelectronic sensor chip 1 using WLCSP package is 1 / 2 of the iBGA package volume. This effectively reduces the package volume, thus better meeting the customer's high-density requirements for body space.

[0052] 2. Good heat dissipation performance: This package structure is small in size and thin in thickness. The package thickness is 1 / 2 of that of the iBGA package of the same specifications, resulting in good heat dissipation when the photoelectric sensor chip 1 is running.

[0053] 3. Excellent electrical performance: This package structure adopts redistribution technology, and the internal wiring length is much shorter than that of the iBGA package structure. The linewidth ratio is also larger. Therefore, the parasitic lead capacitance, resistance and inductance parameters are very small, the signal transmission delay time is short, which is conducive to improving the high-frequency performance of the circuit, effectively increasing the bandwidth of data transmission, reducing current loss, and improving the stability of data transmission.

[0054] 4. High connection density: This package structure uses TSV technology to bring more I / Os out from the pads 13 to the back of the optoelectronic sensor chip 1 in the form of a redistribution layer. Conductive bumps 4 are formed on the back of the optoelectronic sensor chip 1 and soldered to another redistribution layer with a larger size. This fan-out method is used to create larger solder balls 6 and wider solder ball spacing, which solves the contradiction between a large number of I / Os and a small package size. Compared with various packages of the same size, more I / Os can be placed in a smaller space to meet the needs of subsequent high-density interconnection, and the cost can be controlled to be extremely low.

[0055] This application also provides an electronic device including the packaging structure described above.

[0056] Based on the above embodiments, this utility model includes the above-described packaging structure, and therefore also has the above-described beneficial effects.

[0057] To facilitate understanding of this invention, an embodiment of this invention also provides a method for preparing the packaging structure. Please refer to... Figures 2 to 6 , Figures 2 to 6 This is a schematic flowchart illustrating a method for fabricating a packaging structure according to an embodiment of the present invention. The method employs a combination of TSV (Transmission Seed) technology, RDL (Redistribution Layer) technology, and molding technology, and may specifically include:

[0058] Step 1: Package preparation

[0059] like Figure 2 As shown, a dam 7 is formed on the upper surface of the photoelectric sensor chip 1, and glass 2 is added to the photosensitive area 12 as a structural support; more I / O are led out from the pad 13 to the back side of the substrate 11 through the first redistribution layer 3 using TSV technology, and conductive bumps 4 are formed on the back side of the substrate 11 (the diameter of the conductive bumps 4 can be less than or equal to 150μm).

[0060] This step is a wafer-level packaging technology with high packaging precision and excellent consistency in dam height. After the package is completed, the packaged product needs to be divided into individual dies by cutting.

[0061] Step 2, Fabrication of the second rewiring layer 5:

[0062] like Figure 3 As shown, the second super-wiring layer 5 is prepared on the carrier board 10. The main purpose is to solder the conductive bumps 4 to the second super-wiring layer 5. In this step, the second super-wiring layer 5 is made using a wafer-level large-area array process with high precision. Fan-out is made in this way to create larger solder balls 6 and wider solder ball 6 spacing to meet the needs of conventional SMT.

[0063] Step 3: Flip-chip soldering of the package:

[0064] like Figure 4 As shown, the conductive bumps 4 of the package prepared in the first step are soldered onto the prepared second wiring layer 5 in a flip-chip manner for interconnection;

[0065] Step 4, Structure Molding:

[0066] like Figure 5 As shown, the flip-chip structure is molded to form a plastic encapsulation layer 8, thereby enhancing the structural strength and integrating the package with the second rewiring layer 5 into a whole.

[0067] Step 5: Remove carrier plate 10:

[0068] like Figure 6 As shown, the carrier board 10 below the second wiring layer 5 is removed to expose the solder ball pads;

[0069] Step 6: Planting the bulbs:

[0070] Solder balls (optional) are placed on the solder pads of the second redistribution layer 5 to form solder balls 6, ultimately resulting in... Figure 1 The packaging structure shown is such that, since the second wiring layer 5 has been fanned out, the diameter of the solder balls 6 can be greater than or equal to 300μm, and the spacing can be greater than 150μm, which meets the requirements of conventional SMT soldering, can improve the feasibility of SMT mass production, and reduce the frequency of abnormalities.

[0071] The above-mentioned packaging structure can be prepared by applying the preparation method of the packaging structure provided in the embodiments of this utility model.

[0072] The above provides a detailed description of the packaging structure and electronic device provided by this utility model. For those skilled in the art, based on the ideas of the embodiments of this utility model, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A package structure, characterized by, include: Optoelectronic sensor chip, glass, first wiring layer, second wiring layer, conductive bumps and solder balls; The glass is disposed above the photoelectric sensing chip; The upper surface of the photoelectric sensor chip is provided with a photosensitive area and a plurality of pads surrounding the photosensitive area; the side surface and the lower surface of the photoelectric sensor chip are also provided with a first super-wiring layer, the first super-wiring layer is provided with a plurality of through holes corresponding one-to-one with the positions of the pads, the pads are electrically connected to the metal portion of the lower surface of the first super-wiring layer through the metal in the through holes, and the metal portion of the lower surface of the first super-wiring layer is also provided with the conductive bumps respectively. The second redistribution layer is disposed below the conductive bumps, and the area of ​​the second redistribution layer is larger than the area of ​​the photoelectric sensor chip; the metal portion on the upper surface of the second redistribution layer is electrically contacted with the conductive bumps respectively; the metal portion on the upper surface and the metal portion on the lower surface of the second redistribution layer are electrically connected; the metal portion on the lower surface of the second redistribution layer is also provided with solder balls respectively; the size of the solder balls is larger than the size of the conductive bumps, and the spacing between the solder balls is larger than the spacing between the conductive bumps.

2. The package structure of claim 1, wherein, Also includes: Enclosure; The dam is disposed between the glass and the photoelectric sensing chip; the glass, the photoelectric sensing chip, and the dam together form a sealed cavity; The photosensitive area is located within the sealed cavity.

3. The package structure of claim 2, wherein, The height of the dam is equal to the distance between the glass and the photosensitive area; the height of the dam is 20μm-30μm, including the values ​​at both ends.

4. The package structure of claim 1, wherein, Also includes: Molding layer; The molding layer is disposed on the upper surface of the second rewiring layer, wrapping the sides of the glass and the photoelectric sensor chip, and filling the gap between the photoelectric sensor chip and the second rewiring layer.

5. The package structure of claim 1, wherein, An insulating layer is provided between the photoelectric sensing chip and the first redistribution layer; the insulating layer does not cover the pads.

6. The package structure of claim 1, wherein, In addition to the locations of the conductive bumps, the lower surface of the first layer of wiring is also provided with a solder resist layer.

7. The package structure of claim 1, wherein, The photosensitive area includes a photosensitive layer and a microlens covering the photosensitive layer.

8. The package structure of claim 1, wherein, The through hole is a stepped hole.

9. The package structure of claim 1, wherein, The diameter of the conductive bump is less than or equal to 150 μm; And / or, the diameter of the solder balls is greater than or equal to 300 μm; the spacing between the solder balls is greater than 150 μm.

10. An electronic device, comprising: Includes the packaging structure as described in any one of claims 1-9.

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