Connection layer and stacked battery

Abstract

The application relates to the technical field of solar cells, in particular to a connecting layer and a stacked cell. The connecting layer comprises a first transparent conductive oxide layer, a second transparent conductive oxide layer and a third transparent conductive oxide layer which are stacked; wherein the doping type of the second transparent conductive oxide layer is different from that of the first transparent conductive oxide layer, and the doping type of the third transparent conductive oxide layer is the same as that of the first transparent conductive oxide layer; the doping type is n-type doping or p-type doping; and the thickness of the second transparent conductive oxide layer is less than or equal to 10 nm. The connecting layer of the embodiment of the application can provide more recombination sites, has higher recombination efficiency, can reduce the accumulation of charges at the interface of the recombination layer, and thus effectively improves the open-circuit voltage and the fill factor of the stacked cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a connecting layer and a stacked cell. Background Technology

[0002] With the development of photovoltaic technology, the efficiency of single-junction solar cells is gradually approaching its theoretical limit—the Shockley-Quesel efficiency (~33%). To overcome this bottleneck, tandem solar cells based on perovskite and crystalline silicon have become a promising development direction. This technology achieves segmented and more efficient absorption and utilization of the solar spectrum by stacking semiconductor materials with different band gaps (such as wide-bandgap perovskite top cells and narrow-bandgap crystalline silicon bottom cells), thereby significantly improving the overall energy conversion efficiency of the device.

[0003] Currently, tandem solar cell technology is particularly favored in space applications (such as satellites) due to its ability to provide higher power output per unit area. In the future, with continued breakthroughs in material stability and mass production processes, tandem solar cell technology is expected to be widely applied in ground-based photovoltaic power plants, driving solar power generation efficiency to new heights. The connecting layer in a tandem solar cell is used for electrical series connection and carrier recombination between sub-cells, ensuring that the output voltage of the tandem device is the sum of the voltages of the sub-cells. While the connecting layer provides a carrier recombination interface, it suffers from insufficient recombination efficiency, leading to carrier accumulation and voltage loss in the tandem device's output voltage.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Utility Model Content

[0005] This application provides a connecting layer and a stacked battery to solve or alleviate one or more of the technical problems mentioned above.

[0006] The first aspect of this application provides a connection layer, including:

[0007] A first transparent conductive oxide layer, a second transparent conductive oxide layer, and a third transparent conductive oxide layer are stacked together; wherein, the doping type of the second transparent conductive oxide layer is different from that of the first transparent conductive oxide layer, and the doping type of the third transparent conductive oxide layer is the same as that of the first transparent conductive oxide layer; the doping type is n-type doping or p-type doping; the thickness of the second transparent conductive oxide layer is less than 10 nm.

[0008] The connecting layer of the first aspect of the embodiments of this application can provide more recombination sites and has higher recombination efficiency, which can reduce the accumulation of charge at the interface of the recombination layer, thereby effectively improving the open circuit voltage and fill factor of the tandem battery.

[0009] A second aspect of this application provides a stacked battery, including the interconnecting layer described in the first aspect. This improves the open-circuit voltage and fill factor. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0011] Figure 1 This is a schematic diagram of the connection layer provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram of the connection layer provided in another embodiment of this application;

[0013] Figure 3 This is a schematic diagram of the structure of the connection layer provided in another embodiment of this application;

[0014] Figure 4 This is a schematic diagram of the structure of the stacked battery provided in the embodiments of this application.

[0015] Explanation of reference numerals in the attached figures:

[0016] 1-First transparent conductive oxide layer; 2-Second transparent conductive oxide layer; 3-Third transparent conductive oxide layer; 4-Buffer layer; 5-First metal layer; 6-Second metal layer; 010-Second electrode; 020-Third hole transport layer; 030-Light absorption layer; 040-Third electron transport layer; 050-Second connecting layer; 060-Second hole transport layer; 070-Mid-bandgap perovskite layer; 080-Second electron transport layer; 090-First connecting layer; 011-First hole transport layer; 012-Wide-bandgap perovskite layer; 013-First electron transport layer; 014-First electrode. Detailed Implementation

[0017] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0018] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0019] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0022] The fill factor (FF) used in this article refers to the actual maximum available power (P). m or V mp ×J mp The ratio of the theoretical (not practically available) power (Jsc × Voc) to the theoretical (not practically available) power (Jsc × Voc). Therefore, FF can be determined by the following formula: FF = (V mp ×J mp ) / (J sc ×V oc Jmp and Vmp represent the current density and voltage at the maximum power point (Pm), respectively, which is obtained by changing the resistance in the circuit until J×V reaches its maximum value; Jsc and Voc represent the short-circuit current and open-circuit voltage, respectively. The fill factor is a key parameter for evaluating solar cells. Commercial solar cells typically have a fill factor of approximately 60% or higher.

[0023] The open-circuit voltage (Voc) used in this paper is the potential difference between the anode and cathode of the device under conditions of no external load connection.

[0024] The short-circuit current (Isc) used in this article is the maximum current flowing through the output terminal of a photovoltaic cell or module when it is short-circuited (voltage V=0) under STC conditions.

[0025] The power conversion efficiency (PCE) of solar cells used in this article refers to the percentage of power converted from absorbed light into electrical energy. The PCE of a solar cell can be measured under standard test conditions (STC) based on incident light irradiance (E: W / m²). 2 ) and the surface area of ​​solar cells (Ac:m 2 The STC is calculated by dividing by the point of maximum power (Pm). STC typically refers to the value at a temperature of 25°C and an irradiance of 100 W / m². 2The spectrum of air quality 1.5 (AM1.5).

[0026] This application provides a technical solution for a connecting layer and a stacked battery. Based on this, the accumulation of charge carriers on the connecting layer is reduced. See below for details.

[0027] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0028] The first aspect of the embodiments of this application provides a connection layer.

[0029] In optional embodiments, such as Figure 1 As shown, the interconnecting layer includes a first transparent conductive oxide layer 1, a second transparent conductive oxide layer 2, and a third transparent conductive oxide layer 3 stacked together. The doping type of the second transparent conductive oxide layer 2 is different from that of the first transparent conductive oxide layer 1, while the doping type of the third transparent conductive oxide layer 3 is the same as that of the first transparent conductive oxide layer 1. The thickness of the second transparent conductive oxide layer 2 is less than 10 nm. This forms an npn or pnp interconnecting layer. When the interconnecting layer is an npn structure, the ultrathin p-type layer acting as an interlayer has little impact on electron transport. However, holes that fail to recombine at the recombination interface can tunnel into the p-type interlayer within the interconnecting layer. Therefore, electron-hole recombination can also occur at the np interface inside the interconnecting layer, thereby improving the recombination efficiency of the tandem solar cell and effectively reducing the impact of charge accumulation on the device's turn-on voltage and stability. The effect is similar when the interconnecting layer is pnp. Furthermore, the entire interconnecting layer is composed of a transparent conductive oxide layer (TCO), which can reduce light loss.

[0030] Optionally, the thickness of the second transparent conductive oxide layer can be 10 nm, 9 nm, 7 nm, 5 nm, 4 nm, 3 nm, 1 nm, etc.

[0031] It is worth noting that the doping type of the transparent conductive oxide layer refers to the semiconductor doping type, which includes p-type doping (corresponding to p-type transparent conductive oxide) and n-type doping (corresponding to n-type transparent conductive oxide).

[0032] Optionally, the first transparent conductive oxide layer 1, the second transparent conductive oxide layer 2, and the third transparent conductive oxide layer 3 are each independently a p-type transparent conductive oxide or an n-type transparent conductive oxide.

[0033] Furthermore, the p-type transparent conductive oxide can be CuAlO2 or NiO.

[0034] Furthermore, the n-type transparent conductive oxide is tin-doped indium oxide (ITO), aluminum-doped zinc oxide (AZO), zinc-doped indium oxide (IZO), or fluorine-doped tin dioxide (FTO).

[0035] Optionally, the thickness of the first transparent conductive oxide layer 1 and the thickness of the third transparent conductive oxide layer 3 are each independently between 5 nm and 50 nm. This avoids the formation of discontinuous "island structures" due to excessively thin interconnect layers, which could lead to interruptions in carrier transport channels. It also avoids increasing device series resistance and affecting optical performance due to excessive thickness. For example, the thickness of the first transparent conductive oxide layer 1 and the thickness of the third transparent conductive oxide layer 3 can be 5 nm, 15 nm, 25 nm, 35 nm, 55 nm, 50 nm, etc.

[0036] In an optional embodiment, this application embodiment improves the bandgap problem at the perovskite / TCO interface by introducing a buffer layer. Therefore, it can be disposed on the first transparent conductive oxide layer or the third transparent conductive oxide layer, depending on the contact with the perovskite sub-cell.

[0037] In some embodiments, see Figure 2 A buffer layer 4 is provided on the side of the third transparent conductive oxide layer 3 away from the second transparent conductive oxide layer 2; the buffer layer 4 is SnO2 nanoparticles or ZnO nanoparticles. Thus, the buffer layer 4 is introduced to improve the energy level alignment at the perovskite / TCO interface and reduce barrier loss.

[0038] In other embodiments, a buffer layer 4 is provided on the side of the third transparent conductive oxide layer away from the second transparent conductive oxide layer 2; the buffer layer 4 is made of SnO2 nanoparticles or ZnO nanoparticles. Thus, the buffer layer 4 is introduced to improve the energy level alignment at the perovskite / TCO interface and reduce barrier loss.

[0039] Furthermore, the particle size (Dv50) of SnO2 nanoparticles or ZnO nanoparticles can be 5 nm to 50 nm. For example, the particle size (Dv50) of SnO2 nanoparticles or ZnO nanoparticles can be 5 nm, 10 nm, 20 nm, 30 nm, 50 nm, etc.

[0040] Optionally, when the buffer layer 4 is made of SnO2 nanoparticles, its thickness is 5 nm to 30 nm. This ensures high coverage, effectively passivates interface defects, and controls series resistance, thereby increasing the electron tunneling probability. For example, the thickness of the buffer layer 4 can be 5 nm, 10 nm, 15 nm, 25 nm, 30 nm, etc.

[0041] Optionally, when the buffer layer 4 is made of ZnO nanoparticles, its thickness is 10 nm to 40 nm. This results in a relatively low carrier mobility of ZnO (~30 cm² / V·s), and using a thickness within this range can compensate for conductivity loss and avoid interference and reflection losses caused by excessive thickness. For example, the thickness of the buffer layer 4 can be 10 nm, 15 nm, 25 nm, 30 nm, 40 nm, etc.

[0042] In an optional embodiment, see Figure 3 The connecting layer further includes a first metal layer 5 and / or a second metal layer 6; the first metal layer 5 is disposed on the side of the second transparent conductive oxide layer 2 near the first transparent conductive oxide layer 1; the second metal layer 6 is disposed on the side of the second transparent conductive oxide layer 2 near the third transparent conductive oxide layer 3; thus, the first metal layer 5 and / or the second metal layer 6 can serve as a "highway" for electrons / holes, accelerating the transport of charge carriers across the interface.

[0043] Furthermore, the thicknesses of the first metal layer 5 and the second metal layer 6 are independently 3 nm to 15 nm. This ensures the formation of a continuous metal film while reducing light loss. For example, the thicknesses of the first metal layer 5 and the second metal layer 6 are independently 3 nm, 5 nm, 7 nm, 12 nm, 15 nm, etc.

[0044] Optionally, the first metal layer 5 and the second metal layer 6 can be independently Ag layers or Cu layers. This allows for the excitation of localized surface plasmon resonance (LSPR) in the visible light region, enhancing transmittance in a specific wavelength range (500 nm–800 nm).

[0045] In an optional embodiment, the thickness of the connecting layer is 20 nm to 100 nm. This improves the recombination rate while maintaining optical performance. For example, the thickness of the connecting layer can be 20 nm, 30 nm, 60 nm, 80 nm, 100 nm, etc.

[0046] A second aspect of this application provides a stacked battery, including a connecting layer from the first aspect of this application. Therefore, the connecting layer, having high recombination efficiency, ensures that the output voltage loss of the stacked battery remains at a low level.

[0047] Optionally, the stacked solar cell includes a perovskite sub-cell and a crystalline silicon base cell, with the connecting layer located between the perovskite sub-cell and the crystalline silicon base cell.

[0048] Optionally, the stacked battery can be a double-junction battery, a triple-junction battery, etc. See [link to specific implementation] for details. Figure 4The tandem solar cell is a triple-junction cell consisting of a first perovskite sub-cell, a second perovskite sub-cell, and a crystalline silicon base cell. The first perovskite sub-cell is stacked from top to bottom with a first electrode 014, a first electron transport layer 013, a wide bandgap perovskite layer 012, and a first hole transport layer 011. The second perovskite sub-cell is stacked from top to bottom with a second electron transport layer 080, a mid-bandgap perovskite layer 070, and a second hole transport layer 060. The crystalline silicon base cell is stacked from top to bottom with a third electron transport layer 040, a light absorption layer 030, a third hole transport layer 020, and a second electrode 010. A first connecting layer 090 is provided on the first hole transport layer 011 and the second electron transport layer 080, and a second connecting layer 050 is provided between the second hole transport layer 060 and the third electron transport layer 040. At least one of the first connecting layer 090 and the second connecting layer 050 is selected from the connecting layers of the first aspect of the embodiments of this application.

[0049] Optionally, the first electron transport layer 013, the second electron transport layer 080, and the third electron transport layer 040 may be selected from at least one of TiO2, SnO2, and ZnO.

[0050] Optionally, the thicknesses of the first electron transport layer 013, the second electron transport layer 080, and the third electron transport layer 040 can each be independently 5 nm to 50 nm. For example, the thicknesses of the first electron transport layer 013, the second electron transport layer 080, and the third electron transport layer 040 can each be independently 5 nm, 15 nm, 25 nm, 35 nm, 50 nm, etc.

[0051] Optionally, the first hole transport layer 011, the second hole transport layer 060, and the third hole transport layer 020 can be small organic molecule materials such as poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), 2,2',7,7'-tetrakis(N,N-di-p-methoxyphenylamino)-9,9'-spirodifluorene (HTM-1 or Spiro-OMeTAD), and 3,6-bis(4,4'-dimethoxydiphenylamino)-9-phenylcarbazole (HTM-2).

[0052] Optionally, the first hole transport layer 011, the second hole transport layer 060, and the third hole transport layer 020 can be inorganic materials such as NiO and CuO.

[0053] Optionally, the thicknesses of the first hole transport layer 011, the second hole transport layer 060, and the third hole transport layer 020 can be from 1 nm to 50 nm. For example, the thickness of the first hole transport layer 011 can be 1 nm, 10 nm, 12 nm, 18 nm, 28 nm, 37 nm, 50 nm, etc. The thicknesses of the second hole transport layer 060 and the third hole transport layer 020 are also similar.

[0054] Optionally, the light-absorbing layer 030 can be a TOPCon cell, HJT cell, IBC cell, etc.

[0055] Optionally, the thickness of the light absorption layer 030 can be 80 μm to 180 μm. For example, the thickness of the light absorption layer 030 can be 80 μm, 100 μm, 120 μm, 1600 μm, 180 μm, etc.

[0056] Optionally, the first electrode 014 and the second electrode 010 can be transparent conductive oxides such as ITO, FTO, and IZO, respectively.

[0057] Optionally, the first electrode 014 and the second electrode 010 can be conductive polymer and metal electrodes (Ag, Au, etc.), respectively.

[0058] Optionally, the thickness of the first electrode 014 and the second electrode 010 can be 100 nm to 1000 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 600 nm, 780 nm, 1000 nm, etc.

[0059] Optionally, the band gap of the medium band gap perovskite layer 070 can be 1.4–1.6 eV.

[0060] Furthermore, the structural formula of the mid-bandgap perovskite layer 070 is ABX3, where A represents FA. + MA + Cs + 、Rb + One or more of them, where B is Pb 2+ Sn 2+ One or more of them, where X is I - ,Br - Cl - SCN - OCN - One or more of them.

[0061] Furthermore, the thickness of the mid-bandgap perovskite layer 070 can be 60 nm to 1000 nm. For example, the thickness of the mid-bandgap perovskite layer 070 can be 60 nm, 160 nm, 300 nm, 550 nm, 800 nm, 950 nm, 1000 nm, etc.

[0062] Optionally, the band gap of the wide bandgap perovskite layer 012 is 1.7–2.1 eV.

[0063] Furthermore, the structural formula of the wide-bandgap perovskite layer 012 is ABX3, where A represents FA. + MA+ Cs + 、Rb + One or more of them, where B is Pb 2+ Sn 2+ One or more of them, where X is I - ,Br - Cl - SCN - OCN - One or more of them.

[0064] Furthermore, the thickness of the wide-bandgap perovskite layer 012 can be 300 nm to 600 nm. For example, the thickness of the wide-bandgap perovskite layer 012 can be 300 nm, 450 nm, 500 nm, 600 nm, etc.

[0065] The following section will conduct performance tests on the structure or manufacturing method of the stacked battery provided in the embodiments of this application, as well as related comparative examples.

[0066]

Example 1

[0067] The structure of the tandem battery is shown in the figure. Figure 4 The specific preparation process is as follows:

[0068] An n-type c-Si silicon wafer with a bulk resistivity of 1.5 ± 0.5 Ω·cm was used as the substrate. The substrate was textured in an alkaline solution, followed by standard RCA cleaning, and then etched with hydrofluoric acid (HF) solution to remove the surface oxide layer, yielding the light-absorbing layer 030. Next, plasma-enhanced chemical vapor deposition (PECVD) was used to deposit (i)a-Si:H / (n)μc-SiO on the front side of the silicon wafer. x A :H bilayer structure is deposited as the third electron transport layer 040, and an (i)a-Si:H / (p)μc-Si:H bilayer structure is deposited on the back side as the third hole transport layer 020. Then, a 20 nm thick ITO layer (first transparent conductive oxide layer 1) is deposited on the front side using radio frequency magnetron sputtering, followed by a 5 nm thick NiO layer (second transparent conductive oxide layer 2), and finally a 30 nm thick IZO layer (third transparent conductive oxide layer 3), serving as the second interconnect layer 050. A 15 nm thick ITO layer is deposited on the back side, and then silver paste is screen-printed onto the back side and thermally annealed at 180°C to form the second electrode 010.

[0069] 2. On the front side of the crystalline silicon bottom cell, a second hole transport layer 060 is spin-coated: a self-assembled monolayer (SAM) solution prepared by dissolving Meo-2PACz and 2PACz in ethanol (total concentration 0.5 mg / mL) at a ratio of 3:1 is spin-coated at 4000 rpm for 30 seconds, followed by thermal annealing at 100°C for 10 min to form a 3 nm thick hole transport layer (HTL).

[0070] 3. Preparation of a mid-bandgap perovskite layer 070 on the second hole transport layer 060: A mid-bandgap perovskite precursor solution (FA...) 0.98 MA 0.02 ) 0.95 Cs 0.05 Pb(I 0.98 Br 0.02 )3 was dissolved in a DMF:DMSO=4:1 (v:v) mixed solvent to prepare a precursor with a concentration of 1.7 mol / L. Then, it was spin-coated at 2000 rpm for 25 seconds, then accelerated to 5000 rpm for 30 seconds. 200 μL of chlorobenzene was added dropwise 10 seconds before the end of the spin-coating process for anti-solvent treatment. Finally, it was heat-annealed at 100°C for 20 minutes to form a perovskite layer 070 with a thickness of about 1 μm with a medium band gap.

[0071] 4. Fabrication of a second electron transport layer 080 (ETL) on a mid-bandgap perovskite layer 070: First, a 10 nm thick C layer was deposited using vacuum thermal evaporation. 60 A layer was formed, and then a 30 nm thick SnO2 layer was prepared by atomic layer deposition (ALD). 60 / SnO2 together form the second electron transport layer 080.

[0072] 5. Fabrication of a first interconnect layer 090 on the second electron transport layer 080: First, a 15 nm thick IZO layer (first transparent conductive oxide layer 1) is deposited by magnetron sputtering, then a 1 nm thick NiO layer (second transparent conductive oxide layer 2) is sputtered, and finally a 25 nm thick IZO layer (third transparent conductive oxide layer 3) is sputtered to form the IZO / NiO / IZO composite first interconnect layer 090.

[0073] 6. Fabrication of the first hole transport layer 011 on the first interconnect layer 090: First, a 15 nm thick NiO layer is deposited using magnetron sputtering. X A layer was then spin-coated with a SAM solution (Meo-2PACz:2PACz=3:1, 0.5 mg / mL ethanol solution, 4000 rpm / 30s, annealed at 100°C for 10min) with the same formulation and process as in step 2. NiO X Together with SAM, it forms the first hole transport layer 011.

[0074] 7. Fabrication of a wide-bandgap perovskite layer 012 on the first hole transport layer 011: A wide-bandgap perovskite precursor solution (FA) is prepared... 0.7 Cs 0.3 Pb(I 0.333 Br 0.667 )3 Dissolved in a DMF:DMSO=4:1 (v:v) mixed solvent, concentration 1.0 mol / L) Spin-coated at 1000 rpm for 10 seconds, then accelerated to 4000 rpm for 40 seconds, and 160 μL of anisole was added dropwise 10 seconds before the end for anti-solvent treatment. Finally, it was heat-annealed at 100°C for 20 minutes to form a wide-bandgap perovskite layer 012 with a thickness of about 400 nm.

[0075] 8. Fabrication of the first electron transport layer 013 and the first electrode 014 on the wide-bandgap perovskite layer 012: First, a 10 nm thick C layer was deposited using vacuum thermal evaporation. 60 A layer was formed, and then a 30 nm thick SnO2 layer (C) was prepared by ALD. 60 Together with SnO2, it forms the first electron transport layer 013. Next, a 20 nm thick IZO layer is deposited by magnetron sputtering, and then a 400 nm thick Ag layer is deposited on the IZO by vacuum thermal evaporation. The IZO and Ag together form the first electrode 014.

[0076]

Example 2

[0077] Everything else is the same as in Example 1, except that:

[0078] In step 1, a 20 nm thick ITO layer is deposited on the front side using radio frequency magnetron sputtering as the second interconnect layer 050.

[0079]

Example 3

[0080] Everything else is the same as in Example 1, except that:

[0081] In step 5, a 15 nm thick IZO layer (first transparent conductive oxide layer 1) is first deposited by magnetron sputtering, followed by an 8 nm thick NiO layer (second transparent conductive oxide layer 2), a 25 nm thick IZO layer (third transparent conductive oxide layer 3), and a 10 nm thick ZnO nanolayer (buffer layer 4), which serve as the first connecting layer 090.

[0082] Comparative Example 1

[0083] The other steps are the same as in Example 1, except that:

[0084] In step 1, a 20 nm thick ITO layer is deposited on the front side using radio frequency magnetron sputtering as the second interconnect layer 050;

[0085] In step 5, a 30 nm thick IZO layer is deposited using magnetron sputtering as the first interconnect layer 090.

[0086] Comparative Example 2

[0087] The other steps are the same as in Example 1, except that:

[0088] In step 1, a 20 nm thick ITO layer (first transparent conductive oxide layer 1) is deposited on the front side by radio frequency magnetron sputtering, followed by a 15 nm thick NiO layer (second transparent conductive oxide layer 2), and finally a 30 nm thick IZO layer (third transparent conductive oxide layer 3) is sputtered as the second interconnect layer 050.

[0089] In step 5, a first interconnect layer 090 is prepared on the second electron transport layer 080: First, a 15 nm thick IZO layer (first transparent conductive oxide layer 1) is deposited by magnetron sputtering, then a 30 nm thick NiO layer (second transparent conductive oxide layer 2) is sputtered, and finally a 25 nm thick IZO layer (third transparent conductive oxide layer 3) is sputtered to form the IZO / NiO / IZO composite first interconnect layer 090.

[0090] [Test Example]

[0091] IV tests were performed on the stacked cells of Examples 1 to 3 and Comparative Examples 1 to 2. The specific test data are shown in Table 1.

[0092] Test data are shown in Table 1:

[0093]

[0094] As shown in Table 1, compared with Comparative Example 1, Examples 1-3 demonstrate that the interconnect layer structure of this application can effectively improve the open-circuit voltage and fill factor of the triple-junction device. This is mainly due to the higher recombination efficiency, which reduces charge accumulation at the recombination interface. Compared with Comparative Example 2, Examples 1-3 demonstrate that when the thickness of the interlayer in the interconnect layer is too large, the device performance is severely affected. This is because an excessively thick interlayer will form a large potential barrier inside the interconnect layer, which will seriously hinder charge transport within the interconnect layer.

[0095] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0096] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A tie layer characterized in that, It includes a first transparent conductive oxide layer, a second transparent conductive oxide layer and a third transparent conductive oxide layer stacked together; Wherein, the doping type of the second transparent conductive oxide layer is different from that of the first transparent conductive oxide layer, and the doping type of the third transparent conductive oxide layer is the same as that of the first transparent conductive oxide layer; The doping type is either n-type doping or p-type doping; The thickness of the second transparent conductive oxide layer is less than 10 nm.

2. The connecting layer according to claim 1, characterized in that, A buffer layer is provided on the side of the first transparent conductive oxide layer away from the second transparent conductive oxide layer; or A buffer layer is provided on the side of the third transparent conductive oxide layer away from the second transparent conductive oxide layer; The buffer layer is made of SnO2 nanoparticles or ZnO nanoparticles.

3. The tie layer of claim 2, wherein, When the material of the buffer layer is SnO2 nanoparticles, the thickness of the buffer layer is 5 nm to 30 nm.

4. The tie layer of claim 2, wherein, When the material of the buffer layer is ZnO nanoparticles, the thickness of the buffer layer is 10 nm to 40 nm.

5. The tie layer of claim 2, wherein, The second transparent conductive oxide layer has a first metal layer on the side closest to the first transparent conductive oxide layer; A second metal layer is provided on the side of the second transparent conductive oxide layer near the third transparent conductive oxide layer; The thicknesses of the first metal layer and the second metal layer are independently 3nm to 15nm.

6. The tie layer of claim 5, wherein, The first metal layer and the second metal layer are respectively independently Ag layer or Cu layer.

7. The tie layer of claim 1, wherein The first transparent conductive oxide layer, the second transparent conductive oxide layer, and the third transparent conductive oxide layer satisfy at least one of the following characteristics: (a) The first transparent conductive oxide layer, the second transparent conductive oxide layer and the third transparent conductive oxide layer are each independently a p-type transparent conductive oxide or an n-type transparent conductive oxide; The p-type transparent conductive oxide is CuAlO2 or NiO; The n-type transparent conductive oxide is tin-doped indium oxide, aluminum-doped zinc oxide, zinc-doped indium oxide, or fluorine-doped tin dioxide. (b) The thickness of the first transparent conductive oxide layer and the thickness of the third transparent conductive oxide layer are each 5 nm to 50 nm independently.

8. The tie layer according to any one of claims 1 to 7, wherein The thickness of the connecting layer is 20nm to 100nm.

9. A stacked battery characterized by comprising: Includes the connecting layer as described in any one of claims 1 to 8.

10. The stacked battery of claim 9, wherein, It includes a perovskite sub-cell and a crystalline silicon base cell, with the connecting layer located between the perovskite sub-cell and the crystalline silicon base cell.

Images