Display device

Abstract

A display device is provided. The display device can include a substrate, a light emitting element on the substrate and at a display area, an alignment key on the substrate and at a portion of an alignment area surrounding a non-display area of the display area, and a cover layer covering an entire alignment area and including an inorganic material. The display device can have improved reliability.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0135033, filed on October 4, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more suitable embodiments of this disclosure relate to a display device. For example, one or more suitable embodiments of this disclosure relate to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0003] With the growing interest in information display, research and development have been ongoing on alignment keys used to align components during the manufacturing process of display devices.

[0004] The information disclosed in this Background section is provided to enhance understanding of the background of the described techniques. It may include information that does not constitute part of the prior art suitable for those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a display device with improved or enhanced reliability.

[0006] One or more suitable embodiments of this disclosure relate to a method of manufacturing a display device.

[0007] The aspects of this disclosure are not limited to those described above, and those skilled in the art will understand other aspects not mentioned through the appended claims.

[0008] One or more embodiments of this disclosure may provide a display device comprising: a substrate; a light-emitting element disposed on the substrate and positioned at a display area; an alignment key disposed on the substrate and positioned at a portion of an alignment area surrounding a non-display area of ​​the display area; and a capping layer covering the entire alignment area and comprising an inorganic material.

[0009] In one or more embodiments, the display device may further include a substrate layer disposed between the substrate and the capping layer and covering the entire alignment area except for the alignment keys.

[0010] In one or more embodiments, the substrate layer may include: a first substrate layer disposed on a substrate; and a second substrate layer disposed between the first substrate layer and the capping layer. The reflectivity of the first substrate layer may be higher than that of the second substrate layer.

[0011] In one or more embodiments, the first substrate layer may include aluminum. The second substrate layer may include titanium nitride.

[0012] In one or more embodiments, the capping layer may include aluminum oxide.

[0013] In one or more embodiments, the capping layer may include: a first capping layer disposed on the substrate layer; a second capping layer disposed on the first capping layer; and a third capping layer disposed on the second capping layer.

[0014] In one or more embodiments, the first capping layer may include aluminum oxide. The second capping layer may include acrylic resin. The third capping layer may include acrylic resin.

[0015] In one or more embodiments, the display device may further include: an encapsulation film disposed on a light-emitting element in the display area; an adhesive layer disposed on the encapsulation film in the display area; a color filter layer disposed on the adhesive layer in the display area; and a lens layer disposed on the color filter layer in the display area.

[0016] In one or more embodiments, the first cover layer may comprise substantially the same material as the encapsulating film. The second cover layer may comprise substantially the same material as the adhesive layer. The third cover layer may comprise substantially the same material as the lens layer.

[0017] In one or more embodiments, the alignment key may protrude from the upper surface of the substrate layer.

[0018] In one or more embodiments, the alignment key may include an inorganic material.

[0019] One or more embodiments of this disclosure may provide a method of manufacturing a display device, the method comprising the steps of: forming (e.g., applying) a light-emitting element on a substrate at a display area; forming (e.g., applying) an alignment key on the substrate at a portion of an alignment area of ​​a non-display area surrounding the display area; and forming (e.g., applying) a capping layer covering the entire alignment area and comprising an inorganic material.

[0020] In one or more embodiments, the method may further include: forming (e.g., applying) a substrate layer prior to the step of forming alignment keys, the substrate layer being on a substrate and including an opening defined in a portion of the alignment region.

[0021] In one or more embodiments, alignment keys may be formed at the opening and protrude from the upper surface of the substrate layer.

[0022] In one or more embodiments, the substrate layer may include a first substrate layer and a second substrate layer. The step of forming the substrate layer may include: forming (e.g., applying) a first substrate layer on a substrate; forming (e.g., applying) a second substrate layer on the first substrate layer; and forming openings by patterning a portion of the first substrate layer and a portion of the second substrate layer. The reflectivity of the material forming the first substrate layer may be higher than that of the material forming the second substrate layer.

[0023] In one or more embodiments, the first substrate layer may include aluminum (e.g., formed of aluminum). The second substrate layer may include titanium nitride (e.g., formed of titanium nitride).

[0024] In one or more embodiments, the capping layer may include aluminum oxide.

[0025] In one or more embodiments, the capping layer may include a first capping layer to a third capping layer. The step of forming the capping layer may include: forming a first capping layer, the first capping layer being on a substrate layer and including alumina; forming a second capping layer, the second capping layer being on the first capping layer and including acrylic resin; and forming a third capping layer, the third capping layer being on the second capping layer and including acrylic resin.

[0026] In one or more embodiments, the method may further include: after the step of forming the light-emitting element, forming (e.g., applying) an encapsulation film on the light-emitting element at the display area; forming (e.g., applying) an adhesive layer on the encapsulation film at the display area; forming (e.g., applying) a color filter layer on the adhesive layer at the display area; and forming (e.g., applying) a lens layer on the color filter layer at the display area.

[0027] In one or more embodiments, the first capping layer may be formed concurrently (e.g., simultaneously) with the encapsulation film. The second capping layer may be formed concurrently (e.g., simultaneously) with the adhesive layer. The third capping layer may be formed concurrently (e.g., simultaneously) with the lens layer.

[0028] One or more embodiments of this disclosure may provide an electronic device comprising: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device may include: a substrate; a light-emitting element disposed on the substrate and positioned at a display area; an alignment key disposed on the substrate and positioned at a portion of an alignment area surrounding a non-display area of ​​the display area; and a capping layer covering the entire alignment area and comprising an inorganic material.

[0029] In one or more embodiments, the electronic device may include a mobile phone, smartphone, tablet PC, mobile communication terminal, electronic notebook, e-book, portable multimedia player (PMP), navigation system, navigation device, ultra-mobile PC (UMPC), television, laptop computer, monitor, electric vehicle, billboard, Internet of Things (IoT) device, smartwatch, watch phone, or head-mounted display (HMD).

[0030] This disclosure provides a display device with enhanced reliability and a method for manufacturing the same. The display device may include a substrate, light-emitting elements positioned in a display area, and alignment keys located in a non-display area surrounding the display area. The alignment keys may be covered by a capping layer made of an inorganic material, which enhances the durability of the display device. Furthermore, the display device may primarily consist of a substrate layer between the substrate and the capping layer, the substrate layer comprising a first substrate layer with higher reflectivity and a second substrate layer with lower reflectivity. The method of manufacturing the display device may involve the steps of: forming light-emitting elements on the substrate; creating alignment keys in the non-display area; and applying a capping layer throughout the alignment area. The process may also include forming a substrate layer consisting of two sublayers prior to forming the alignment keys. The display device can be integrated into various electronic devices, such as smartphones, tablets, and televisions, thereby providing improved performance and reliability.

[0031] Details of one or more suitable embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0032] Figure 1 This is a block diagram illustrating one or more embodiments of a display device.

[0033] Figure 2 It is shown Figure 1 A block diagram of one or more embodiments of the sub-pixels.

[0034] Figure 3 It is shown Figure 2 Circuit diagrams of one or more embodiments of the sub-pixels.

[0035] Figure 4 It is shown Figure 1 A plan view of one or more embodiments of the display panel.

[0036] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of the display area of ​​the display panel.

[0037] Figure 6 It is shown Figure 5 A plan view of one or more embodiments of the first pixel.

[0038] Figure 7 It is according to one or more embodiments of this disclosure along Figure 6 A sectional view taken from line I-I'.

[0039] Figure 8 It is shown Figure 4 A magnified plan view of the alignment area.

[0040] Figure 9 It is along Figure 8 The sectional view taken from line II-II'.

[0041] Figure 10 It is shown Figure 9 An enlarged cross-sectional view of the cover layer.

[0042] Figures 11 to 16 This is a diagram illustrating the operation (e.g., steps, tasks, or actions) of a method for manufacturing a display device according to one or more embodiments of the present disclosure.

[0043] Figure 17 It is a block diagram of an electronic device according to one or more embodiments.

[0044] Figure 18 A schematic diagram of one or more suitable embodiments of an electronic device is shown. Detailed Implementation

[0045] Because this disclosure allows for one or more suitable modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in more detail in the written description. However, this is not intended to limit this disclosure to a particular mode of practice, and it will be understood that all modifications, equivalents, and alternatives are included in this disclosure without departing from the spirit and technical scope thereof.

[0046] Throughout this disclosure, and throughout one or more suitable drawings and embodiments, the same reference numerals refer to the same parts. For clarity, the dimensions of elements in the drawings may be exaggerated. It will be understood that although terms such as "first" and / or "second," etc., may be used herein to describe one or more suitable embodiments, these embodiments should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed may be referred to as a second element without departing from the teachings of this disclosure. Similarly, a second element may also be referred to as a first element.

[0047] It will also be understood that if the terms "comprising, including, and having" or "having" are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or one or more (e.g., any suitable) combinations thereof (e.g., when the terms "comprising, including, and having" or "having" are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or one or more (e.g., any suitable) combinations thereof), but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or one or more (e.g., any suitable) combinations thereof. Furthermore, the terms "comprising, including, and having" or similar terms include or support the terms "consisting of" and "substantially consisting of," indicating the presence of the stated features, integrals, steps, operations, elements, and / or components, while other features, integrals, steps, operations, elements, components, and / or groups thereof are absent or substantially absent. When a first portion, such as a layer, film, region, or plate, is disposed on a second portion, the first portion may not only be directly on the second portion, but a third portion may also be disposed between them. In this specification, when it is expressed that a first portion, such as a layer, film, region, or plate, is formed on a second portion, the surface on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces (such as the side or lower surface of the second portion). Conversely, when a first portion, such as a layer, film, region, or plate, is below a second portion, the first portion may not only be directly below the second portion, but a third portion may also be disposed between them.

[0048] While terms such as "first" and "second" can be used to describe one or more suitable components, these components are not necessarily limited to the terms mentioned above. The terms are used to distinguish one component from another.

[0049] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0050] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b and c” indicates only a, only b, only c, (e.g., simultaneously) both a and b, (e.g., simultaneously) both a and c, (e.g., simultaneously) both b and c, all of a, b and c, or variations thereof.

[0051] It will also be understood that if an element or layer is referred to as being "on," "connected to," "bonded to," or "adjacent to" another element, layer, or substrate, then the element or layer may be directly on, directly connected to, directly bonded to, or directly adjacent to the other element, layer, or substrate, or one or more intermediary elements, layers, or substrates may be present (e.g., when an element or layer is referred to as being "on," "connected to," "bonded to," or "adjacent to" another element, layer, or substrate, the element or layer may be directly on, directly connected to, directly bonded to, or directly adjacent to the other element, layer, or substrate, or one or more intermediary elements, layers, or substrates may be present). Conversely, when an element or layer is referred to as being "directly on," "directly connected to," "directly bonded to," or "immediately adjacent to" another element or layer, no intermediary element or layer is present.

[0052] The first direction DR1, the second direction DR2, and the third direction DR3 are not limited to directions corresponding to the three axes of the Cartesian coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be orthogonal to each other (e.g., perpendicular), or they can represent different directions that are not orthogonal to each other (e.g., not perpendicular).

[0053] The embodiments and desired or required details of this disclosure are described with reference to the accompanying drawings in order to describe the disclosure in more detail so that those skilled in the art to which this disclosure pertains can suitably practice it. The same reference numerals always denote the same elements, and their repeated descriptions may be omitted or omitted for ease of interpretation. The dimensions of elements in the drawings may be enlarged or reduced for ease of description. In some embodiments, the dimensions and thickness of each element shown in the drawings are arbitrarily indicated for ease of description; therefore, the disclosure is not necessarily limited thereto. Throughout the specification, the same reference numerals denote the same components. Furthermore, the singular form may include the plural form unless it is specifically mentioned in the sentence.

[0054] Figure 1 This is a block diagram illustrating one or more embodiments of the display device 100.

[0055] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0056] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn, where m and n are positive integers greater than 1.

[0057] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can generate light of a specific color (such as red, green, blue, cyan, magenta, and / or yellow). Two or more subpixels SP can form a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0058] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In one or more embodiments, gate control signal GCS may include a start signal indicating the start of each frame and / or a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0059] In one or more embodiments, first emission control lines EL1 to m-th emission control lines ELm can be provided connected to sub-pixels SP arranged in the row direction. In this case, gate driver 120 may include emission control drivers configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control drivers can operate under the control of controller 150.

[0060] Gate driver 120 may be arranged on one side of display panel 110. However, one or more embodiments are not limited to the foregoing examples. For example, gate driver 120 may be divided into two or more drivers that are physically and / or logically separated from each other. Drivers may be arranged on a first side of display panel 110 and a second side of display panel 110 opposite to the first side. Thus, according to one or more embodiments, gate driver 120 may be arranged around display panel 110 in one or more suitable configurations.

[0061] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In one or more embodiments, data control signal DCS may include source start pulse, source shift clock, and / or source output enable signal, etc.

[0062] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using the voltage from the voltage generator 140. If a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, then the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn (for example, when the gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn). Therefore, the associated sub-pixel SP can generate light corresponding to the data signal. As a result, an image can be displayed on the display panel 110.

[0063] In one or more embodiments, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0064] Voltage generator 140 can operate in response to a voltage control signal VCS provided from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 can be configured to receive an input voltage from an external device located outside display device 100, regulate the received voltage, and adjust the regulated voltage to generate multiple voltages.

[0065] Voltage generator 140 can generate a first electrical voltage VDD and a second electrical voltage VSS. The generated first electrical voltage VDD and second electrical voltage VSS can be supplied to the sub-pixel SP. The first electrical voltage VDD can have a relatively high voltage level. The second electrical voltage VSS can have a lower voltage level than the first electrical voltage VDD. In one or more embodiments, the first electrical voltage VDD and / or the second electrical voltage VSS can be provided by an external device of the display device 100.

[0066] Additionally, voltage generator 140 can generate one or more suitable voltages. For example, voltage generator 140 can generate an initialization voltage to be applied to the sub-pixel SP. For example, during sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a reference voltage can be applied to each of the first data lines DL1 to the nth data line DLn. Voltage generator 140 can generate a reference voltage.

[0067] The controller 150 can control the overall operation of the display device 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the operation of displaying the input image data IMG from an external device. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and / or a voltage control signal VCS in response to the control signal CTRL.

[0068] The controller 150 can convert the input image data IMG into a format suitable for the display device 100 and / or display panel 110, and then output image data DATA. In one or more embodiments, the controller 150 can align the input image data IMG to a row-based subpixel SP format, and then output image data DATA.

[0069] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 can be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 can be functionally separate components within a single driver integrated circuit (DIC). In one or more embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 can be configured as a component separate from the driver integrated circuit (DIC).

[0070] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense ambient temperature and generate temperature data TEP indicating the sensed temperature (e.g., ambient temperature). In one or more embodiments, the temperature sensor 160 may be arranged adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0071] The controller 150 may control one or more suitable operations of the display device 100 in response to temperature data TEP. In one or more embodiments, the controller 150 may adjust the brightness of the image output from the display panel 110 in response to temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first power voltage VDD and the second power voltage VSS.

[0072] Figure 2 It is shown Figure 1 A block diagram of one or more embodiments of subpixels SP (e.g., any subpixel SP in the subpixel SP). Figure 2 In, it is shown Figure 1 The sub-pixel SPij arranged in the i-th row (where i is an integer equal to or greater than 1 and less than or equal to m) and j-th column (where j is an integer equal to or greater than 1 and less than or equal to n) of the sub-pixel SP.

[0073] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0074] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. Here, the first power voltage node VDDN can be configured for transmission. Figure 1 The first power voltage node VDD. The second power voltage node VSSN can be configured for transmission. Figure 1 The node of the second power voltage VSS.

[0075] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC. The cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0076] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm, and the i-th transmit control line ELi, and Figure 1 The j-th data line DLj is one of the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC is configured to control the light-emitting element LD in response to a signal received through the aforementioned signal lines.

[0077] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In one or more embodiments, as... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0078] The sub-pixel circuit SPC can operate in response to a transmission control signal received via the i-th transmission control line ELi. In one or more embodiments, the i-th transmission control line ELi may include one or more sub-transmission control lines. When the i-th transmission control line ELi includes two or more sub-transmission control lines, the sub-pixel circuit SPC can operate in response to a transmission control signal received via the corresponding sub-transmission control line.

[0079] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage, in response to the emission control signal received via the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0080] Figure 3 It is shown Figure 2 Circuit diagrams of one or more embodiments of the sub-pixel SPij.

[0081] Reference Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0082] The sub-pixel circuit (SPC) can be connected to the i-th gate line GLi', the i-th emitter control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3. Compared to... Figure 2 Compared to the i-th transmit control line ELi, the i-th transmit control line ELi' may include a first sub-transmit control line SEL1 and a second sub-transmit control line SEL2.

[0083] The sub-pixel circuit SPC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0084] The first transistor T1 is connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 can be connected to the second node N2. Therefore, the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0085] The second transistor T2 can be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 can be connected to the first sub-gate line SGL1. Therefore, the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0086] The third transistor T3 can be connected between the first node N1 and the second node N2. The gate of the third transistor T3 can be connected to the second sub-gate line SGL2. Therefore, the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 can be connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 can be connected to the second sub-emission control line SEL2. Therefore, the fourth transistor T4 can be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0088] The fifth transistor T5 can be connected between the anode electrode AE ​​of the light-emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. In one or more embodiments, the initialization voltage can be supplied by… Figure 1 The voltage is provided by a voltage generator 140. In one or more embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. Therefore, the fifth transistor T5 may be turned on in response to a gate signal on the third sub-gate line SGL3.

[0089] The sixth transistor T6 is connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 can be connected to the first sub-emitter control line SEL1. Therefore, the sixth transistor T6 can be turned on in response to the emitter control signal of the first sub-emitter control line SEL1.

[0090] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power voltage node VDDN and the second node N2.

[0091] Thus, the sub-pixel circuit SPC may include first transistors T1 to sixth transistors T6, and first capacitor C1 and second capacitor C2. However, one or more embodiments are not limited to the foregoing examples. The sub-pixel circuit SPC can be implemented as any of one or more suitable forms of circuits, each including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may vary.

[0092] The first transistors T1 through T6 may include P-type (P-class) transistors (e.g., formed of P-type (P-class) transistors). Each of the first transistors T1 through T6 may include a metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., formed of a metal-oxide-semiconductor field-effect transistor (MOSFET)). However, one or more embodiments are not limited to the foregoing examples. For example, at least one of the first transistors T1 through T6 may be replaced with an N-type (N-class) transistor.

[0093] In one or more embodiments, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor and / or oxide semiconductor, etc.

[0094] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and an emitting layer. The emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. If, after the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to a low level, then the fourth transistor T4 and the sixth transistor T6 may be turned on (e.g., when the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, and the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to a low level, the fourth transistor T4 and the sixth transistor T6 may be turned on). Furthermore, the first transistor T1 may be turned on in response to the voltage of the second node N2, allowing current to flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element (LD) may be configured to emit light corresponding to the amount of current.

[0095] Figure 4 It is shown Figure 1 A plan view of one or more embodiments of the display panel 110.

[0096] Reference Figure 4,and Figure 1 The display panel DP corresponding to one or more embodiments of the display panel 110 depicted may include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA may surround the display area DA. For example, the display area DA is within the non-display area NDA.

[0097] Display panel DP can include substrate SUB, subpixels SP, and pads (also known as solder pads or solder pads) PD.

[0098] The display panel DP serves as a display screen for head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and / or augmented reality (AR) devices. In some embodiments, the display panel DP can be positioned very close to the user's eyes. In this case, a relatively high density of subpixels SP may be desired or required. To increase the pixel density of the subpixels SP, the substrate SUB can be provided using a silicon substrate. The subpixels SP and / or the display panel DP can be formed on the substrate SUB, which is a silicon substrate. A display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see reference 100). Figure 1 This can be referred to as an OLED on silicon (OLEDoS) display device.

[0099] Subpixels SP can be arranged on the substrate SUB at the display area DA (e.g., within the display area DA). Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 that intersects (e.g., crosses) the first direction DR1. However, one or more embodiments are not limited to the foregoing examples. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP can be in a Pentile form (e.g., Pentile). ® Arrangement of structures (e.g., RGBG matrix, RGBG structure, or RGBG matrix structure), but this disclosure is not limited thereto. ® It is an officially registered trademark of Samsung Display Co., Ltd. The first direction DR1 can refer to the row direction, and the second direction DR2 can refer to the column direction.

[0100] Two or more subpixels SP (e.g., selected from subpixels SP) can form a pixel PXL. For example, three subpixels SP can form a pixel PXL.

[0101] Components for controlling subpixels SP can be arranged on the substrate SUB at the non-display area NDA (e.g., within the non-display area NDA). For example, lines connected to the subpixels SP (such as...) Figure 1The first gate line GL1 to the m gate line GLm and the first data line DL1 to the n data line DLn can be arranged in the non-display area NDA.

[0102] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated into the non-display area NDA of the display panel DP. In one or more embodiments, Figure 1 The gate driver 120 may be on the display panel DP (e.g., mounted on the display panel DP) and positioned in the non-display area NDA. In one or more embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In one or more embodiments, the temperature sensor 160 may be positioned in the non-display area NDA to sense the temperature of the display panel DP.

[0103] The pad PD can be located on the substrate SUB at the non-display area NDA (e.g., disposed within the non-display area NDA). The pad PD can be electrically connected to the sub-pixel SP via line connections. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0104] The pad PD can connect the display panel DP to the display device 100 (see reference). Figure 1 Other component connections. In one or more embodiments, the voltages and signals desired or required for the operation of components included in the display panel DP can be transmitted from the pad PD via... Figure 1 The driver integrated circuit (DIC) is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0105] In one or more embodiments, the circuit board can be electrically connected to the pad PD via a conductive adhesive assembly such as an anisotropic conductive film. Here, the circuit board can be a flexible circuit board (FPCB) comprising a flexible material (e.g., made of a flexible material) and / or a flexible film. The driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pad PD.

[0106] The non-display area NDA may include alignment areas AA. Each of the alignment areas AA may be adjacent to the display area DA and the pad PD. Alignment keys AK may be arranged on the substrate SUB in the alignment areas AA respectively. Each of the alignment keys AK may be located at a portion of the corresponding alignment area AA (e.g., arranged in a portion of the corresponding alignment area AA). The alignment keys AK may be arranged symmetrically with respect to the centerline extending in the second direction DR2 of the display panel DP. The alignment keys AK are used during the manufacturing process of the assembly to enable the equipment or components of the display panel DP to align. For example, because the equipment recognizes the alignment keys AK and sets the position based on the alignment keys AK, the reliability of the manufacturing process of the display panel DP can be improved due to the alignment keys AK.

[0107] In one or more embodiments, the display area DA may have one or more suitable shapes. The display area DA may have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA may have shapes such as polygons, circles, semicircles, and / or ellipses.

[0108] In one or more embodiments, the display panel DP may have a planar display surface. In one or more embodiments, the display panel DP may have a display surface that is at least partially circular (rounded). In one or more embodiments, the display panel DP may be flexible, foldable, and / or rollable. In the foregoing embodiments, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0109] Figure 5 It is shown Figure 4 An exploded perspective view of a portion of the display area DA of the display panel DP. Figure 5 For clarity and simplicity, the display panel DP is schematically shown in the diagram. Figure 4 The portion corresponding to two pixels PXL1 and PXL2 within the pixel PXL. The remaining portions of the display panel DP corresponding to other pixels PXL can also be constructed in essentially the same way.

[0110] Reference Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, one or more embodiments are not limited to the foregoing examples. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels SP, or may include two sub-pixels SP.

[0111] exist Figure 5In this embodiment, when viewed on a third direction DR3 that intersects (e.g., intersects) the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have rectangular shapes and substantially the same dimensions (e.g., when viewed on a third direction DR3 that intersects (e.g., intersects) the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have rectangular shapes and substantially the same dimensions). However, one or more embodiments are not limited to the foregoing examples. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have one or more suitable shapes.

[0112] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0113] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed by semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be disposed of as a body wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, and / or a semiconductor-on-insulator (SeOI) layer, etc. In one or more embodiments, the substrate SUB may include a glass substrate. In one or more embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0114] The pixel circuit layer (PCL) may be on a substrate SUB (e.g., disposed / arranged on the substrate SUB). The substrate SUB and / or the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least a portion of circuit components and / or lines, etc. The conductive patterns may include copper, but one or more embodiments are not limited thereto.

[0115] The circuit elements may include the individual sub-pixel circuits SPC of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see reference). Figure 2The sub-pixel circuit (SPC) may include transistors and one or more capacitors. Each transistor may include a semiconductor portion and a gate electrode, the semiconductor portion including a source region, a drain region, and a channel region, the gate electrode being stacked with the semiconductor portion. In one or more embodiments, where the substrate SUB includes a silicon substrate (e.g., formed from a silicon substrate), the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer (PCL) as a conductive pattern of the pixel circuit layer (PCL). In one or more embodiments, where the substrate SUB includes a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer (PCL). Each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated). For example, each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated) on a plane defined in a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated) on a third direction DR3, with an insulating layer located therebetween (e.g., the insulating layer is placed between every two electrodes).

[0116] The lines of the pixel circuit layer (PCL) may include signal lines, such as gate lines, emit control lines, and data lines, connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The lines may also include connections to... Figure 2 The first power voltage node VDDN line. Additionally, the line may include connections to... Figure 2 The second power voltage node VSSN line.

[0117] The light-emitting element layer (LDL) may include an anode electrode (AE), a pixel-defining layer (PDL), an emission structure (EMS), and a cathode electrode (CE).

[0118] The anode electrode AE ​​can be on the pixel circuit layer PCL (e.g., disposed / arranged on the pixel circuit layer PCL). The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can include an opaque conductive material capable of reflecting light, but one or more embodiments are not limited thereto.

[0119] A pixel defining layer (PDL) may be disposed on the anode electrode AE. The PDL may include openings (OPs) that expose portions of the anode electrode AE. Each emission region corresponding to the first sub-pixel SP1 through the third sub-pixel SP3 may be defined by the openings (OPs) in the PDL. In one or more embodiments, each emission region corresponding to the first sub-pixel SP1 through the third sub-pixel SP3 may be understood as being defined by the anode electrode AE. In regions adjacent to the boundaries of adjacent sub-pixels, the PDL may include separators that cause discontinuities at the emission structure EMS. In this case, each emission region corresponding to the first sub-pixel SP1 through the third sub-pixel SP3 may be understood as being defined by the separators in the PDL.

[0120] In one or more embodiments, the pixel defining layer (PDL) may include an inorganic material. In this case, the pixel defining layer (PDL) may include multiple inorganic layers stacked on top of each other. For example, the pixel defining layer (PDL) may include silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x In one or more embodiments, the pixel-defining layer (PDL) may include an organic material. However, the material of the pixel-defining layer (PDL) is not limited to the foregoing examples.

[0121] The emission structure EMS can be located on an anode electrode AE ​​exposed through an opening OP in the pixel-defining layer PDL (e.g., disposed on an anode electrode AE ​​exposed through an opening OP in the pixel-defining layer PDL). The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0122] In one or more embodiments, the emission structure EMS may fill the opening OP in the pixel-defining layer PDL and be disposed over the entire surface of the upper portion of the pixel-defining layer PDL. For example, the emission structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least some of the layers in the emission structure EMS may be interrupted or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, one or more embodiments are not limited to the foregoing examples. For example, the portions of the emission structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each (e.g., each of the plurality of portions of the emission structure EMS) may be disposed in a corresponding opening OP in the pixel-defining layer PDL.

[0123] The cathode electrode CE can be on the emitter structure EMS (e.g., disposed / arranged on the emitter structure EMS). The cathode electrode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. Thus, the cathode electrode CE can be configured as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0124] The cathode electrode CE can be a thin-film metal layer with a thickness sufficient to allow light emitted from the emitting structure EMS to pass through it. The cathode electrode CE can include a metallic material and / or a transparent conductive material with a relatively small thickness (e.g., made of a metallic material and / or a transparent conductive material with a relatively small thickness). In one or more embodiments, the cathode electrode CE can include at least one of one or more suitable transparent conductive materials (including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and / or gallium tin oxide). In one or more embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and compounds or mixtures thereof. However, the material of the cathode electrode CE is not limited to the foregoing examples.

[0125] The anode electrode AE ​​(e.g., any one of the anode electrodes AE, e.g., any one selected from the anode electrodes AE), the portion of the emitting structure EMS superimposed on the anode electrode AE, and the portion of the cathode electrode CE superimposed on this portion of the emitting structure EMS can be understood as constituting a light-emitting element LD (see [link to LD]). Figure 2 For example, each of the light-emitting elements in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the emitting structure EMS superimposed on the anode electrode AE, and a portion of the cathode electrode CE superimposed on the portion of the emitting structure EMS. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported to the emitting layer of the emitting structure EMS, thus forming excitons. If the excitons transition from an excited state or relax to the ground state, light can be generated (e.g., light can be generated when excitons transition from an excited state or relax to the ground state). The brightness of the light can be determined based on the amount of current flowing through the emitting layer. The wavelength range of the light to be generated can be determined based on the construction of the emitting layer. For example, the brightness of the light is determined by the amount of current flowing through the emitting layer (e.g., charge carriers (holes and electrons)), and the wavelength range of the light is determined by the construction of the emitting layer.

[0126] The encapsulation layer TFE can be on the cathode electrode CE (e.g., disposed on the cathode electrode CE). The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent or reduce the penetration of oxygen and / or water, etc., into the light-emitting element layer LDL. In one or more embodiments, the encapsulation layer TFE can include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layers can include silicon nitride, silicon oxide, and / or silicon oxynitride (SiO2). x N y For example, the organic layer may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or benzocyclobutene (BCB). However, the materials of the organic and inorganic layers of the encapsulation layer TFE are not limited to the foregoing examples.

[0127] The optical functional layer (OFL) can be on the encapsulation layer TFE (e.g., set / arranged on the encapsulation layer TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens layer (LA).

[0128] A color filter layer (CFL) can be disposed between the encapsulation layer (TFE) and the lens layer (LA). The CFL can be configured to filter light emitted from the emission structure (EMS) and selectively output light within a wavelength range and / or color corresponding to each sub-pixel (SP). The CFL may include color filters (CFs) corresponding to first sub-pixels SP1 through third sub-pixels SP3, respectively. Each of the color filters (CFs) allows light within a wavelength range corresponding to the associated sub-pixel (SP) to pass through it. For example, the color filter (CF) corresponding to the first sub-pixel (SP1) allows red light to pass through it, the color filter (CF) corresponding to the second sub-pixel (SP2) allows green light to pass through it, and the color filter (CF) corresponding to the third sub-pixel (SP3) allows blue light to pass through it. Depending on the light emitted from the emission structure (EMS) of each sub-pixel (SP), at least some of the color filters (CFs) may not be provided.

[0129] The lens layer LA can be on the color filter layer CFL (e.g., disposed / arranged on the color filter layer CFL). The lens layer LA may include lenses LS corresponding to the first sub-pixels SP1 to the third sub-pixels SP3, respectively. Each of the lenses LS can output and guide light emitted from the emission structure EMS along a desired path, thereby improving light output efficiency. The lens layer LA may have a relatively high refractive index. For example, the lens layer LA may have a higher refractive index than the outer coating OC. In one or more embodiments, the lenses LS may include an organic material. In one or more embodiments, the lenses LS may include an acrylic material. However, the material of the lenses LS is not limited to the foregoing examples.

[0130] In one or more embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens layer LA may be offset in a direction parallel to the plane defined on the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the center of each color filter CF and the center of each lens LS may be aligned with or superimposed on the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may be completely superimposed on the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens layer LA. In the region of the display area DA adjacent to the non-display area NDA, if viewed on the third direction DR3, the center of the color filter CF and the center of the lens LS may be offset in the planar direction from the center of the corresponding opening OP of the pixel defining layer PDL (e.g., when viewed on the third direction DR3, the center of the color filter CF and the center of the lens LS may be offset in the planar direction from the center of the corresponding opening OP of the pixel defining layer PDL). For example, in the region adjacent to the non-display region NDA within the display region DA, each opening OP of the pixel-defining layer PDL can be partially superimposed with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens layer LA. Therefore, light emitted from the emitting structure EMS in the central region of the display region DA can be effectively output in the normal direction of the display surface. Light emitted from the emitting structure EMS around the outer edge of the display region DA can be effectively output in a direction inclined at an angle relative to the normal direction of the display surface. For example, in one or more embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens layer LA can be offset in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel-defining layer PDL. Specifically, in the central region of the display region DA, the center of each color filter CF and the center of each lens LS can be aligned with the center of the corresponding opening OP of the pixel-defining layer PDL, resulting in complete superposition. However, in the region adjacent to the non-display region NDA within the display area DA, the centers of the color filter CF and the lens LS can be offset from the center of the corresponding opening OP of the pixel-defining layer PDL in the planar direction, resulting in partial superposition when viewed in the third direction DR3, which is the vertical direction. Therefore, light emitted from the emission structure EMS in the central region of the display area DA can be effectively output in the normal direction of the display surface. Conversely, light emitted from the emission structure EMS around the outer edge of the display area DA can be effectively output in a direction inclined at a certain angle relative to the normal direction of the display surface.

[0131] The outer coating OC can be disposed on the lens layer LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the emission structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include one or more suitable materials for protecting the underlying layers from foreign matter such as dust and / or water. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include epoxy resin, but one or more embodiments are not limited thereto. The outer coating OC can have a lower refractive index than the lens layer LA.

[0132] A cover window (CW) may be on the outer coating (OC) (e.g., disposed / arranged on the outer coating). The cover window (CW) may be configured to protect the underlying layer. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but one or more embodiments are not limited thereto. For example, the cover window (CW) may be an encapsulating glass layer configured to protect components disposed below it. In one or more embodiments, a cover window (CW) may not be provided.

[0133] Figure 6 It is shown Figure 5 A plan view of one or more embodiments of the first pixel PXL1. Figure 6 For the purpose of clarity and concise explanation, the diagram is shown schematically. Figure 5 The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The other pixels PXL can be constructed in essentially the same way as the first pixel PXL1.

[0134] Reference Figure 5 and Figure 6 The first pixel PXL1 may include the first sub-pixel SP1 to the third sub-pixel SP3 arranged on the first direction DR1.

[0135] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA formed around the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA formed around the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA formed around the third emission region EMA3.

[0136] The first emission region EMA1 can be a light-emitting structure EMS (see reference). Figure 5 The first emission region EMA2 can be the region where light is emitted from the emission structure EMS corresponding to the second sub-pixel SP1. The second emission region EMA3 can be the region where light is emitted from the emission structure EMS corresponding to the third sub-pixel SP3.

[0137] Figure 7 It is according to one or more embodiments of this disclosure along Figure 6 A sectional view taken from line I-I'.

[0138] Reference Figure 7 It provides a substrate SUB and a pixel circuit layer PCL arranged on the substrate SUB.

[0139] The substrate SUB may include a silicon wafer substrate formed by semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0140] The pixel circuit layer (PCL) can be on the substrate SUB (e.g., disposed / arranged on the substrate SUB). The substrate SUB and the pixel circuit layer (PCL) can include individual circuit elements for the first sub-pixel SP1 through the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer (PCL) can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 can be a sub-pixel circuit (SPC) included in the first sub-pixel SP1 (see reference). Figure 2 The transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 For clarity and brevity, only one transistor for each subpixel is shown, and the remaining circuit elements are not presented.

[0141] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0142] The source region SRA and drain region DRA can be disposed in the substrate SUB. The well WL can be formed at the substrate SUB (e.g., disposed in the substrate SUB) by an ion implantation process. The source region SRA and drain region DRA can be disposed spaced apart and / or separated from each other in the well WL (e.g., spaced apart or separated). The region between the source region SRA and drain region DRA in the well WL can be defined as a channel region. The gate electrode GE can be stacked with the channel region between the source region SRA and drain region DRA and can be disposed at the pixel circuit layer PCL (e.g., disposed in the pixel circuit layer PCL). The gate electrode GE can be spaced apart and / or separated from the well WL or channel region by an insulating layer such as the gate insulating layer GI (e.g., spaced apart or separated). The gate electrode GE can include a conductive material.

[0143] Multiple layers of a pixel circuit layer PCL (e.g., multiple layers included in the pixel circuit layer PCL) may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection SRC passing through one or more insulating layers.

[0144] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be set as one of the transistors of the first sub-pixel SP1.

[0145] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be constructed in essentially the same way as the transistor T_SP1 of the first sub-pixel SP1.

[0146] Thus, the substrate SUB and the pixel circuit layer PCL may include the individual circuit elements of the first sub-pixel SP1 to the third sub-pixel SP3.

[0147] The via layer VIAL can be on the pixel circuit layer PCL (e.g., disposed / arranged on the pixel circuit layer PCL). The via layer VIAL can cover the pixel circuit layer PCL and has an overall flat surface. The via layer VIAL is configured to planarize the stepped portions on the pixel circuit layer PCL. The via layer VIAL can include silicon oxide (SiO2). x Silicon nitride (SiN) x The embodiment may contain at least one of silicon carbonitride (SiCN) and silicon carbonitride (SiCN), but one or more embodiments are not limited thereto.

[0148] The light-emitting element layer (LDL) can be disposed on the via layer (VIAL). The LDL may include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1 to a third anode electrode AE3, a pixel defining layer (PDL), an emission structure (EMS), and a cathode electrode (CE).

[0149] The first reflective electrodes RE1 to the third reflective electrodes RE3 can be formed on the via layer VIAL at the first sub-pixel SP1 to the third sub-pixel SP3 respectively (e.g., respectively disposed / arranged in the first sub-pixel SP1 to the third sub-pixel SP3). Each of the first reflective electrodes RE1 to the third reflective electrodes RE3 can contact a circuit element arranged in the pixel circuit layer PCL through a corresponding via through the via layer VIAL.

[0150] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, which are configured to reflect light emitted from the emitting structure EMS toward the display surface (or cover window CW). The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include metallic materials suitable for reflecting light. The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti) and / or alloys of two or more materials selected from the foregoing materials, but one or more embodiments are not limited thereto.

[0151] In one or more embodiments, the connecting electrode may be disposed below each of the first reflective electrode RE1 to the third reflective electrode RE3. The connecting electrode may enhance the electrical connection characteristics between the corresponding reflective electrode and the corresponding circuit element of the pixel circuitry layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), and / or tantalum nitride (TaN), but one or more embodiments are not limited thereto. In one or more embodiments, the corresponding reflective electrode may be positioned between multiple layers of the connecting electrode.

[0152] A buffer pattern BFP may be disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3 (e.g., at least one of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3). The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but one or more embodiments are not limited thereto. Because of the arrangement of the buffer pattern BFP, the height of the corresponding reflective electrode on the third-direction DR3 can be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL, thus adjusting the height of the first reflective electrode RE1.

[0153] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflection mirror. For example, each of the first reflecting electrodes RE1 to the third reflecting electrodes RE3 and the cathode electrode CE can provide a resonant structure in the corresponding sub-pixel. Light emitted from the emission layer of the emission structure EMS can be amplified by reciprocating between the corresponding reflecting electrode and the cathode electrode CE. The amplified light can be output through the cathode electrode CE. In this way, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance for light emitted from the emission layer of the corresponding emission structure EMS.

[0154] Due to the buffer pattern BFP, the first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels. This adjusted resonant distance allows for effective amplification of light within a specific wavelength range (e.g., red). Therefore, the first sub-pixel SP1 can efficiently and effectively output light within the corresponding wavelength range.

[0155] exist Figure 7 In this embodiment, the buffer pattern BFP is disposed in the first sub-pixel SP1 but not in the second sub-pixels SP2 and SP3, but one or more embodiments are not limited thereto. The buffer pattern BFP may also be disposed in at least one of the second sub-pixels SP2 and SP3, allowing adjustment of the resonant distance of at least one of the second sub-pixels SP2 and SP3. For example, the first sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE may be less than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be less than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0156] To planarize the stepped portions (e.g., height differences or steps between different layers) between the first reflective electrode RE1 and the third reflective electrode RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrodes RE1 to RE3. The planarization layer PLNL can cover the entire surface of the first reflective electrodes RE1 to RE3 and the via layer VIAL and has a flat surface. In one or more embodiments, the planarization layer PLNL may not be provided.

[0157] On the planarization layer PLNL, the first anode electrode AE1 to the third anode electrode AE3 can be arranged to be superimposed on the first reflective electrode RE1 to the third reflective electrode RE3, respectively. If viewed on a third-direction DR3, the first anode electrode AE1 to the third anode electrode AE3 can have the same... Figure 6 The first emission regions EMA1 to the third emission regions EMA3 have similar shapes (for example, when viewed on a third-direction DR3, the first anode electrode AE1 to the third anode electrode AE3 may have the same shape as...). Figure 6(The first emission region EMA1 to the third emission region EMA3 have similar shapes). The first anode electrode AE1 to the third anode electrode AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0158] In one or more embodiments, the first anode electrode AE1 to the third anode electrode AE3 may include a transparent conductive material (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO)). x The materials used for the first anode electrode AE1 to the third anode electrode AE3 are at least one of indium gallium zinc oxide (IGZO) and / or indium tin zinc oxide (ITZO). However, the materials used for the first anode electrode AE1 to the third anode electrode AE3 are not limited to the foregoing examples. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0159] The pixel defining layer (PDL) can be disposed on portions of the first anode electrode AE1 to the third anode electrode AE3 and the planarization layer PLNL. The pixel defining layer (PDL) may include openings (OP) that expose the portions of the first anode electrode AE1 to the third anode electrode AE3. The region superimposed on the pixel defining layer (PDL) can be understood as the boundary region (BDA) between adjacent sub-pixels (SP).

[0160] In one or more embodiments, the pixel defining layer (PDL) may include a plurality of inorganic insulating layers. Each of the inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, the pixel defining layer PDL may include a first inorganic insulating layer ISL1, a second inorganic insulating layer ISL2, and a third inorganic insulating layer ISL3 stacked sequentially. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may include silicon nitride and / or silicon oxide, but one or more embodiments are not limited thereto. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may have a stepped profile in each adjacent region of the opening OP.

[0161] A pixel-defined layer (PDL) may include separators (SPRs) disposed in a boundary region (BDA) between adjacent sub-pixels (SP). For example, separators (SPRs) may be disposed in each of the boundary regions (BDA) between sub-pixels (SP).

[0162] The separator SPR can cause discontinuities in the emission structure EMS within the boundary region BDA. For example, the emission structure EMS can be interrupted or bent within the boundary region BDA by the separator SPR. Therefore, the structures corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 respectively... Figure 6 The first emission region EMA1 to the third emission region EMA3 can be defined along the separator SPR of the pixel definition layer PDL.

[0163] The separator SPR can be disposed in or on the pixel-defining layer PDL. The pixel-defining layer PDL may include one or more trenches TRCH1 and TRCH2 in the boundary region BDA as separator SPRs. In one or more embodiments, as... Figure 7 As shown, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and partially through the planarization layer PLNL. In one or more embodiments, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the planarization layer PLNL and partially through the via layer VIAL. In one or more embodiments, one or more trenches TRCH1 and TRCH2 may at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be located at one or more trenches TRCH1 and TRCH2 (e.g., disposed within one or more trenches TRCH1 and TRCH2).

[0164] exist Figure 7 In this embodiment, two trenches TRCH1 and TRCH2 are disposed in the boundary region BDA. However, one or more embodiments are not limited to the foregoing example. For example, the pixel-defining layer PDL may include one trench in the boundary region BDA. In one or more embodiments, the pixel-defining layer PDL may include three or more trenches in the boundary region BDA.

[0165] Due to the first trench TRCH1 and the second trench TRCH2, discontinuities such as the first gap VD1 and the second gap VD2 can be formed in the boundary region BDA at the emitter structure EMS (e.g., within the emitter structure EMS). Some layers among the multiple layers stacked in the emitter structure EMS can be interrupted or bent by the first gap VD1 and the second gap VD2. For example, at least one charge generation layer and at least one hole injection layer included in the emitter structure EMS can be cut off at the first gap VD1 and the second gap VD2. Thus, due to the first trench TRCH1 and the second trench TRCH2, the portions of the emitter structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 are at least partially separated from each other. For example, due to the first trench TRCH1 and the second trench TRCH2, the emitter structure EMS within the first sub-pixel SP1 to the third sub-pixel SP3 is at least partially divided. This means that the layers of the emitter structure EMS in these sub-pixels SP are not continuous and are separated by the gaps VD1 and VD2 created by the trenches TRCH1 and TRCH2.

[0166] Depending on the shape of the first trench TRCH1 and the second trench TRCH2, the discontinuity formed at the emission structure EMS can be modified in one or more suitable ways.

[0167] In one or more embodiments, the emission structure EMS can be formed by processes such as vacuum deposition and / or inkjet printing. In this case, a material substantially the same as the emission structure EMS can be positioned in the first trench TRCH1 and the second trench TRCH2 on the bottom surface adjacent to the via layer VIAL.

[0168] The pixel defining layer (PDL) may include additional spacers to allow the emitter structure (EMS) to also include discontinuities adjacent to the boundary region BDA. In one or more embodiments, the uppermost of the first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) of the pixel defining layer (PDL), the third inorganic insulating layer (ISL3), may have a width greater than the width of the second inorganic insulating layer (ISL2) located directly below it. For example, the pixel defining layer (PDL) may have a "T"-shaped or "I"-shaped cross-section in the boundary region BDA. Depending on the shape of the pixel defining layer (PDL), multiple layers included in the emitter structure (EMS) may be at least partially cut off or bent in the boundary region BDA and / or in the region adjacent to the boundary region BDA.

[0169] The emitting structure EMS can be arranged on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL. The emitting structure EMS can be filled in the opening OP of the pixel defining layer PDL and arranged throughout the entire area of ​​the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the emitting structure EMS can be at least partially cut or bent in the boundary region BDA by the separator SPR. Therefore, during the operation of the display panel DP, current leakage from each of the first sub-pixels SP1 to the third sub-pixels SP3 to adjacent sub-pixels through the layer included in the emitting structure EMS can be prevented or reduced. As a result, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0170] The cathode electrode CE can be arranged on the emitting structure EMS. The cathode electrode CE can be commonly arranged in the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can act as a semi-reflective mirror, partially transmitting and partially reflecting the light emitted from the emitting structure EMS.

[0171] The first anode electrode AE1, the portion of the emitting structure EMS superimposed on the first anode electrode AE1, and the portion of the cathode electrode CE superimposed on the first anode electrode AE1 can form a first light-emitting element LD1. The second anode electrode AE2, the portion of the emitting structure EMS superimposed on the second anode electrode AE2, and the portion of the cathode electrode CE superimposed on the second anode electrode AE2 can form a second light-emitting element LD2. The third anode electrode AE3, the portion of the emitting structure EMS superimposed on the third anode electrode AE3, and the portion of the cathode electrode CE superimposed on the third anode electrode AE3 can form a third light-emitting element LD3.

[0172] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can prevent or reduce the penetration of oxygen, and / or water, into the light-emitting element layer LDL.

[0173] To enhance the encapsulation efficiency of the TFE encapsulation layer, an encapsulation film ETF comprising alumina (Al2O3) can be further disposed on the TFE encapsulation layer. The alumina-containing encapsulation film ETF can be positioned on the upper surface of the TFE encapsulation layer facing the optical functional layer OFL and / or below the lower surface of the TFE encapsulation layer facing the light-emitting element layer LDL.

[0174] The encapsulation film ETF, including alumina, can be formed using atomic layer deposition (ALD). However, one or more embodiments are not limited to the foregoing examples. Films comprising at least one of one or more suitable materials adapted to enhance encapsulation efficiency can be further disposed above and below the encapsulation layer TFE.

[0175] An optical functional layer (OFL) can be disposed on an encapsulation film ETF. In one or more embodiments, the optical functional layer (OFL) can be attached to the encapsulation film ETF via an adhesive layer (APL). For example, the optical functional layer (OFL) can be manufactured by a separate process and attached to the encapsulation layer TFE via the adhesive layer (APL). The adhesive layer (APL) can also be used to protect a lower layer including the encapsulation film ETF and an upper layer including the color filter layer CFL. The adhesive layer (APL) can comprise an acrylic resin.

[0176] The optical functional layer OFL may include a color filter layer CFL and a lens layer LA. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first color filter CF1 to the third color filter CF3 can be used to transmit light in different wavelength ranges. For example, the first color filter CF1 to the third color filter CF3 can transmit red light, green light, and blue light, respectively.

[0177] In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be partially superimposed on each other in the boundary region BDA. In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart and / or separated from each other (e.g., spaced apart or separated), and the black matrix may be disposed between the first color filter CF1 to the third color filter CF3.

[0178] The lens layer LA can be disposed on the color filter layer CFL. The lens layer LA may include a first lens LS1 to a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first lens LS1 to the third lens LS3 can respectively guide the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 into the desired path, thereby enhancing the light output efficiency.

[0179] The outer coating OC can be disposed on the lens layer LA. The outer coating OC can be configured to protect the underlying layer from foreign matter such as dust and / or water. The cover window CW can be disposed on the outer coating OC.

[0180] Figure 8 It is shown Figure 4 A magnified plan view of the alignment area AA. Figure 9 It is along Figure 8 The sectional view taken from line II-II'.

[0181] Reference Figure 8 and Figure 9Alignment key AK can be located on the substrate SUB at a portion of the alignment region AA (e.g., set / arranged within a portion of the alignment region AA). The substrate layer BSL can be located on the substrate SUB throughout the entire alignment region AA, excluding alignment key AK (e.g., arranged on the substrate SUB). For example, the substrate layer BSL can define an opening OP' corresponding to alignment key AK. Alignment key AK can be arranged at the opening OP' of the substrate layer BSL. Therefore, in a plan view, the substrate layer BSL can surround the periphery of alignment key AK.

[0182] The alignment bond AK can have a shape that protrudes from the upper surface of the substrate layer BSL on the third-direction DR3. For example, the alignment bond AK can be formed with an embossed pattern. The alignment bond AK can include inorganic materials. The alignment bond AK can have a multilayer structure formed by stacking inorganic layers including inorganic materials. More specifically, the alignment bond AK can include at least one of tetraethyl orthosilicate (TEOS), plasma-enhanced oxide (PEOX), and silicon nitride.

[0183] The alignment key AK can have a cross shape in a plan view. However, in embodiments, the shape of the alignment key AK is not limited to the foregoing example.

[0184] The substrate layer BSL may include a first substrate layer BSL1 and a second substrate layer BSL2. The first substrate layer BSL1 may be on a substrate SUB (e.g., disposed / arranged on the substrate SUB). One or more suitable layers, including one or more conductive layers and / or insulating layers, may be disposed between the first substrate layer BSL1 and the substrate SUB. The second substrate layer BSL2 may be on the first substrate layer BSL1 (e.g., disposed on the first substrate layer BSL1). An opening in the first substrate layer BSL1 corresponding to the alignment key AK and an opening in the second substrate layer BSL2 corresponding to the alignment key AK may form an opening OP' included in the substrate layer BSL.

[0185] The reflectivity of the first substrate layer BSL1 can be higher than that of the second substrate layer BSL2. For example, the first substrate layer BSL1 may comprise aluminum, and the second substrate layer BSL2 may comprise titanium nitride. However, one or more embodiments are not limited thereto.

[0186] A capping layer CPL can be disposed on the alignment key AK and the substrate layer BSL. The capping layer CPL can cover the entire alignment area AA, thereby (e.g., simultaneously) covering both the alignment key AK and the substrate layer BSL.

[0187] The capping CPL may include inorganic materials. The capping CPL may include materials with high transmittance and low reflectance. The capping CPL may include at least one of alumina and acrylic resin. Therefore, the capping CPL can reduce the reflectance of the surfaces of the alignment bond AK and the substrate layer BSL.

[0188] Figure 10 It is shown Figure 9 An enlarged cross-sectional view of the capping layer CPL.

[0189] Further reference Figure 10 The capping layer CPL may include a first capping layer CPL1 to a third capping layer CPL3. The first capping layer CPL1 may be on the alignment key AK and the second substrate layer BSL2 (e.g., disposed / arranged on the alignment key AK and the second substrate layer BSL2) and may include alumina. The second capping layer CPL2 may be on the first capping layer CPL1 (e.g., disposed / arranged on the first capping layer CPL1) and may include acrylic resin. The third capping layer CPL3 may be on the second capping layer CPL2 (e.g., disposed / arranged on the second capping layer CPL2) and may include acrylic resin. However, one or more embodiments are not limited to the foregoing examples. In one or more embodiments, the capping layer CPL may include only the first capping layer CPL1. In one or more embodiments, the capping layer CPL may include only the first capping layer CPL1 and the second capping layer CPL2, which contain different materials.

[0190] Further reference Figure 7 The first capping layer CPL1 in the alignment region AA may be made of the same material as the encapsulation film ETF in the display region DA. For example, the first capping layer CPL1 in the alignment region AA may be formed concurrently (e.g., simultaneously) with the encapsulation film ETF in the display region DA. Furthermore, the second capping layer CPL2 in the alignment region AA may be made of the same material as the adhesive layer APL in the display region DA. For example, the second capping layer CPL2 in the alignment region AA may be formed concurrently (e.g., simultaneously) with the adhesive layer APL in the display region DA. Furthermore, the third capping layer CPL3 in the alignment region AA may be made of the same material as the lens layer LA in the display region DA. For example, the third capping layer CPL3 in the alignment region AA may be formed concurrently (e.g., simultaneously) with the lens layer LA in the display region DA.

[0191] In one or more embodiments, a capping layer CPL comprising inorganic material may be disposed over the entire alignment region AA on the alignment key AK and the substrate layer BSL, thereby protecting the substrate layer BSL. Therefore, the capping layer CPL can prevent or reduce the loss of the second substrate layer BSL2 during the manufacturing process. The alignment key AK is identified by the reflectivity difference between the alignment key AK and the substrate layer BSL. The reflectivity difference between the alignment key AK and the substrate layer BSL can be maintained by the capping layer CPL. Furthermore, the capping layer CPL can reduce the reflectivity of the alignment region AA. As a result, the total reflectivity of the alignment region AA is reduced, thereby mitigating identification failures due to the high reflectivity of the first substrate layer BSL1. Therefore, due to the enhanced identification rate of the alignment key AK, the reliability of the display device manufactured using the alignment key AK can be improved.

[0192] Figures 11 to 16 This is a diagram illustrating the operation (e.g., steps) of a method for manufacturing a display device 100 according to an embodiment of the present disclosure.

[0193] Reference Figure 11 It can be included in the non-display area NDA on the substrate SUB (see reference). Figure 4 Alignment area AA in ) (refer to Figure 8 A first substrate layer BSL1 is formed at the location. For example, the first substrate layer BSL1 may include aluminum (e.g., formed of aluminum). One or more conductive layers and / or insulating layers may be formed between the substrate SUB and the first substrate layer BSL1.

[0194] Reference Figure 12 A second substrate layer BSL2 can be formed on the first substrate layer BSL1 at the alignment region AA. The reflectivity of the material forming the first substrate layer BSL1 can be higher than that of the material forming the second substrate layer BSL2. For example, the second substrate layer BSL2 may include titanium nitride (e.g., formed from titanium nitride).

[0195] Reference Figure 13 An opening OP' can be formed by patterning portions of the first substrate layer BSL1 and the second substrate layer BSL2. The opening OP' can be formed at a portion of the alignment region AA. In one or more embodiments, a single opening OP' can be formed concurrently (e.g., simultaneously) in the first substrate layer BSL1 and the second substrate layer BSL2. In one or more embodiments, a first opening can be formed at the first substrate layer BSL1, and a second opening can be formed at the second substrate layer BSL2, overlapping the first opening at the first substrate layer BSL1, thus forming a single large opening OP'. As a result, a substrate layer BSL that defines the opening OP' and includes the first substrate layer BSL1 and the second substrate layer BSL2 can be formed.

[0196] Reference Figure 14 Alignment key AK can be formed at the opening OP'. Therefore, alignment key AK can be positioned within a portion of the alignment region AA, and the substrate layer BSL is arranged around alignment key AK. Alignment key AK can be formed to protrude from the upper surface of the substrate layer BSL. For example, alignment key AK can be formed with an embossed pattern. Here, alignment key AK can have a multilayer structure formed by stacking inorganic layers including inorganic materials.

[0197] The alignment key AK can be formed in a cross shape in a plan view. However, in one or more embodiments, the shape of the alignment key AK is not limited to the foregoing example.

[0198] Reference Figure 15 and Figure 16 The capping layer CPL can be formed on the alignment key AK and the substrate layer BSL throughout the alignment region AA (e.g., the capping layer CPL can be formed on the alignment key AK and the substrate layer BSL throughout the alignment region AA). The capping layer CPL can include inorganic materials. In one or more embodiments, the capping layer CPL can include a first capping layer CPL1 to a third capping layer CPL3 that are sequentially stacked and include different materials.

[0199] For example, in the alignment region AA, a first capping layer CPL1 can be formed on the alignment bond AK and the substrate layer BSL. The first capping layer CPL1 may include aluminum oxide (e.g., formed of aluminum oxide).

[0200] In the alignment region AA, the second capping layer CPL2 may be formed on the first capping layer CPL1 (e.g., the second capping layer CPL2 may be formed on the first capping layer CPL1). The second capping layer CPL2 may include an acrylic resin (e.g., formed from an acrylic resin).

[0201] In the alignment region AA, the third capping layer CPL3 may be formed on the second capping layer CPL2 (e.g., the third capping layer CPL3 may be formed on the second capping layer CPL2). The third capping layer CPL3 may include an acrylic resin (e.g., formed from an acrylic resin).

[0202] As a result, a capping layer CPL can be formed, comprising a first capping layer CPL1 to a third capping layer CPL3 containing different materials.

[0203] In one or more embodiments, only the first capping layer CPL1 can be formed as a capping layer CPL. In one or more embodiments, the first capping layer CPL1 and the second capping layer CPL2, comprising different materials, can be formed as capping layer CPLs. For example, the capping layer CPL may comprise alumina and may optionally comprise acrylic resin.

[0204] Further reference Figure 7A light-emitting element (LD) can be formed on a substrate SUB at a display area DA. In the display area DA, an encapsulation layer TFE and an encapsulation film ETF can be formed on the light-emitting element LD (e.g., the encapsulation layer TFE and the encapsulation film ETF can be formed on the light-emitting element LD). The encapsulation film ETF can include aluminum oxide (e.g., formed of aluminum oxide). A first capping layer CPL1 can comprise substantially the same material as the encapsulation film ETF in the display area DA (e.g., formed of substantially the same material as the encapsulation film ETF in the display area DA), and can be formed concurrently (e.g., simultaneously).

[0205] In the display area DA, the adhesive layer APL may be formed on the encapsulation film ETF (e.g., the adhesive layer APL may be formed on the encapsulation film ETF). The adhesive layer APL may include an acrylic resin (e.g., formed from an acrylic resin). The second capping layer CPL2 may comprise substantially the same material as the adhesive layer APL in the display area DA (e.g., formed from substantially the same material as the adhesive layer APL in the display area DA), and may be formed concurrently (e.g., simultaneously).

[0206] In the display area DA, the color filter layer CFL can be formed on the adhesive layer APL (e.g., the color filter layer CFL can be formed on the adhesive layer APL). In the display area DA, the lens layer LA can be formed on the color filter layer CFL (e.g., the lens layer LA can be formed on the color filter layer CFL). The lens layer LA can be formed in a lens shape by forming an acrylic resin layer throughout the display area DA and then patterning the acrylic resin layer. The third capping layer CPL3 can comprise substantially the same material as the lens layer LA in the display area DA (e.g., formed from substantially the same material as the lens layer LA in the display area DA) and can be formed concurrently (e.g., simultaneously). However, unlike the lens layer LA, the patterning process of the third capping layer CPL3 may not be performed.

[0207] In one or more embodiments, since a capping layer CPL comprising inorganic material is disposed over the entire alignment region AA on the alignment key AK and the substrate layer BSL, the capping layer CPL can protect the substrate layer BSL, thereby preventing or reducing etching of the substrate layer BSL during the manufacturing process. Therefore, due to the capping layer CPL, the reflectivity of the alignment region AA, on which the alignment key AK and the substrate layer BSL are disposed, can be reduced. As a result, recognition failures of the alignment key AK due to high reflectivity during the manufacturing process can be reduced, thereby enhancing the reliability of display devices produced using the alignment key AK.

[0208] Furthermore, since the components of the cover layer CPL can be made of substantially the same materials (e.g., formed from substantially the same materials) and formed by substantially the same process as the corresponding components in the display area DA, separate processes and materials are not desired or required, thereby enhancing manufacturing process efficiency.

[0209] The display device according to one or more embodiments can be adapted to one or more suitable types (categories) of electronic devices. In one or more embodiments, the electronic device includes the above-described display device, and may also include other modules or devices with additional functions in addition to the display device.

[0210] Figure 17 This is a block diagram of an electronic device 10 according to one or more embodiments. (Refer to...) Figure 17 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0211] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0212] The memory 13 can store data and / or information used to operate the processor 12 and / or the display module 11. If the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11 (e.g., when the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11). The display module 11 can process the provided signals and output image information on the display screen.

[0213] The power module 14 may include a power supply module (such as a power adapter and / or battery device) and a power conversion module. The power conversion module converts the power supplied by the power supply module and generates power to operate the electronic device 10.

[0214] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to one or more embodiments as described above. Furthermore, in terms of function, some of the modules included in the electronic device 10 may be included in the display device, while other modules may be disposed separately from the display device. For example, the display module 11 may be included in the display device, while the processor 12, memory 13, and power module 14 may not be included in the display device but may be disposed separately in the electronic device 10.

[0215] Figure 18 A schematic diagram of one or more suitable embodiments of an electronic device is shown.

[0216] Reference Figure 18 The embodiment of the application display device includes one or more suitable types (categories) of electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c), and vehicle electronic devices 10_3 including display modules (such as central information displays (CIDs) arranged on the dashboard, central instrument panel, and dashboard of a vehicle, as well as interior mirror displays).

[0217] As described above, because a capping layer comprising inorganic materials is arranged over the alignment keys and substrate layer throughout the alignment area, the capping layer protects the substrate layer and reduces the reflectivity of the alignment area where the alignment keys and substrate layer are arranged. Therefore, alignment key recognition failures due to high reflectivity during the manufacturing process can be reduced. Consequently, the alignment key recognition rate is enhanced, which improves the reliability of display devices manufactured using alignment keys. In summary, by utilizing the presence of an alignment area including multiple alignment keys, the components of the display panel can be well aligned and positioned during the manufacturing process, increasing and improving the production yield and performance of the display panel.

[0218] As used herein, the terms “approximately,” “about,” and similar terms are used as approximations rather than terms of degree and are intended to account for the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” also includes the stated value and means: within an acceptable range of deviation for a particular value, taking into account the measurement in question and the errors associated with the measurement of that particular quantity (i.e., limitations of the measurement system), as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0219] In the context of this disclosure and unless otherwise defined, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively.

[0220] Any numerical range described herein is intended to include all subranges with the same numerical precision contained within the range. For example, the range “1.0 to 10.0” is intended to include all subranges between the minimum value 1.0 and the maximum value 10.0 (and inclusive of the minimum value 1.0 and the maximum value 10.0), that is, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the expressly described range herein.

[0221] Electronic devices / devices, fabrication equipment for them, or any other related devices / devices or components including display devices according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on an integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the device may be implemented on flexible printed circuit films, tape-on-a-carrier packages (TCPs), printed circuit boards (PCBs), or formed on a substrate. Additionally, various components of the device may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0222] Those skilled in the art will understand that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0223] The effects of this disclosure are not limited to the foregoing, and one or more other suitable effects are contemplated herein.

[0224] While the spirit and scope of this disclosure have been described through detailed exemplary embodiments, it should be noted that the above embodiments are merely descriptive and should not be considered limiting. Those skilled in the art will understand that one or more suitable changes, substitutions, and modifications may be made herein without departing from the scope of the disclosure as defined by the claims and their equivalents.

[0225] The scope of this disclosure and its equivalents is not limited to the detailed description herein, but should be defined by the appended claims. Furthermore, all changes or modifications to this disclosure derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of this disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: Base; Multiple light-emitting elements are present on the substrate and in the display area; Alignment key, on the substrate, and at a portion of the alignment area surrounding the non-display area of ​​the display area; and The first capping layer covers the entire alignment area and is formed of an inorganic material.

2. The display device according to claim 1, wherein The display device further includes a substrate layer between the substrate and the first cover layer, and is disposed throughout the alignment area except for the alignment key.

3. The display device of claim 2, Its features are, The substrate layer comprises: a first substrate layer on the substrate; and a second substrate layer between the first substrate layer and the first capping layer. The reflectivity of the first substrate layer is higher than that of the second substrate layer.

4. The display device according to claim 3, characterized in that, wherein, The first substrate layer is formed of aluminum, and The second substrate layer is formed of titanium nitride.

5. The display device according to claim 2, wherein The first capping layer is formed of aluminum oxide.

6. The display device according to claim 5, wherein The display device further includes: A second cover layer, on top of the first cover layer; and The third capping layer is on top of the second capping layer.

7. The display device according to claim 6, characterized in that, wherein The second capping layer is formed of acrylic resin, and The third capping layer is formed of acrylic resin.

8. The display device according to claim 6, characterized in that, The display device further includes: An encapsulating film is placed on the plurality of light-emitting elements in the display area; An adhesive layer is located on the encapsulation film in the display area; A color filter layer is located on the adhesive layer in the display area; and A lens layer is located on the color filter layer in the display area.

9. The display device according to claim 8, characterized in that, in, The first capping layer and the encapsulating film comprise the same material. Wherein, the second cover layer and the adhesive layer comprise the same material, and The third cover layer and the lens layer are made of the same material.

10. The display device according to claim 2, characterized in that, The alignment key protrudes from the upper surface of the substrate layer.

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