Semiconductor device structure

Abstract

A semiconductor device structure is described. The semiconductor device structure includes a plurality of source / drain regions, an interconnect structure disposed above the source / drain regions, a backside interconnect structure disposed below the source / drain regions, and a first conductive feature disposed in the backside interconnect structure. The first conductive feature is electrically connected to a first number of the source / drain regions. The semiconductor device structure further includes a second number of memory devices disposed in the backside interconnect structure, the memory devices electrically connected to the first conductive feature, and the second number is different than the first number.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to several generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process usually provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Utility Model Content

[0004] Some embodiments disclosed herein represent a semiconductor device structure. The semiconductor device structure includes a plurality of source / drain regions, an interconnect structure disposed above the source / drain regions, a back-side interconnect structure disposed below the source / drain regions, and a first conductive feature disposed in the back-side interconnect structure. The first conductive feature is electrically connected to a first number of source / drain regions. The semiconductor device structure further includes a second number of memory devices disposed in the back-side interconnect structure, the memory devices being electrically connected to the first conductive feature, and the second number differing from the first number.

[0005] Another embodiment disclosed herein is a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed above a substrate, and the first source / drain region has a first width. The semiconductor device structure further includes an interconnect structure disposed above the first source / drain region and a first conductive feature disposed below the back side of the substrate. The first conductive feature has a second width significantly larger than the first width, and the first conductive feature is electrically connected to the first source / drain region. The semiconductor device structure further includes a first intermetallic dielectric (IMD) layer disposed below the first conductive feature, a second IMD layer disposed below the first IMD layer, and a plurality of memory devices disposed in the second IMD layer. The memory devices are electrically connected to the first conductive feature and offset from the first source / drain region.

[0006] One embodiment disclosed herein is a semiconductor device structure. The semiconductor device structure includes a plurality of source / drain regions, an interconnect structure disposed above the source / drain regions, a back-side interconnect structure disposed below the source / drain regions, and a first conductive feature disposed in the back-side interconnect structure. The first conductive feature is electrically connected to a first number of source / drain regions. The semiconductor device structure further includes a second number of memory devices disposed in the back-side interconnect structure, the memory devices being electrically connected to the first conductive feature, and the second number differing from the first number. The semiconductor device structure includes three intermetallic dielectric layers disposed between the first conductive feature and the memory devices. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional side view of a semiconductor device structure according to some embodiments;

[0009] Figure 2 A cross-sectional side view of a portion of a semiconductor device structure according to some embodiments;

[0010] Figure 3A and Figure 3B A cross-sectional side view of a portion of a semiconductor device structure according to some embodiments;

[0011] Figures 4A to 4D Various views of a portion of the back-side interconnect structure of a semiconductor device structure according to some embodiments;

[0012] Figure 5 This is a cross-sectional side view of a semiconductor device structure according to some embodiments;

[0013] Figure 6A and Figure 6B A bottom view of a semiconductor device structure according to some embodiments;

[0014] Figure 7 This is a cross-sectional side view of a semiconductor device structure according to an alternative embodiment;

[0015] Figure 8A and Figure 8B This is a bottom view of a semiconductor device structure according to an alternative embodiment;

[0016] Figures 9A to 9I This is a cross-sectional side view of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0017] [Symbol Explanation]

[0018] 100: Semiconductor Device Structure

[0019] 102:Substrate

[0020] 106: Source / Drain (S / D) Region

[0021] 106a: First source region

[0022] 106b: First drain region

[0023] 106c: Second source region

[0024] 106d: Second drain region

[0025] 124, 140: Silicide layer

[0026] 126,407: Conductive contact

[0027] 130: Semiconductor layer

[0028] 132: Internal spacer

[0029] 134: Gate dielectric layer

[0030] 136: Gate electrode layer

[0031] 136a: First gate electrode layer

[0032] 136b: Second gate electrode layer

[0033] 136c: Third gate electrode layer

[0034] 142: Hard mask layer

[0035] 144: Padding

[0036] 150: Isolation Area

[0037] 154:ILD

[0038] 200: Device Layer

[0039] 202: Part

[0040] 300: Interconnection Structure

[0041] 302, 402: IMD layer

[0042] 304, 404: Conductivity characteristics / First conductivity characteristics

[0043] 306, 406: Conductivity characteristics / Secondary conductivity characteristics

[0044] 320: Bonding layer

[0045] 330: Carrier wafer

[0046] 400: Backside interconnect structure

[0047] 403: Barrier Layer

[0048] 405, 409, 420: Conductivity characteristics

[0049] 410: Memory device

[0050] 410a: First Memory Device

[0051] 410b: Second memory device

[0052] 410c: Third Memory Device

[0053] 410d: Fourth Memory Device

[0054] 410e: Fifth Memory Device

[0055] 410f: Sixth Memory Device

[0056] 412: Redistribution layer

[0057] 414: Top electrode layer

[0058] 416: Bottom Electrode Layer

[0059] 418:MTJ layer

[0060] 480: Bottom Electrode Through-Hole (BEVA)

[0061] X, Y, Z: Direction Detailed Implementation

[0062] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0063] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0064] Figure 1 Explain the structure of semiconductor device 100. (For example...) Figure 1 As shown, the semiconductor device structure 100 includes a device layer 200. Device layer 200 includes a substrate 102. Device layer 200 may include one or more devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. In some embodiments, device layer 200 includes transistors, such as nanostructured transistors having multiple channels surrounded by a gate electrode layer. The term nanostructure is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, and beam or strip-shaped material portions, such as those including cylindrical or substantially rectangular cross-sections. The channels of the devices in device layer 200 may be surrounded by a gate electrode layer. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode layer surrounding the channels. In some embodiments, device layer 200 includes devices such as planar FETs, FinFETs, complementary FETs (CFETs), forked FETs, or other suitable devices.

[0065] The semiconductor device structure 100 may further include an interconnect structure 300, which is disposed above the device layer 200 and the substrate 102, such as... Figure 1As shown. An interconnect structure 300 may be disposed on the front side of the device layer 200. The interconnect structure 300 includes various conductive features, such as a plurality of first conductive features 304 and a plurality of second conductive features 306, and an intermetallic dielectric (IMD) layer 302 for separating and isolating the various conductive features 304, 306. In some embodiments, the first conductive features 304 are conductive lines, and the second conductive features 306 are conductive vias. The interconnect structure 300 includes multiple layers of conductive features 304, 306, and the conductive features 304, 306 are disposed in each layer to provide electrical pathways for various devices disposed in the underlying device layer 200. The conductive features 304 and 306 may be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive features 304 and 306 are made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, silicon titanium nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, silicon tungsten nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof.

[0066] IMD layer 302 includes one or more dielectric materials to provide isolation to various conductive features 304, 306. IMD layer 302 may include multiple dielectric layers embedded with multiple layers of conductive features 304, 306. IMD layer 302 is made of a dielectric material, such as SiO2. x SiO x C y H z or SiO x C y Where x, y, and z are integers or non-integers. In some embodiments, the IMD layer 302 includes a low-k dielectric material, the k value of which is less than the k value of silicon oxide.

[0067] like Figure 1As shown, in some embodiments, the semiconductor device structure 100 further includes a back-side interconnect structure 400 located below the device layer 200. The back-side interconnect structure 400 may be disposed on the back side of the device layer 200. The back-side interconnect structure 400 includes various conductive features, such as a plurality of first conductive features 404 and a plurality of second conductive features 406, and an IMD layer 402 for separating and isolating the various conductive features 404, 406. In some embodiments, the first conductive features 404 are conductive lines, and the second conductive features 406 are conductive vias. The back-side interconnect structure 400 includes multiple layers of conductive features 404, 406, and the conductive features 404, 406 are disposed in each layer to provide electrical pathways for various devices disposed in the upper device layer 200. The conductive features 404, 406 may include the same material as the conductive features 304, 306. In some embodiments, the back-side interconnect structure 400 includes a redistribution layer (RDL) 412 disposed at the bottom of the back-side interconnect structure 400, such as... Figure 1 As shown.

[0068] The back-side interconnect structure 400 further includes conductive features 405 that contact the back side of the device layer 200, such as contacting the back side of the substrate 102. Figure 1 As shown. In some embodiments, conductive feature 405 is a power rail coupled to a reference voltage, positive supply voltage, etc., and the power rail can be used to provide power to one or more devices in device layer 200. The back-side interconnect structure 400 helps alleviate routing constraints, which in turn can increase the device density in device layer 200. Furthermore, conductive feature 405 can have a larger size compared to conductive features formed in interconnect structure 300. Therefore, one or more memory devices 410 can be formed near conductive feature 405, and the parasitic capacitance of one or more memory devices 410 can be reduced. In some embodiments, conductive feature 405 is connected to devices in device layer 200 via conductive contacts 407, such as Figure 1 As shown. In some embodiments, conductive feature 405 is connected to conductive feature 304 of interconnect structure 300 via conductive feature 409. Conductive feature 409 may be a via extending through substrate 102 and IMD layer 302 of interconnect structure 300, such as... Figure 1 As shown.

[0069] In some embodiments, one or more memory devices 410 are formed in the back-side interconnect structure 400, such as Figure 1As shown. One or more memory devices 410 may include any suitable memory device. In some embodiments, the memory device 410 is a non-volatile memory device that retains data even after power loss. Examples of non-volatile memory devices include flash memory, magnetic random-access memory (MRAM), embedded MRAM (eMRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric random-access memory (FRAM), resistive random-access memory (RRAM), and phase-change random-access memory (PRAM). In some embodiments, the memory device 410 is an MRAM. One or more memory devices 410 may be located below the conductive feature 405, such as one, two, or three layers below the conductive feature 405. The layers between the conductive feature 405 and the one or more memory devices 410 are represented by dots, such as... Figure 1 As shown. The various arrangements of one or more memory devices 410 relative to conductive features 405 are described in detail below.

[0070] Figure 2 A cross-sectional side view of a portion 202 of a semiconductor device structure 100 according to some embodiments. Figure 2 This illustrates an embodiment of a nanostructured transistor in device layer 200. For example... Figure 2As shown, device layer 200 includes a substrate 102 on which source / drain (S / D) regions 106 are disposed. Substrate 102 may be a semiconductor substrate, such as a bulk silicon substrate. In some embodiments, substrate 102 may be an elemental semiconductor, such as silicon or germanium with a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; other suitable materials; or combinations thereof. Possible substrates 102 may also include silicon-on-insulator (SOI) substrates. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. S / D regions 106 may include semiconductor materials such as Si or Ge, III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. The exemplary S / D region 106 may include, but is not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. The S / D region 106 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. The S / D region 106 may be formed by epitaxial growth methods using CVD, ALD, or MBE. In this disclosure, the source region and drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain region may refer to the source or drain individually or jointly, depending on the context.

[0071] like Figure 2As shown, the S / D region 106 can be connected via one or more semiconductor layers 130, which can serve as channels for a FET. In some embodiments, the FET is a nanostructure FET comprising multiple semiconductor layers 130, and at least a portion of each semiconductor layer 130 is surrounded by a gate electrode layer 136. The semiconductor layers 130 may be made of or comprise materials such as Si, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or other suitable materials. In some embodiments, each semiconductor layer 130 is made of Si. The number of vertically aligned semiconductor layers 130 can range from about 2 to about 6. The gate electrode layer 136 comprises one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 136 comprises a metal. A gate dielectric layer 134 may be disposed between the gate electrode layer 136 and the semiconductor layer 130. The gate dielectric layer 134 may comprise one or more layers, such as an interface layer and a high-k dielectric layer. In some embodiments, the interface layer is an oxide layer, and the high-k dielectric layer includes hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, or other suitable high-k materials.

[0072] The gate dielectric layer 134 and the gate electrode layer 136 may be separated from the S / D region 106 by an inner spacer 132. The inner spacer 132 may include a dielectric material such as SiON, SiCN, SiOC, SiOCN, or SiN. A gate spacer (not shown) may be disposed above the semiconductor layer 130. The gate spacer may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0073] The conductive contact 126 can be disposed in the ILD layer (not shown) and above the S / D area 106, such as... Figure 2As shown. The conductive contact 126 may include one or more conductive materials, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. A silicide layer 124 may be disposed between the conductive contact 126 and the S / D region 106. The conductive contact 126 and the gate electrode layer 136 are electrically isolated by a gate spacer (not shown).

[0074] In some embodiments, such as Figure 2 As shown, a hard mask layer 142 is formed on the back side of substrate 102, and conductive contacts 407 are formed in substrate 102 and hard mask layer 142. In some embodiments, substrate 102 is thinned from the back side before forming hard mask layer 142. Hard mask layer 142 may include any suitable material. In some embodiments, hard mask layer 142 includes a dielectric material, such as SiN, SiCN, SiOCN, SiON, or other suitable dielectric materials. Conductive contacts 407 include a conductive material, such as Co, W, Ru, Mo, Cu, or other suitable materials. In some embodiments, a pad 144 may be formed on the side surface of each conductive contact 407. Each pad 144 may include SiN, SiCN, SiOCN, SiON, or other suitable materials. In some embodiments, pad 144 includes the same material as hard mask layer 142. In some embodiments, the pad 144 is formed by first forming a conformal layer in an opening formed in the hard mask layer 142 and the substrate 102, and then performing an anisotropic etching process to remove the horizontal portion of the conformal layer to form the pad 144 on the side surfaces of the hard mask layer 142 and the substrate 102. Figure 2 As shown, in some embodiments, a silicide layer 140 is formed between each conductive contact 407 and the corresponding S / D region 106. The silicide layer 140 may include TiSi, CoSi, NiSi, TiNiSi, or other suitable materials.

[0075] like Figure 2 As shown, the back-side interconnect structure 400 includes an IMD layer 402 and a conductive feature 405. In some embodiments, a barrier layer 403 is provided between the conductive feature 405 and the IMD layer 402 and between the conductive feature 405 and the hard mask layer 142, such as... Figure 2 As shown. Barrier layer 403 is used to prevent metal from diffusing from conductive feature 405 to hard mask layer 142 and IMD layer 402. In some embodiments, conductive feature 405 comprises a non-diffusion-prone material, and barrier layer 403 is not used. In some embodiments, barrier layer 403 is selectively formed on the dielectric material of IMD layer 402 and hard mask layer 142. Barrier layer 403 may comprise TiN, TaN, Ru, Co, or other suitable materials. Barrier layer 403 may be formed by conformal processes (such as ALD).

[0076] Figure 3A and Figure 3B This is a cross-sectional side view of a partial semiconductor device structure 100 according to some embodiments. Figure 3A and Figure 3B The YZ plane of a portion of a semiconductor device structure 100 according to some embodiments is illustrated. In some embodiments, substrate 102 is removed during back-side processing. Figure 3A As shown, in some embodiments, conductive contacts 126 and silicide layer 124 are formed on the front side of S / D region 106, and conductive contacts 407 and silicide layer 140 are formed on the back side of S / D region 106. In some embodiments, isolation regions 150 (such as shallow trench isolates (STI)) are disposed around conductive contacts 407, such as... Figure 3A As shown.

[0077] In some embodiments, conductive feature 405 is electrically connected via S / D region 106 to conductive features 304, 306 located in interconnect structure 300, such as Figure 3A As shown. In some embodiments, in regions where the S / D region 106 is absent, conductive feature 405 may be electrically connected via conductive feature 409 to conductive features 304, 306 located in the interconnect structure 300, such as... Figure 3B As shown. The conductive feature 409 may be a conductive via and may extend through the isolation region 150 and into the ILD 154. In some embodiments, the conductive feature 409 extends into the conductive contact 126, such as... Figure 3B As shown.

[0078] Figures 4A to 4D Various views of a portion of the back-side interconnect structure 400 of a semiconductor device structure 100 according to some embodiments. Figure 4A This is a cross-sectional view of a portion of the back-side interconnect structure 400 of the semiconductor device structure 100. (See attached image.) Figure 4A As shown, the back-side interconnect structure 400 includes one or more memory devices 410. In some embodiments, the memory device 410 is an MRAM cell, and each MRAM cell includes a top electrode layer 414, a bottom electrode layer 416, and a magnetic tunnel junction (MTJ) layer 418 located between the top electrode layer 414 and the bottom electrode layer 416. The top electrode layer 414 and the bottom electrode layer 416 may each include a conductive material, such as TiN, TaN, Cu, Co, W, Ag, Al, Ru, AlCu, Mo, or combinations thereof.

[0079] MTJ layer 418 is stacked with multiple materials ( Figure 4AThe MTJ layer 418 is deposited above the bottom electrode layer 416 in the form of a tunneling barrier layer (not specified in the text). In some embodiments, the MTJ layer 418 includes a lower ferromagnetic electrode and an upper ferromagnetic electrode spaced apart from each other by a tunneling barrier layer. In some embodiments, the lower ferromagnetic electrode may have a fixed or “pike-tacked” magnetic orientation, while the upper ferromagnetic electrode has a variable or “free” magnetic orientation, which can switch between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other embodiments, the MTJ layer 418 may be vertically “reversed”, such that the lower ferromagnetic electrode has a “free” magnetic orientation, while the upper ferromagnetic electrode has a “pike-tacked” magnetic orientation.

[0080] In some embodiments, the upper and lower ferromagnetic electrodes each comprise or are made of iron, cobalt, nickel, iron-cobalt, nickel-cobalt, cobalt-iron-boron compounds, iron-boron compounds, iron-platinum, iron-palladium, etc. In some embodiments, the tunneling barrier layer provides electrical isolation between the upper and lower ferromagnetic electrodes while still allowing electrons to pass through the tunneling barrier layer under appropriate conditions. The tunneling barrier layer may comprise or be made of magnesium oxide (MgO), aluminum oxide (e.g., Al₂O₃), nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, etc. In some embodiments, the tunneling barrier layer may comprise a non-ferromagnetic metal, such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, etc.

[0081] In some embodiments, one or more memory devices 410 are RRAM, and the MTJ layer 418 is a resistive layer, such as a TaO layer. The top electrode layer 414 may be an Ir layer, and the bottom electrode layer 416 may be a Ta layer. In some embodiments, the thickness of the top electrode layer 414 ranges from about 5 nm to about 10 nm, the thickness of the bottom electrode layer 416 ranges from about 10 nm to about 30 nm, and the thickness of the resistive layer ranges from about 15 nm to about 30 nm.

[0082] Figure 4A Describe a planar MRAM cell, and Figure 4B Explain the vertical MRAM cell. Figure 4B This is a cross-sectional view of a portion of the back-side interconnect structure 400 of the semiconductor device structure 100. (See attached image.) Figure 4B As shown, the bottom electrode layer 416 is formed in the opening and has a "U"-shaped cross-sectional profile. The MTJ layer 418 is formed on the bottom electrode layer 416 and also has a "U"-shaped cross-sectional profile. The top electrode 414 is formed on the MTJ layer 418 and has three sides surrounded by the MTJ layer 418 and the bottom electrode layer 416, as shown. Figure 4B As shown.

[0083] Figure 4C This is a cross-sectional view of a portion of the back-side interconnect structure 400 of the semiconductor device structure 100. (See attached image.) Figure 4C As shown, in some embodiments, one or more memory devices 410 each have a trapezoidal cross-sectional shape. In some embodiments, the top electrode layer 414 has a first width along the X direction, the MTJ layer 418 has a second width along the X direction, and the bottom electrode layer 416 has a third width along the X direction. In some embodiments, the third width is greater than the second width, and the second width is greater than the first width. In some embodiments, each memory device 410 includes a bottom electrode via (BEVA) 480. The BEVA 480 may include the same or different material as the bottom electrode layer 416. In some embodiments, the bottom electrode layer 146 includes a TaN layer and a TiN layer, and the BEVA 480 includes TiN. In some embodiments, the MTJ layer 418 includes a first ferromagnetic layer, a second ferromagnetic layer disposed on the first ferromagnetic layer, a third ferromagnetic layer disposed on the second ferromagnetic layer, a first tunneling barrier layer disposed on a third tunneling barrier layer, a fourth ferromagnetic layer disposed on the first tunneling barrier layer, a second tunneling barrier layer disposed on the fourth tunneling barrier layer, and a capping layer disposed on the second tunneling barrier layer. In some embodiments, the first ferromagnetic layer comprises NiCr, the second ferromagnetic layer comprises CoIr, the third ferromagnetic layer comprises CoFeB, the first tunneling barrier layer comprises MgO, the fourth ferromagnetic layer comprises CoFeB, the second tunneling barrier layer comprises MgO, and the capping layer comprises Ru.

[0084] In some embodiments, the thickness of BEVA 480 ranges from about 35 nm to about 60 nm, the thickness of the bottom electrode layer 416 ranges from about 15 nm to about 45 nm, and the thickness of the top electrode layer 414 ranges from about 15 nm to about 45 nm. In some embodiments, the thickness of the first ferromagnetic layer ranges from about 3 nm to about 7 nm, the thickness of the second ferromagnetic layer ranges from about 1 nm to about 3 nm, the thickness of the third ferromagnetic layer ranges from about 1 nm to about 2 nm, the thickness of the first tunneling barrier layer ranges from about 0.5 nm to about 1.5 nm, the thickness of the fourth ferromagnetic layer ranges from about 1 nm to about 3 nm, the thickness of the second tunneling barrier layer ranges from about 0.5 nm to about 1.5 nm, and the thickness of the capping layer ranges from 5 nm to about 15 nm.

[0085] In some embodiments, the MTJ layer 418 includes a first ferromagnetic layer, a second ferromagnetic layer disposed on the first ferromagnetic layer, a first coupling layer disposed on the second ferromagnetic layer, a third ferromagnetic layer disposed on the first coupling layer, a second coupling layer disposed on the third ferromagnetic layer, a fourth ferromagnetic layer disposed on the second coupling layer, a first tunneling barrier layer disposed on the third ferromagnetic layer, a fifth ferromagnetic layer disposed on the first tunneling barrier layer, a second tunneling barrier layer disposed on the fifth ferromagnetic layer, and a capping layer disposed on the second tunneling barrier layer. In some embodiments, the first ferromagnetic layer includes NiCr, the second ferromagnetic layer includes CoPt, the first coupling layer includes Ru, the third ferromagnetic layer includes CoPt, the second coupling layer includes TaCo, the fourth ferromagnetic layer includes CoFeB, the first tunneling barrier layer includes MgO, the fifth ferromagnetic layer includes CoFeB, the second tunneling barrier layer includes MgO, and the capping layer includes Ru. In some embodiments, the thickness of the first ferromagnetic layer ranges from about 3 nm to about 7 nm, the thickness of the second ferromagnetic layer ranges from about 3 nm to about 7 nm, the thickness of the first coupling layer ranges from about 0.2 nm to about 1 nm, the thickness of the third ferromagnetic layer ranges from about 1.5 nm to about 3.5 nm, the thickness of the second coupling layer ranges from about 0.5 nm to about 1.5 nm, the thickness of the fourth ferromagnetic layer ranges from about 0.5 nm to about 1.5 nm, the thickness of the first tunneling barrier layer ranges from about 0.5 nm to about 1.5 nm, the thickness of the fifth ferromagnetic layer ranges from about 1 nm to about 3 nm, the thickness of the second tunneling barrier layer ranges from about 0.5 nm to about 1.5 nm, and the thickness of the capping layer ranges from 1 nm to about 3 nm.

[0086] Figure 4D This is a top view of the memory device 410. In some embodiments, the top electrode layer 414 has a first shape when viewed from the top, the MTJ layer 418 has a second shape when viewed from the top, and the bottom electrode layer 416 has a third shape when viewed from the top. In some embodiments, the first, second, and third shapes are identical. For example, the first, second, and third shapes are all circular, such as... Figure 4D As shown. In some embodiments, the first, second, and third shapes are all rectangles. In some embodiments, the first, second, and third shapes are different. For example, the first shape may be a circle, the second shape may be a circle, and the third shape may be a rectangle. Figure 4D As shown, in some embodiments, the diameter of the top electrode layer 414 is smaller than the diameter of the MTJ layer 418 and smaller than the diameter of the bottom electrode layer 416.

[0087] Figure 5 This is a cross-sectional side view of a semiconductor device structure 100 according to some embodiments. In some embodiments, one or more memory devices 410 are located in an IMD layer 402 one level below conductive features 405, such as... Figure 5As shown. In other words, a single IMD layer 402 is disposed between one or more memory devices 410 and conductive features 405, and conductive features 406 or conductive vias are disposed in the single IMD layer 402 to electrically connect one or more memory devices 410 and conductive features 405. In some embodiments, as described above, since conductive features 405 are located on the back side of device layer 200, the size of conductive features 405 is enlarged. The enlarged conductive features 405 can be electrically connected to multiple memory devices 410. Furthermore, the enlarged conductive features 405 can enable various arrangements of memory devices 410 with reduced parasitic capacitance. For example, in some embodiments, memory devices 410 are not perpendicularly aligned (along the Z direction) with the S / D region 106 of the device in device layer 200. In these embodiments, memory devices 410 are in Figure 5 The plane shown is not indicated.

[0088] Figure 6A and Figure 6B This is a bottom view of a semiconductor device structure 100 according to some embodiments. Figure 6A and Figure 6B The description includes the S / D region 106, gate electrode layer 136, conductive feature 405, memory device 410, conductive contact 407 connecting the S / D region 106 and conductive feature 405, and conductive feature 406 connecting conductive feature 405 and memory device 410. For clarity, other components of the semiconductor device structure 100 are omitted.

[0089] like Figure 6A As shown, the S / D region 106 is formed on the opposite side of the gate electrode layer 136. A conductive feature 405 is disposed below the S / D region 106 and the gate electrode layer 136. Figure 6A As shown, the conductive feature 405 may include a width along the Y direction, which is significantly larger than the width of the S / D region 106 along the Y direction. The width of the S / D region 106 may vary due to facets, such as... Figure 3A As shown. In some embodiments, the width of the conductive feature 405 may be greater than the maximum width of the S / D region 106. In some embodiments, the S / D region 106 is formed of a fin-shaped structure, and the width of the conductive feature 405 is significantly greater than the width of the fin-shaped structure. Figure 6A As shown, conductive feature 405 extends laterally into the region between adjacent fin structures. Therefore, conductive feature 405 does not interfere with conductive features 404, 406 that are electrically connected to the S / D region 106 located in the adjacent fin structures.

[0090] In embodiments where power rails are formed on the front side of device layer 200, the power rails may have the same width as the fin structure due to metal routing constraints. The power rails located on the front side of device layer 200 can be electrically connected to multiple source regions and multiple memory devices. Because the width of the front power rails is relatively small, the number of memory devices connected to the front power rails cannot exceed the number of source regions connected to the front power rails. For example, the front power rails may be electrically connected to two source regions, and at most two memory devices may be electrically connected to the front power rails.

[0091] Because the enlarged conductive feature 405 is located on the back side of the device layer 200, the number of memory devices 410 electrically connected to the conductive feature 405 can be significantly greater than the number of source regions electrically connected to the conductive feature 405. Furthermore, the memory devices 410 electrically connected to the conductive feature 405 can be arranged in a manner that minimizes parasitic capacitance. For example... Figure 6A As shown, multiple memory devices 410 are disposed below the conductive feature 405. The memory devices 410 are spaced apart and not disposed directly below the S / D region 106 to reduce parasitic capacitance. In other words, the memory devices 410 are offset from the S / D region 106 along the Z-direction. The term "offset" refers to the specific relationship along the Z-direction between the memory devices 410 and the S / D region 106 electrically connected to the memory devices 410, and the term "offset" is defined as the centerline of the memory devices 410 being located outside the plane defined by the outer edge of the S / D region 106. In some embodiments, the memory devices 410 are completely offset from the S / D region 106 to which the memory devices 410 are electrically connected. For example, the memory devices 410 and the electrically connected S / D region 106 do not overlap along the Z-direction. Figure 6A As shown, in some embodiments, conductive feature 405 is electrically connected to two source regions 106 via corresponding conductive contacts 407, and electrically connected to eight memory devices 410 via corresponding conductive features 406. Therefore, the number of memory devices 410 electrically connected to conductive feature 405 is at least twice the number of source regions 106 electrically connected to conductive feature 405, for example, about four times the number of source regions 106. In some embodiments, conductive feature 405 cannot be electrically connected to both the source region 106 and drain region 106 of the same transistor. The memory devices 410 are spaced apart to reduce parasitic capacitance. For example, as... Figure 6A As shown, the S / D region 106 (or fin structure) is located between adjacent memory devices 410 along the Y direction when viewed from the bottom, and the gate electrode layer 136 is located between adjacent memory devices 410 along the X direction when viewed from the bottom.

[0092] In some embodiments, such as Figure 6BAs shown, to further reduce parasitic capacitance, the number of memory devices 410 electrically connected to conductive feature 405 is approximately twice the number of source regions 106 electrically connected to conductive feature 405. In some embodiments, the semiconductor device structure 100 includes a first gate electrode layer 136a, a second gate electrode layer 136b disposed adjacent to the first gate electrode layer 136a, and a third gate electrode layer 136c disposed adjacent to the second gate electrode layer 136b, as shown. Figure 6B As shown. A first source region 106a is disposed on a first side of a first gate electrode layer 136a, and a first drain region 106b is disposed on a second side opposite to the first side of the first gate electrode layer 136a. The first drain region 106b is also disposed on a first side of a second gate electrode layer 136b, and a second source region 106c is disposed on a second side opposite to the first side of the second gate electrode layer 136b. The second source region 106c is also disposed on a first side of a third gate electrode layer 136c, and a second drain region 106d is disposed on a second side opposite to the first side of the third gate electrode layer 136c. The first source region 106a has a first side and a second side opposite to the first side, the first drain region 106b has a first side and a second side opposite to the first side, the second source region 106c has a first side and a second side opposite to the first side, and the second drain region 106d has a first side and a second side opposite to the first side. The orientation directions of the first and second sides of the first source region 106a, the second source region 106c, the first drain region 106b, and the second drain region 106d are substantially perpendicular to the orientation directions of the first and second sides of the first gate electrode layer 136a, the second gate electrode layer 136b, and the third gate electrode layer 136c. Furthermore, the first sides of the first source region 106a, the second source region 106c, the first drain region 106b, and the second drain region 106d are substantially aligned along the X direction, and the second sides of the first source region 106a, the second source region 106c, the first drain region 106b, and the second drain region 106d are substantially aligned along the X direction. In some embodiments, such as Figure 6B As shown, conductive feature 405 is electrically connected to the first memory device 410a, the second memory device 410b, the third memory device 410c, and the fourth memory device 410d. The first memory device 410a is disposed on the first side of the first source region 106a, the second memory device 410b is disposed on the second side of the first drain region 106b, the third memory device 410c is disposed on the first side of the second source region 106c, and the fourth memory device 410d is disposed on the second side of the second drain region 106d. This arrangement of the first to fourth memory devices 410a to 410d minimizes parasitic capacitance.

[0093] Figure 7This is a cross-sectional side view of a semiconductor device structure 100 according to an alternative embodiment. In some embodiments, one or more memory devices 410 are located in an IMD layer 402, which is located two or more layers below the conductive feature 405, such as... Figure 7 As shown. In other words, two or more IMD layers 402 are disposed between one or more memory devices 410 and conductive features 405. In some embodiments, conductive features 420 are formed in the two or more IMD layers 402 to electrically connect the conductive features 405 and the memory device 410, instead of using conductive features 404, 406. Figure 7 As shown, in some embodiments, a conductive feature 420 contacts one of the conductive feature 405 and the memory device 410. Compared to conductive features 404 and 406, a single conductive feature 420 has reduced resistance. In some embodiments, the conductive feature 420 is a supervia extending through multiple IMD layers 402.

[0094] In some embodiments, such as Figure 7 As shown, the memory device 410 and the conductive feature 404 are disposed in the same IMD layer 402, and the conductive feature 405 is disposed directly above the conductive feature 404 and the memory device 410. In some embodiments, three IMD layers 402 are disposed between the memory device 410 and the conductive feature 405, and between the conductive features 404 and 405. A single conductive feature 420 is disposed in the three IMD layers 402 to electrically connect the conductive feature 405 and the memory device 410. Multiple conductive features 404 and 406 are disposed in the three IMD layers 402 to electrically connect the conductive features 405 and 404, such as... Figure 7 As shown.

[0095] Figure 8A and Figure 8B This is a bottom view of a semiconductor device structure 100 according to an alternative embodiment. Figure 8A and Figure 8B The diagram describes the S / D region 106, gate electrode layer 136, conductive feature 405, memory device 410, and conductive feature 420 connecting conductive feature 405 and memory device 410. For clarity, other components of the semiconductor device structure 100 are omitted. In some embodiments, since the memory device 410 is located in a multilayer beneath the S / D region 106, the memory device 410 can be disposed directly beneath the S / D region 106 without increasing parasitic capacitance. Figure 8A As shown, four memory devices 410 are disposed directly below four S / D regions 106. Of the four S / D regions 106, two are source regions 106 and the other two are drain regions 106. In some embodiments, the two source regions 106 are connected via conductive contacts 407 (… Figure 7The gate electrode layer 136 is electrically connected to conductive feature 405, and conductive feature 405 is electrically connected to four memory devices via conductive feature 420. Therefore, the number of memory devices 410 electrically connected to conductive feature 405 is still at least twice the number of source regions 106 electrically connected to conductive feature 405. Furthermore, adjacent memory devices 410 are separated by at least the width of gate electrode layer 136, which further reduces parasitic capacitance.

[0096] In some embodiments, the memory device 410 is aligned along the X direction, such as Figure 8A As shown. In some embodiments, the memory device 410 is offset along the X direction, so more memory devices 410 can be placed below the conductive feature 405, such as... Figure 8B As shown. In some embodiments, the semiconductor device structure 100 includes a first gate electrode layer 136a, a second gate electrode layer 136b disposed adjacent to the first gate electrode layer 136a, and a third gate electrode layer 136c disposed adjacent to the second gate electrode layer 136b, as shown. Figure 8B As shown. A first source region 106a is disposed on a first side of the first gate electrode layer 136a, and a first drain region 106b is disposed on a second side opposite to the first side of the first gate electrode layer 136a. The first drain region 106b is also disposed on a first side of the second gate electrode layer 136b, and a second source region 106c is disposed on a second side opposite to the first side of the second gate electrode layer 136b. The second source region 106c is also disposed on a first side of the third gate electrode layer 136c, and a second drain region 106d is disposed on a second side opposite to the first side of the third gate electrode layer 136c. In some embodiments, as Figure 8B As shown, conductive feature 405 is electrically connected to the first memory device 410a, the second memory device 410b, the third memory device 410c, the fourth memory device 410d, the fifth memory device 410e, and the sixth memory device 410f. The first memory device 410a is located directly below the first source region 106a. The second memory device 410b and the third memory device 410c are located between the first and second gate electrode layers 136 when viewed from the bottom, while the first drain region 106b is located between the second memory device 410b and the third memory device 410c when viewed from the bottom. The fourth memory device 410d is located directly below the second source region 106c. The fifth memory device 410e and the sixth memory device 410f are located between the second and third gate electrode layers 136 when viewed from the bottom, while the second drain region 106d is located between the fifth memory device 410e and the sixth memory device 410f when viewed from the bottom. By utilizing this arrangement of memory devices 410a-f, parasitic capacitance is minimized.

[0097] Figures 9A to 9IThis is a cross-sectional side view of various stages in manufacturing a semiconductor device structure 100 according to some embodiments. Figure 9A As shown, a plurality of devices are formed on substrate 102 to form device layer 200, and an interconnect structure 300 is formed above device layer 200. The process for forming device layer 200 can be referred to as front-end-of-line (FEOL) process, while the process for forming interconnect structure 300 can be referred to as back-end-of-line (BEOL) process. In some embodiments, the process for forming conductive contacts 126 is referred to as middle-of-line (MOL) process.

[0098] Next, as Figure 9B As shown, a bonding layer 320 and a carrier wafer 330 are formed above the interconnect structure 300. The semiconductor device structure 100 is then flipped for back-side processing. Figure 9C As shown, the substrate 102 is thinned or removed. Next, as... Figure 9D As shown, a conductive feature 409 is formed through a portion of the substrate 102 and the IMD layer 302 to contact the conductive feature 304 formed in the interconnect structure 300. A conductive contact 407 is formed through the substrate 102 to electrically connect to the source region 106 (or the drain region 106). A conductive feature 405 is formed on the back side of the substrate 102 (or the back side of a dielectric material replacing the substrate 102), and the conductive feature 405 is electrically connected to the conductive feature 409 and the conductive contact 407. The IMD layer 402 is formed over the substrate 102, and a conductive feature 406 is formed over the conductive feature 405. Figure 9E As shown, conductive feature 404 is formed above conductive feature 406, and another IMD layer 402 is formed above conductive feature 404. At this stage, three IMD layers 402 are formed above conductive feature 405. In the first region above conductive feature 405, conductive features 404 and 406 are formed in the lower two of the three IMD layers 402, while no conductive feature is formed in the top of the three IMD layers 402, as shown. Figure 9E As shown. In the second region above the conductive feature 405, no conductive feature is formed in the three IMD layers 402.

[0099] Next, as Figure 9FAs shown, a conductive feature 406 is formed in a first region above conductive feature 405, and a conductive feature 420 is formed in a second region above conductive feature 405. Conductive features 406 and 420 can be formed by first forming openings in the first and second regions above conductive feature 405. The opening formed in the first region is shallower than the opening formed in the second region because the conductive feature 404 formed in the first region can serve as an etch stop layer. Next, conductive material is formed in the openings in the first and second regions above conductive feature 405 to form conductive features 406 and 420. A planarization process is performed to remove portions of the conductive material formed on the IMD layer 402.

[0100] like Figure 9G As shown, a bottom electrode layer 416, an MTJ layer 418, and a top electrode layer 414 are sequentially deposited over the IMD layer 402, conductive feature 406, and conductive feature 420. Next, the bottom electrode layer 416, MTJ layer 418, and top electrode layer 414 are patterned to form a memory device 410, as shown. Figure 9H As shown. The memory device 410 can be a planar MRAM. In some embodiments, a vertical MRAM can be formed. For example, an IMD layer 402 is formed on conductive features 406, 420, an opening is formed in the IMD layer 402, and a bottom electrode layer 416, an MTJ layer 418, and a top electrode layer 414 are formed in the opening to form a vertical MRAM. Figure 8A and Figure 8B The arrangement is shown.

[0101] In some embodiments, the memory device 410 is formed in a similar manner as a layer over the conductive feature 405, and the memory device 410 may be as follows: Figure 6A and Figure 6B The arrangement is shown.

[0102] Next, as Figure 9I As shown, the back-side interconnect structure 400 is completed, the semiconductor device structure 100 is flipped so that the interconnect structure 300 is disposed above the back-side interconnect structure 400, and the carrier wafer 330 and the bonding layer 320 are removed.

[0103] This disclosure provides a semiconductor device structure 100 in various embodiments, which includes a conductive feature 405 and memory devices 410 disposed in a back-side interconnect structure 400. Some embodiments offer advantages. For example, because the conductive feature 405 is formed in the back-side interconnect structure 400, the size of the conductive feature 405 is increased due to fewer routing constraints. The larger conductive feature 405 allows more memory devices 410 to be electrically connected to the conductive feature 405 with reduced parasitic capacitance.

[0104] One embodiment disclosed herein is a semiconductor device structure. The semiconductor device structure includes a plurality of source / drain regions, an interconnect structure disposed above the source / drain regions, a back-side interconnect structure disposed below the source / drain regions, and a first conductive feature disposed in the back-side interconnect structure. The first conductive feature is electrically connected to a first number of source / drain regions. The semiconductor device structure further includes a second number of memory devices disposed in the back-side interconnect structure, the memory devices being electrically connected to the first conductive feature, and the second number differing from the first number.

[0105] In some embodiments, the first quantity is 2, and the second quantity is 4, 6, or 8. In some embodiments, the semiconductor device structure further includes a first intermetallic dielectric layer disposed between the first conductive feature and the memory device, wherein the first conductive feature and the memory device are in contact with the first intermetallic dielectric layer. In some embodiments, the semiconductor device structure further includes a plurality of second conductive features disposed in the first intermetallic dielectric layer, wherein the memory device and the first conductive feature are electrically connected through the second conductive features. In some embodiments, the semiconductor device structure further includes a substrate, wherein source / drain regions are formed on the front side of the substrate, and the first conductive feature is in contact with the back side of the substrate. In some embodiments, the semiconductor device structure further includes one or more conductive contacts disposed in the substrate, wherein the first conductive feature is electrically connected to a first number of source / drain regions in the source / drain regions through the conductive contacts. In some embodiments, three intermetallic dielectric layers are disposed between the first conductive feature and the memory device. In some embodiments, the semiconductor device structure further includes a third conductive feature disposed in the three intermetallic dielectric layers, wherein the third conductive feature is electrically connected to one of the first conductive feature and the memory device.

[0106] Another embodiment disclosed herein is a semiconductor device structure. The semiconductor device structure includes a first source / drain region disposed above a substrate, and the first source / drain region has a first width. The semiconductor device structure further includes an interconnect structure disposed above the first source / drain region and a first conductive feature disposed below the back side of the substrate. The first conductive feature has a second width significantly larger than the first width, and the first conductive feature is electrically connected to the first source / drain region. The semiconductor device structure further includes a first intermetallic dielectric (IMD) layer disposed below the first conductive feature, a second IMD layer disposed below the first IMD layer, and a plurality of memory devices disposed in the second IMD layer. The memory devices are electrically connected to the first conductive feature and offset from the first source / drain region.

[0107] In some embodiments, the semiconductor device structure further includes a plurality of second conductive features disposed in a first intermetallic dielectric layer, wherein the memory device is electrically connected to the first conductive feature through the second conductive features. In some embodiments, the semiconductor device structure further includes a second source / drain region disposed above a substrate, a first gate electrode layer disposed between the first source / drain region and the second source / drain region, a third source / drain region disposed above the substrate, a second gate electrode layer disposed between the second source / drain region and the third source / drain region, a third gate electrode layer disposed near the third source / drain region, and a fourth source / drain region disposed above the substrate, wherein the third gate electrode layer is disposed between the third source / drain region and the fourth source / drain region. In some embodiments, the memory device includes a first memory device, a second memory device, a third memory device, and a fourth memory device. In some embodiments, the first source / drain region is disposed between the first memory device and the second memory device, and the second source / drain region is disposed between the third memory device and the fourth memory device. In some embodiments, the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region each have a first side and a second side opposite to the first side. The first sides of the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region are aligned, and the second sides of the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region are aligned. In some embodiments, a first memory device is disposed on the first side of the first source / drain region, a second memory device is disposed on the second side of the second source / drain region, a third memory device is disposed on the first side of the third source / drain region, and a fourth memory device is disposed on the second side of the fourth source / drain region. In some embodiments, a first gate electrode layer is disposed between the first memory device and the second memory device, a second gate electrode layer is disposed between the second memory device and the third memory device, and a third gate electrode layer is disposed between the third memory device and the fourth memory device.

[0108] Another embodiment disclosed herein is a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes the following steps: forming a plurality of source / drain regions above a substrate; forming an interconnect structure above the source / drain regions; flipping the substrate; forming a first conductive feature on the back side of the substrate; depositing a first intermetallic dielectric (IMD) layer on the first conductive feature; depositing a second IMD layer on the first IMD layer; depositing a third IMD layer on the second IMD layer; forming a second conductive feature in a first region above the first conductive feature that passes through the first, second, and third intermetallic dielectric layers; and forming a memory device on the second conductive feature.

[0109] In some embodiments, the method for forming a semiconductor device structure further includes forming a plurality of third conductive features in a first inter-metal dielectric layer, a second inter-metal dielectric layer, and a third inter-metal dielectric layer in a second region above the first conductive feature. In some embodiments, the third conductive feature includes: one or more first conductive vias formed in the first inter-metal dielectric layer; one or more conductive lines formed in the second inter-metal dielectric layer; and one or more second conductive vias formed in the third inter-metal dielectric layer. In some embodiments, the third conductive feature is formed prior to the step of forming the second conductive feature.

[0110] One embodiment disclosed herein is a semiconductor device structure. The semiconductor device structure includes a plurality of source / drain regions, an interconnect structure disposed above the source / drain regions, a back-side interconnect structure disposed below the source / drain regions, and a first conductive feature disposed in the back-side interconnect structure. The first conductive feature is electrically connected to a first number of source / drain regions. The semiconductor device structure further includes a second number of memory devices disposed in the back-side interconnect structure, the memory devices being electrically connected to the first conductive feature, and the second number differing from the first number. The semiconductor device structure includes three intermetallic dielectric layers disposed between the first conductive feature and the memory devices.

[0111] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to the equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized by, Include: Multiple source / drain regions; An interconnect structure is disposed above the plurality of source / drain regions; A back-side interconnect structure is disposed below the plurality of source / drain regions; A first conductive feature is disposed in the back-side interconnect structure, wherein the first conductive feature is electrically connected to a first number of source / drain regions in the plurality of source / drain regions; and A second number of memory devices are disposed in the back-side interconnect structure, wherein the memory devices are electrically connected to the first conductive feature, and the second number is different from the first number.

2. The semiconductor device structure of claim 1, wherein, The first quantity is 2, and the second quantity is 4, 6, or 8.

3. The semiconductor device structure of claim 1, wherein, The device further includes a substrate, wherein the plurality of source / drain regions are formed on a front side of the substrate, and the first conductive feature is in contact with a back side of the substrate.

4. The semiconductor device structure as described in claim 3, characterized in that, It further includes one or more conductive contacts disposed in the substrate, wherein the first conductive feature is electrically connected to the first number of source / drain regions among the plurality of source / drain regions through the one or more conductive contacts.

5. A semiconductor device structure, characterized in that, Include: A first source / drain region is disposed above a substrate, wherein the first source / drain region has a first width; An interconnect structure is disposed above the first source / drain region; A first conductive feature is disposed below a back side of the substrate, wherein the first conductive feature has a second width that is significantly larger than the first width, and the first conductive feature is electrically connected to the first source / drain region; A first intermetallic dielectric layer is disposed below the first conductive feature; A second intermetallic dielectric layer is disposed below the first intermetallic dielectric layer; and Multiple memory devices are disposed in the second intermetallic dielectric layer, wherein the multiple memory devices are electrically connected to the first conductive feature and are offset from the first source / drain region.

6. The semiconductor device structure as described in claim 5, characterized in that, Further includes: A second source / drain region is disposed above the substrate; A first gate electrode layer is disposed between the first source / drain region and the second source / drain region; A third source / drain region is disposed above the substrate; A second gate electrode layer is disposed between the second source / drain region and the third source / drain region; A third gate electrode layer is disposed near the third source / drain region; and A fourth source / drain region is disposed above the substrate, wherein the third gate electrode layer is disposed between the third source / drain region and the fourth source / drain region.

7. The semiconductor device structure as described in claim 6, characterized in that, The plurality of memory devices includes a first memory device, a second memory device, a third memory device, and a fourth memory device.

8. The semiconductor device structure as described in claim 7, characterized in that, The first source / drain region is located between the first memory device and the second memory device, and the second source / drain region is located between the third memory device and the fourth memory device.

9. The semiconductor device structure as claimed in claim 7, characterized in that, Each of the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region has a first side and a second side opposite to the first side. The first sides of the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region are aligned, and the second sides of the first source / drain region, the second source / drain region, the third source / drain region, and the fourth source / drain region are aligned.

10. A semiconductor device structure, characterized in that, Include: Multiple source / drain regions; An interconnect structure is disposed above the plurality of source / drain regions; A back-side interconnect structure is disposed below the plurality of source / drain regions; A first conductive feature is disposed in the back-side interconnect structure, wherein the first conductive feature is electrically connected to a first number of source / drain regions in the plurality of source / drain regions; A second number of memory devices are disposed in the back-side interconnect structure, wherein the memory devices are electrically connected to the first conductive feature, and the second number is different from the first number; and Three intermetallic dielectric layers are disposed between the first conductive feature and the memory device.

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